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path: root/src/import/chips/p9/procedures/hwp/perv
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* p9_sbe_nest_startclocks.C optimizedRaja Das2016-12-201-229/+95
* p9_sbe_chiplet_reset.C optimizedRaja Das2016-12-201-540/+476
* Update p9_clkoff_getreg/p9_ram_core proceduresLiuYangFan2016-11-301-3/+6
* Change auto variables to referencesspashabk-in2016-11-2215-82/+82
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2016-11-211-0/+32
* p9_sbe_attr_setup updatesAnusha Reddy Rangareddygari2016-11-211-0/+6
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-211-0/+4
* Add get XFVC in p9_clkoff_getreg and fix some issues in ramming procedureLiuYangFan2016-11-101-14/+131
* Move to additive multicast group setup for cores and caches in single modeGreg Still2016-11-092-79/+145
* sector buffer,pulse mode attributesAnusha Reddy Rangareddygari2016-11-082-0/+116
* Commit for PLL unlock error unmask in pcb slave config reg IPL xls Ver 222Srinivas Naga2016-11-082-0/+23
* p9_sbe_tp_chiplet_init1: Enable PCB automatic reset on timeoutJoachim Fenkes2016-11-041-0/+4
* Fix for premature SBE<>HB STOP 15 deadman exitGreg Still2016-11-041-1/+1
* p9_sbe_attr_setupAnusha Reddy Rangareddygari2016-11-041-13/+272
* Fix ramming procedure issueLiuYangFan2016-11-011-2/+2
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-10-281-1/+79
* Fixing order of setting clock muxes & functional reset & removing sim only scomsCHRISTINA L. GRAVES2016-10-271-40/+5
* p9_sbe_chiplet_reset -- correct swapped FBC early/early exit hang poll timersJoe McGill2016-10-251-4/+4
* p9_sbe_scominit update for Async MCAbhishek Agarwal2016-10-212-0/+136
* Change clock mux setting to targets PRESENTAnusha Reddy Rangareddygari2016-10-211-4/+4
* Cleaned old makefilesSachin Gupta2016-10-152-130/+0
* SBE compile issue fixedRaja Das2016-10-131-3/+0
* L2 version - p9_sbe_sequence_drtmSantosh2016-10-132-10/+132
* Level 1 HWP - p9_sbe_sequence_drtmSantosh2016-10-132-0/+115
* set TP scan ratio to 8:1 when running on PLLJoe McGill2016-10-131-5/+22
* p9_sbe_chiplet_reset -- adjust scan ratio for chiplets operating at PLL speedJoe McGill2016-10-101-12/+35
* Slowdown after L2cache CE injectSrinivas Naga2016-10-101-1/+12
* DD2 updates:p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2016-10-102-51/+32
* p9_sbe_check_master_stop15 fix for runningGreg Still2016-10-101-33/+55
* p9_sbe_nest_initf procedure update for EUH IO configAbhishek Agarwal2016-10-071-12/+32
* scan HWP updatesJoe McGill2016-10-035-306/+0
* Fixing collection code of perv targets functionalSoma BhanuTej2016-09-304-55/+19
* FFDC UpdatesAnusha Reddy Rangareddygari2016-09-266-38/+93
* I2C bit rate divisor updateAnusha Reddy Rangareddygari2016-09-231-25/+16
* Header file updates based on 9067 figtreeBen Gass2016-09-221-3/+2
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-09-211-2/+2
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-218-22/+21
* Removing checkstop checksAnusha Reddy Rangareddygari2016-09-204-54/+1
* Setup ATTR_OBUS_RATIO_VALUE for SBE platformThi Tran2016-09-191-1/+11
* FIR updatesJoe McGill2016-09-191-2/+2
* Adding in configurations for PNOR/LPC communicationCHRISTINA L. GRAVES2016-09-161-0/+40
* Update file headersSachin Gupta2016-09-1679-79/+79
* Multicast/L2loader updates.Ben Gass2016-09-141-207/+228
* PLL configuration updates -- permit e2e bypass executionJoe McGill2016-09-064-148/+214
* SBE move import`Shakeeb2016-09-0184-0/+12083
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