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path: root/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
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* p9_sbe_chiplet_reset: Remove SIM_ONLY conditional around delayJoachim Fenkes2018-01-131-3/+1
* remove NV iovalid assertion from FW and add scan inits to resolve glsmux xstateJoe McGill2017-11-281-12/+0
* Axone UpdateAnusha Reddy Rangareddygari2017-10-241-28/+68
* p9_sbe_chiplet_reset: Set VITL_AL flag for MC chipletsJoachim Fenkes2017-10-091-0/+5
* Update hardware procedure metadataAnusha Reddy Rangareddygari2017-10-041-1/+1
* resolve Zeppelin DMI channel framelock issuesJoe McGill2017-09-121-0/+18
* Create dmi.pll.scan.initfileBen Gass2017-07-141-2/+7
* Add PERV chiplet to MCGR 0Anusha Reddy Rangareddygari2017-07-131-0/+5
* p9_sbe_chiplet_reset updatesAnusha Reddy Rangareddygari2017-07-121-0/+2
* Update p9_sbe_chiplet_reset to support MV GSD2PIBAbhishek Agarwal2017-07-031-0/+2
* p9_sbe_chiplet_reset: Revert NX_1 hang pulse back to 34sJoachim Fenkes2017-05-041-3/+2
* using literal definitionsSoma BhanuTej2017-04-191-56/+51
* literal definitionsAnusha Reddy Rangareddygari2017-04-061-31/+33
* support customization of Nimbus DD1 PCI reference clock speedJoe McGill2017-03-311-0/+14
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-03-291-0/+37
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2017-03-231-3/+5
* Defer setup of MC multicast groups in async modeDean Sanner2017-02-241-0/+10
* adjust NV mesh control setup applicationJoe McGill2017-02-121-63/+0
* Control NDL training updateAnusha Reddy Rangareddygari2017-01-311-0/+65
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-01-241-68/+27
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-171-5/+27
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2017-01-041-16/+25
* update core internal/external hang timeoutsJoe McGill2016-12-201-1/+1
* p9_sbe_chiplet_reset.C optimizedRaja Das2016-12-201-540/+476
* Change auto variables to referencesspashabk-in2016-11-221-33/+33
* Move to additive multicast group setup for cores and caches in single modeGreg Still2016-11-091-16/+28
* sector buffer,pulse mode attributesAnusha Reddy Rangareddygari2016-11-081-0/+63
* p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-10-281-1/+79
* p9_sbe_chiplet_reset -- correct swapped FBC early/early exit hang poll timersJoe McGill2016-10-251-4/+4
* Change clock mux setting to targets PRESENTAnusha Reddy Rangareddygari2016-10-211-4/+4
* p9_sbe_chiplet_reset -- adjust scan ratio for chiplets operating at PLL speedJoe McGill2016-10-101-12/+35
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-1/+1
* Multicast/L2loader updates.Ben Gass2016-09-141-207/+228
* SBE move import`Shakeeb2016-09-011-0/+1330
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