| Commit message (Collapse) | Author | Age | Files | Lines |
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Also initial mk files for p9n 2.3, but p9c 1.2 will be first.
Change-Id: Ia73aba37be5bcf64b1b2cfe5b1ed153b189c7777
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53909
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54542
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This setting improves tlbie latencies that were measured on IBMi.
Also commit generated initfile changes causing Jenkins compliation
failure.
Change-Id: I206fa3c8f07859d44f6f82f3eadebf6f11352637
CQ: HW438757
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54157
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54179
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The original patch: https://ralgit01.raleigh.ibm.com/gerrit1/#/c/45266/
was merged prematurely.
It was reverted in: https://ralgit01.raleigh.ibm.com/gerrit1/#/c/50703/
pre-commit-actions updated to call code-beautifier twice. Some generated
code for initfiles changes between first and second passes.
Change-Id: I25bdc2ceaf9636a2f6559775bc8cb9616848c9d7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50741
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50961
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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chip_ec_attributes.xml
add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need
MCD disable for HW423589 (applied to Nimbus EC20 and 22+)
p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scan.initfile
p9.l3.scan.initfile
p9.mmu.scom.initfile
p9.ncu.scan.initfile
p9.npu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_pcie_config.C
set unit scope disable dials
p9_sbe_scominit.C
p9_pm_pba_init.C
set PBA unit scope disable dial
p9_pm_set_homer_bar.C
change PBA0 default command scope from GROUP to NODAL
p9.fbc.ab_hp.scom.initfile
disable group master setup
p9_setup_bars.C
p9_setup_bars_defs.H
skip MCD setup for HW423589_OPTION1
cmvc-prereq: 1043014
Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Nimbus DD2.0 disable will go into op910 only (for Boston Coral)
but not into master
Change-Id: I28376316be3e6700af97df83a02c48e46d715dec
CQ: HW415945
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50445
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50453
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The PCIe timeout have increased to 66-100ms, so we need to double
the NCU master timeouts to be above these timeouts. This has a
chain effect causing the L2/L3 master timeouts to increase which
causes the tlbie snooper to increase which causes the tlbie master
to increase.
This would also ususally cause the core timeout to increas, but
the core is already at around 13 seconds, so there is headroom
there.
Change-Id: I5930076151267a9bfa66e24edef0985c165db0b7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50582
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50602
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This reverts commit 41352b2d444e98639eedc06b1eb0d8da89d4adb3.
Change-Id: Ic3f2099eff3f5c942ef8fb6916e8ee78ca1a9e82
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50703
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50722
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Adding CTEPERLPATH to ENV-setup
Jenkins failure CQ SW40996
Change-Id: I02a9c5f31fb0545e8f8c8cd99b528a467ae52cf8
CQ: SW409966
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45266
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50688
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Performance wants a way to turn memory early data on & off
using just scoms. Adding one attribute to control all the needed
scoms and defaulting everything so that early data is off.
For the L3 disable cp_me by default using scom
Changing the scom cp_me dial to disable cp_me for all systems
after Nimbus DD2.0. This is expected to be the correct setup
for most systems.
We didn't disable the cp_me at the scan, because the scom can
only disable cp_me if ON or allow the scan setting if set OFF. Some
systems might want cp_me enabled by only changing a scom. So the default
is to set cp_me on at the scan and off a the scom. This way only the
scom has to be turned off to enable cp_me.
Also update three scoms in the memory controler that are needed for
early data.
Change-Id: Ib2106ec4b7d26cb084601f2d6eee68833b36d30b
CQ: HW426419
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49261
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49331
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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chip_ec_attributes.xml
nest_attributes.xml
p9_sbe_attributes.xml
add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines
set of chips which physically support the feature
add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips
which need extended address workaround for MCD issue (applied only
to Nimbus EC 21)
add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of
memory groups formed. Written by p9_mss_eff_grouping. For
HW423589_OPTION2, this will default to 512GB
add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold
extended address configuration. Written by p9_sbe_fabricinit (SBE)
and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will
default to 0b0000_111, consuming all chip ID bits for extended
addressing.
p9_fbc_utils.C
p9_fbc_utils.H
extend p9_fbc_utils_get_chip_base_address to support address
extension, now outputs set of ranges in each msel based on
ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID
maintain original function for PPE platform which requires
knowledge of non-aliased base addresses only, for code size
p9_mss_eff_grouping.C
p9_mss_eff_grouping_errors.xml
set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform
restrict size of groups formed for HW423589_OPTION2
p9_sbe_fabricinit.C
set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform
configure FBC/NMMU extended addressing registers
p9_setup_bars.C
p9_setup_bars_defs.H
p9_setup_bars_errors.xml
add general purpose support for extended address mode
for HW423589_OPTION2, configure static MCD setup
p9_hcode_image_defines.H
p9_hcode_image_build.C
customize SGPE image with address extension configuration to apply
p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scom.initfile
p9.l3.scom.initfile
p9.ncu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_hcd_cache_scominit.C
p9_hcd_cache_scominit.c
p9_pcie_config.C
set unit address extension configuration on supported chips
p9_rng_init_phase2.C
p9_sbe_scominit.C
p9c_set_inband_addr.C
p9_sbe_load_bootloader.C
p9_sbe_mcs_setup.C
adapt to alterations in p9_fbc_utils_get_chip_base_address
Change-Id: I614d566c073f1169f04f647057e6e85889f1c237
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48892
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I3212489668cf33978854b4767dc307c7f7f0fe99
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49103
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49107
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: If9ffe53acd009c1520cdd7f162e88fd235799225
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46361
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48896
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I954651af59c18401a9bd5f389f86b8faf799edbd
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48817
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48821
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- chips.env.mk
- makefile changes for CME,PGPE and SGPE
Change-Id: I7086a08de6d2b53d8051f64bed01fe525183aacd
RTC:179165
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45289
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45432
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Conflicting dd1 only dials for these were removed:
ATTR_CHIP_EC_FEATURE_HW396288
ATTR_CHIP_EC_FEATURE_HW399624
ATTR_CHIP_EC_FEATURE_HW393578
ATTR_CHIP_EC_FEATURE_HW403075
ATTR_CHIP_EC_FEATURE_HW393318
ATTR_CHIP_EC_FEATURE_HW394497
Work around for HW408891 is contained within HW416934 update.
Change-Id: I8cb266893d802f1673f683f17fd231e17de1cfa1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46177
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46180
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Dial getting overwritten by a global dial; moving both to scan inits
Change-Id: Ia16a78c146b88f21325a4b1e619a5bf4df5328d7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45306
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Emmanuel Sacristan <esacris@us.ibm.com>
Dev-Ready: Emmanuel Sacristan <esacris@us.ibm.com>
Reviewed-by: JAKE C. TRUELOVE <jtruelove@us.ibm.com>
Dev-Ready: JAKE C. TRUELOVE <jtruelove@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45311
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- Adjusted master tlbie timeout from 16->32 (250ms->500ms)
- Enabled tlbie stall mechanism by default
Change-Id: Ifcda75f42ba888ad5353c1d9b75d36e27d48dbda
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44713
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44714
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_mmu_scom is called in p9_sbe_scominit, but ATTR_PROC_EPS_WRITE_CYCLES_T1/2
does not get set until later in the IPL sequence.
Moving initialization of mmu write epsilon values to p9_chiplet_scominit.C
Change-Id: Ibf325fc4b132070b95ea3f55b92090109ab30406
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43210
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43214
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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fir_nmmufir.xml:
bit 9: recoverable, self_th_1
bit 10: mask
fir_nmmucqfir.xml
bit 4 - recoverable, self_th_1
bit 5 - masked
bit 11 - recoverable, threshold_and_mask
bit 15 - recoverable, threshold_and_mask
bit 29 - masked
bit 37 - recoverable, self_th_1
bit 45 - masked
rebase to pick up changes for HW414700, apply for DD2.0 only
Change-Id: I1164cefddab6ba693050dd07b10ffc8e28ae586b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42953
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42956
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I93f995e1c63f376906efc2bad24aa2c5728702fb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42934
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43113
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Core
ECP.PC.FIR.THRESHOLD_RESET = 0b00 to disable
CXA, L2, L3, NMMU, NX, VAS, FBC, MC FIR changes to checkstop on UE at source
Change-Id: I4400acb7d3ec68cced49adb5a77fec7bd8356d40
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42887
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42942
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Core:
- Mask bit 57 to match XML specification
L2:
- Mark bit 18 recoverable (core initiated non-CI store)
- Update XML description for bit 23
- Mark bit 25 checkstop (castout)
NCU:
- Mark bit 3,4 recoverable (core initiated CI store, load)
- Mark bit 7 recoverable (core initiated msg send)
- Mark bit 12 checkstop (IMA)
- Mark bit 15, 16 checkstop (PPE)
- Mark bit 21 recoverable (darn = core initiated CI load)
Change-Id: I620b98e4542bfde7524f4f13dc18fd1868adfd81
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42522
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Daniel J. Henderson <hende@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42789
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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L3_REF_TIMER_DIVIDE_MINOR needs to be left at default value of
Divide by 10 for DD1.X, DD2.0 due to bug
Change-Id: I9bfbf243ecf854c2375e852f60d0bcb47812fe87
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41893
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41899
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Remove ATTR for HW396388; EN_ATTN is needed for all chips
Mask PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR for SW390012
Change-Id: I70280ca7dfdd22ee88780c8cf76444283d1a4213
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41646
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41647
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The following should apply to all chips/systems.
1) Set edram refresh divider to optimal value based on
pb frequency
2) performance fix for castout pacing. Base value was too
high.
Change-Id: I7f280f9826ba7483a31b64aca5caf36affaea843
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41248
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41253
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- Update *.mk files to support p9c chip ID
- Workaround some spy issues p9c 10 engd issues
- Fix bug to allow compilation without ENGD
Change-Id: Ie94b55c93081108668725d3ee9b88bd34eaa794f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40904
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40952
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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redefine EC feature attributes, using inverse logic where required, to qualify
inits specific to P9N DD1 where possible, to eliminate need for updates for
future chips in plan
attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES
attributes added to support initial P9NDD2 engineering data -- several spies
were not being set as a result
-----------------
initfile updates:
-----------------
p9.cme.scan.initfile
add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes
p9.core.common.scan.initfile
remove fused core init, it was applying scan default for P9N DD1 and is
not needed for P9N DD2+ given fuse controls
p9.core.scan.initfile
add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and
dial programming
replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1
and inverse, to pick up initial pass at P9C DD1 inits
p9.cxa.scom.initfile
add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy
p9.ddrphy.scom.initfile
add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy
p9.dpll.scan.initfile
remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS
attribute and inverse to drive inits
p9.l2.scan.initfile
invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes
p9.l3.scan.initfile
p9.l3.scom.initifle
remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes
use HW386657, HW396230 attributes to drive inits
p9.mca.scom.initfile
add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing
programming and dial name differences between P9N DD1, P9N DD2
p9.mmu.scan.initfile
p9.mmu.scom.initfile
invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes
p9.ncu.scan.initfile
p9.ncu.scom.initifle
remove HW396230_SCOM, use HW396230 attribute to drive inits
p9.npu.scom.initfile
remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification
to work for both P9NDD1, P9NDD2 ENGD
p9.obus.scan.initfile
remove EC qualification of OBUS FIR mask for simulation
sample.ec.scan.initfile
remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of
testcase are covered by other tests
-----------------
HWP updates:
-----------------
p9_xip_customize
add customization of epsilon attributes for NMMU application
p9_chiplet_scominit
invert definition of P9_NDL_IOVALID feature attribute
remove usage of P9N_DD1_SPY_NAMES
p9_npu_scominit
replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR
p9_sbe_tracearray
invert definition of CORE_TRACE_SCOMABLE feature attribute
p9_sim_get_nia
remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes
(ok as this HWP is used for VBU sim only and not consumed by FW)
Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40915
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I4a60be950fd5866a15f4c69f2c587a60b5620a2c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40389
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40392
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I4b9296793fc8802f03bfebcb46446c8bc1a1d4e3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39782
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39859
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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1) L3_CERRS_LRU_DECR_PROB_SEL_CFG should be left at default value
and not altered
3) HW375255 should be applied to all systems since rejected by ccb
4) rddsp_demotion_init_lru_cnt_cfg performance chages
Change-Id: Ic36f360da342c8f98e940642b15111d0540ddfc6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39577
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39606
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Id0eb9af939ebc6ca35afdaca0bdc358be016ddea
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37132
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37137
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I712de1525c1094f084cb24af77e78e231420eaf9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38944
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: JOSHUA L. HANNAN <jlhannan@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38946
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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There are several dials in the caches that change what value
they are set to based on the epsilon divider dial setting.
To simplify, I've added a variable that controls all of these
dial settings.
Change-Id: I8f7030bd56900a228475bac5d890a30db8c4dc18
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38842
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38845
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The epsilon attribute value is the number of cycles the caches
needs to wait, but this isn't one-to-one for what needs to be in
the cache dials. Needed to update the equation in the initfile.
Change-Id: Ia5809018a7dfb22e27ae4775bc5146d2a2381ce7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36814
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36816
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Enabling 20 caused generated initfile procedures to
change.
Chip target needed to be added to p9.fbc.ioo_dl.scom.initfile
Change-Id: Id24aa67f8d2c3f07ef85ed3bf8a555c85b4a0d72
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38324
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38328
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-Branch based on scom address changes
-Update error cases for missing/unsupported spys
RTC:163767
Change-Id: Ifc2b5b05a4cd3397125962959c7113da965e988b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35507
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35509
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_obus_scom_address_fixes.H
add OBUS IO PPE address constants
p9.cme.scan.initfile
align EQ pervasive LFIR/XFIR settings with RAS XML docs
p9.core.scan.initfile
align EC pervasive LFIR/XFIR settings with RAS XML docs
p9.core.scom.initfile
p9_hcd_core_scominit.c
adjust core FIR action settings for bits 1,12:13 to match RAS XML doc
p9_sbe_scominit.C
mask PBA FIR bit 1 to match RAS XML doc
initialize FBC/XBUS/OBUS PPE FIR registers
p9_sbe_common.C
align non-EQ/EC pervasive LFIR/XFIR settings with RAS XML docs
CMVC-prereq:1014393
CMVC-prereq:1014431
Change-Id: Ifbc6a47eb2dbe268a7ea832e55986d46a1870420
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34271
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34336
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The L2 dial is a scomable dial for DD1, but the NCU and L3
dials are not scan only for DD1. So the NCU and L3 have two
dials one used in DD1 and one for after DD1.
Change-Id: Ica63b417ae79b3b5a230c8034fd6f76b982df23b
RTC: 167679
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34857
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35108
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ia4e69cf50548e355cfb7cbf5e67be48e61427ffa
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34318
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34348
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Unmask tc_fir_xstop for non-cache contained runs
Change-Id: Ied34464771d8468718f2d86e48b214b707590fed
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34011
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34569
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ib2e652ad78971ac12084ce1053101c081c34b590
RTC:165584
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33566
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33568
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-Update code generation to wrap getScom/putScom getSpy/putSpy
calls in FAPI_TRY macro to save space and be consistient with
the existing hwp procedure style.
Change-Id: I37975ec424b2b369cec200ddef8a05e650954c38
RTC:165557
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33557
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33561
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Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-When refactoring the code to support iterating over EC levels
the optimization implemented to consolidate writes to the same
scom address was inadvertently removed, this commit restores
that optimization.
Change-Id: I43109b6c1e7ed2d4ed2f84f429f86cbe50553f88
RTC:164881
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33379
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Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33380
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-Add support for looping over various EC levels for
SCOM and Scan init files
Change-Id: I7463b71698856922829cddc0e4d8d179803a1db8
RTC:159043
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31688
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31874
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: If3ecb49a4a7d0df3389a6420a72714c860c9f1ea
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31793
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Iabcd4700c79a9542e70ab341d52a4c4f9090b99e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31293
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Change-Id: Ie36fe166916e4e49d34a1e892022ea0a2f55753e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31208
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1. Added HW372116 fix to INT initfile
2. Changes to NX FIR actions, fix to disable abc checker
3. Added Issue 632 fix to MMU initfile
Change-Id: I00a1b646738decefef9e540f655d5d9d0a825744
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29768
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Reviewed-by: Emmanuel Sacristan <esacris@us.ibm.com>
Reviewed-by: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com>
Dev-Ready: CHRISTOPHER D. HANUDEL <chanudel@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31205
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
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Change-Id: Iee61f2987f192790c16685f51ac03fe840acf819
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28954
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
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> Implementing bits definition in nx initfile
> Modifying fir values in mmu initfile to compensate for deadbits
Change-Id: I79e7ffb367db2a3505a25d3e0455c5f875e5304a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28451
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31203
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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