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| author | Luke C. Murray <murrayl@us.ibm.com> | 2017-06-27 16:20:22 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-12 01:04:32 -0400 |
| commit | 640e5681c54baf9b044c409f28a6d3560a4112af (patch) | |
| tree | f86b2bc1961f22044447c8520ddf461897fbb25f /src/import/chips/p9/procedures/hwp/initfiles | |
| parent | 7b91ce9772681a55539550c2260d73cfec2a0cce (diff) | |
| download | talos-sbe-640e5681c54baf9b044c409f28a6d3560a4112af.tar.gz talos-sbe-640e5681c54baf9b044c409f28a6d3560a4112af.zip | |
Quad FIR updates for Nimbus DD2, MPIPL
Core:
- Mask bit 57 to match XML specification
L2:
- Mark bit 18 recoverable (core initiated non-CI store)
- Update XML description for bit 23
- Mark bit 25 checkstop (castout)
NCU:
- Mark bit 3,4 recoverable (core initiated CI store, load)
- Mark bit 7 recoverable (core initiated msg send)
- Mark bit 12 checkstop (IMA)
- Mark bit 15, 16 checkstop (PPE)
- Mark bit 21 recoverable (darn = core initiated CI load)
Change-Id: I620b98e4542bfde7524f4f13dc18fd1868adfd81
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42522
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Daniel J. Henderson <hende@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42789
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/initfiles')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C index afb1c8d8..34d8bf97 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_core_scom.C @@ -29,7 +29,7 @@ using namespace fapi2; -constexpr uint64_t literal_0x0301D70000AB76B6 = 0x0301D70000AB76B6; +constexpr uint64_t literal_0x0301D70000AB76F6 = 0x0301D70000AB76F6; constexpr uint64_t literal_0x0000000000000000 = 0x0000000000000000; constexpr uint64_t literal_0xA854009775100008 = 0xA854009775100008; @@ -40,7 +40,7 @@ fapi2::ReturnCode p9_core_scom(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& TGT { FAPI_TRY(fapi2::getScom( TGT0, 0x20010a43ull, l_scom_buffer )); - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0301D70000AB76B6 ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0301D70000AB76F6 ); FAPI_TRY(fapi2::putScom(TGT0, 0x20010a43ull, l_scom_buffer)); } { |
