summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/hwp/cache
Commit message (Expand)AuthorAgeFilesLines
* p9_hcd_cache_chiplet_reset skip entire vcs workaround in simBen Gass2016-12-201-99/+95
* Istep4: Shouldn't set group_id in cache-contained modeYue Du2016-12-201-7/+11
* Change auto variables to referencesspashabk-in2016-11-224-4/+4
* Fence fixes for L2 loader and Run-N.Ben Gass2016-11-211-0/+32
* STOP Image updatesYue Du2016-11-211-5/+4
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-214-17/+33
* HB: fix HB core boot resulting cme bootYue Du2016-11-101-0/+15
* Istep4: add L3-LCO target setup to cache_scominitYue Du2016-11-091-7/+71
* cache/core/l2_stopclocks updatesYue Du2016-10-262-43/+103
* Skip flushing entire eq ring to 1's in sim p9_hcd_cache_chiplet_resetBen Gass2016-10-211-2/+28
* Cleaned old makefilesSachin Gupta2016-10-152-113/+0
* Lab: DD1 VCS workaround fixYue Du2016-10-143-42/+48
* HW388878 VCS workaroundJoe McGill2016-10-122-2/+2
* Cache HWP: DD1 VCS WorkaroundYue Du2016-10-113-1/+200
* Stop Clocks for MPIPL (Core & Cache(EQ))Raja Das2016-10-061-0/+2
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-4/+1
* Fix for the EKB build failure caused by hcd constantSangeetha T S2016-09-202-2/+4
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2016-09-204-17/+290
* Level 1 HWP for p9_stopclocksSoma BhanuTej2016-09-202-7/+3
* CORE/CACHE: add Level1 cache/l2/core stopclocks proceduresYue Du2016-09-204-0/+255
* Update file headersSachin Gupta2016-09-1631-31/+31
* Multicast/L2loader updates.Ben Gass2016-09-141-4/+27
* PLL configuration updates -- permit e2e bypass executionJoe McGill2016-09-061-28/+43
* SBE move import`Shakeeb2016-09-0133-0/+3149
OpenPOWER on IntegriCloud