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* Add attribute file for cache-contained specific behaviorJoe McGill2016-06-081-0/+46
* p9_ringId.H: resolve duplicate copies of fileMartin Peschke2016-06-081-248/+0
* Translate logical mca regisers in mcs chiplet as mca target typeBen Gass2016-06-081-0/+5
* p9_psi_init -- adjust iovalid control, fix todosJoe McGill2016-06-081-1/+23
* Level 2 HWP for p9_sbe_nest_startclocks,p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2016-06-089-477/+445
* p9_block_wakeup_intr Level 2 - fix PPE compilation issueGreg Still2016-06-082-3/+9
* p9_block_wakeup_intr Level 2Greg Still2016-06-081-37/+87
* Update makefile for new procedures.Sachin Gupta2016-06-081-0/+2
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2016-06-082-0/+131
* Level 1 HWP for p9_hcd_cache_chiplet_l3_dcc_setupAnusha Reddy Rangareddygari2016-06-082-0/+101
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-06-084-77/+243
* partial good/hang pulse updates to support all sim models/clock ratiosJoe McGill2016-06-083-5/+30
* Changes in error handling to stop the read/write as soon as an error occursCHRISTINA L. GRAVES2016-06-082-3/+5
* Adding in LPC functional reset to sbe_lpc_initCHRISTINA L. GRAVES2016-06-082-9/+8
* ADU SupportRaja Das2016-06-083-1/+4
* Update RAM procedures.LiuYangFan2016-06-083-157/+521
* p9_pm_occ_control Fix OCC memory boot launchingGreg Still2016-06-081-1/+32
* Initial check in of xip_tool changes needed to support anotherClaus Michael Olsen2016-06-082-2643/+3
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-06-082-1/+133
* Define attributes for synchronous modeDan Crowell2016-05-201-1/+1
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-05-203-2/+29
* ADU: Support PMISC NHTM control operationsThi Tran2016-05-202-14/+42
* p9_sbe_tp_switch_gears -- skip i2c access outside of SBE platformJoe McGill2016-05-201-10/+3
* p9.core.common.initfile -- clear PSSCR[RL] for cache contained modeJoe McGill2016-05-201-1/+1
* p9_pm_corequad_init: Level 2 - Fapi 1.0 to Fapi 2.0 transliterationSangeetha T S2016-05-201-0/+2350
* Updated attribute valuesSoma BhanuTej2016-05-171-1/+1
* Level 2 HWP for p9_sbe_attr_setup,p9_setup_sbe_configAnusha Reddy Rangareddygari2016-05-166-57/+154
* add core/cache initfilesJoe McGill2016-05-161-6/+66
* Level 2 HWP for p9_sbe_tp_chiplet_init3Soma BhanuTej2016-05-131-26/+49
* Tod init and tod setup L2 proceduresCHRISTINA L. GRAVES2016-05-131-0/+11
* Move array of OP_TYPE strings from .H to .Ccrgeddes2016-05-131-1/+11
* Fix all incorrect copyright prologsStephen Cprek2016-05-131-1/+1
* p9_block_wakeup_intr Level 1Bilicon Patil2016-05-131-0/+107
* invoke cache SCOM initfilesJoe McGill2016-05-111-1/+40
* Pervasive_attribute.xml with ATTR_SDISN_SETUPAnusha Reddy Rangareddygari2016-05-111-0/+1
* Enable p9_block_wakeup_intrSachin Gupta2016-05-092-0/+2
* p9_block_wakeup_intr Level 2Greg Still2016-05-092-14/+32
* Move array of OP_TYPE strings from .H to .Ccrgeddes2016-05-091-8/+1
* Fix all incorrect copyright prologsStephen Cprek2016-05-091-1/+0
* p9_block_wakeup_intr Level 1Bilicon Patil2016-05-092-0/+126
* HWP's for p9_perv_sbe_cmn,p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2016-05-098-93/+183
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-05-091-6/+6
* Infrastructure updates to build cache initfile HWPs in import treeJoe McGill2016-05-062-0/+49
* change epsilon attribute definitions from arrays to scalarsJoe McGill2016-05-064-54/+150
* IPL optimized codesAnusha Reddy Rangareddygari2016-05-058-946/+558
* Level 2 HWP for p9_sbe_chiplet_pll_setupAnusha Reddy Rangareddygari2016-05-051-56/+141
* Changing error messages to save SBE spaceCHRISTINA L. GRAVES2016-05-051-33/+2
* add core/cache initfilesJoe McGill2016-05-046-0/+757
* Level 2 HWP for p9_sbe_nest_startclocksAnusha Reddy Rangareddygari2016-05-041-40/+40
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-05-041-9/+10
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