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| author | Thi Tran <thi@us.ibm.com> | 2016-05-17 15:34:49 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-05-20 05:14:18 -0400 |
| commit | 589e5a88ad3f6b58cbf4a816b2ccb0448bf07243 (patch) | |
| tree | 06ad85b621c35e09b0506e540a932520561d1ca5 /import/chips | |
| parent | 01fd4d1872bc675bf05b4c58123acc826b459c69 (diff) | |
| download | talos-sbe-589e5a88ad3f6b58cbf4a816b2ccb0448bf07243.tar.gz talos-sbe-589e5a88ad3f6b58cbf4a816b2ccb0448bf07243.zip | |
ADU: Support PMISC NHTM control operations
Change-Id: Ife477914e9343ff70e7088c51fbd3a3ecde09167
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24682
Tested-by: Jenkins Server
Tested-by: PPE CI
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24683
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips')
| -rw-r--r-- | import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C | 34 | ||||
| -rw-r--r-- | import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H | 22 |
2 files changed, 42 insertions, 14 deletions
diff --git a/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C index a6d9fae2..94dcfcc0 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C +++ b/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C @@ -78,7 +78,6 @@ extern "C" const uint32_t ALTD_CMD_TSIZE_START_BIT = 32; const uint32_t ALTD_CMD_TSIZE_END_BIT = 39; - const uint32_t ALTD_CMD_SCOPE_NUM_BITS = (ALTD_CMD_SCOPE_END_BIT - ALTD_CMD_SCOPE_START_BIT) + 1; const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT - @@ -108,11 +107,14 @@ extern "C" //I think that the secondary encoding should always be 0 for cl_dma_rd const uint32_t ALTD_CMD_DMAR_TSIZE = 0; - // Values for PB/SWITCH operations + // Values for PB operations const uint32_t ALTD_CMD_PB_OPERATION_TSIZE = 0b00001000; - const uint32_t ALTD_CMD_SWITCH_ACTION_TSIZE = 0b00000010; const uint32_t ALTD_CMD_SCOPE_SYSTEM = 0b00000101; + // Values for PMISC operations + const uint32_t ALTD_CMD_PMISC_TSIZE_1 = 0b00000010; // PMISC SWITCH + const uint32_t ALTD_CMD_PMISC_TSIZE_2 = 0b01000000; // PMISC HTM + // OPTION reg values for SWITCH operation const uint32_t QUIESCE_SWITCH_WAIT_COUNT = 128; const uint32_t INIT_SWITCH_WAIT_COUNT = 128; @@ -347,17 +349,17 @@ extern "C" } // Set TSIZE - if ( l_transSize == FLAG_SIZE_TSIZE_1 ) + if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) { altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_1); } - else if ( l_transSize == FLAG_SIZE_TSIZE_2 ) + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) { altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_2); } - else if ( l_transSize == FLAG_SIZE_TSIZE_4 ) + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 ) { altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_4); @@ -392,17 +394,17 @@ extern "C" ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_DMA_PR_WR); // Set TSIZE - if ( l_transSize == FLAG_SIZE_TSIZE_1 ) + if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) { altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_1); } - else if ( l_transSize == FLAG_SIZE_TSIZE_2 ) + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) { altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_2); } - else if ( l_transSize == FLAG_SIZE_TSIZE_4 ) + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 ) { altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_4); @@ -474,9 +476,17 @@ extern "C" altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PMISC_OPER); - // TSIZE for PMISC operation is fixed value: 0b00000010 - altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, - ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_SWITCH_ACTION_TSIZE); + // Set TSIZE + if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_1); + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_2); + } // Set quiesce and init around a switch operation in option reg FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error"); diff --git a/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H index c8caeba3..9c5eaf6d 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H +++ b/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H @@ -508,8 +508,26 @@ extern"C" iv_eccItagOverwrite = (i_flag & FLAG_OVERWRITE_ECC); // Transaction size - iv_transSize = static_cast<Transaction_size_t> - ( (i_flag & FLAG_SIZE) >> FLAG_ADU_SIZE_SHIFT ); + if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_1 ) + { + iv_transSize = TSIZE_1; + } + else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_2 ) + { + iv_transSize = TSIZE_2; + } + else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_4 ) + { + iv_transSize = TSIZE_4; + } + else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_8 ) + { + iv_transSize = TSIZE_8; + } + else + { + FAPI_ERR("Invalid transaction size: iv_transSize %d", iv_transSize); + } // Debug trace FAPI_DBG("p9_ADU_oper_flag::getFlag() - Flag value 0x%.8X", i_flag); |
