diff options
Diffstat (limited to 'src/import/chips/p9')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C | 15 | ||||
-rw-r--r-- | src/import/chips/p9/sw_simulation/powermgmt.act | 9 |
2 files changed, 18 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C index 44d711b0..ed7c0e83 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C @@ -457,16 +457,19 @@ fapi2::ReturnCode p9_sbe_select_ex( "The cache chiplet associated with the first good core not functional"); // Write to the OCC Core Configuration Status Register - FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_CCSR_SCOM2, l_core_config)); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_CCSR_SCOM, l_core_config)); // Write to the OCC Quad Configuration Status Register - FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QCSR_SCOM2, l_quad_config)); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QCSR_SCOM, l_quad_config)); - // Set (via OR Write) the default value the OCC Quad Status Status Register + // Write the default value of the OCC Quad Status Status Register + // Note: on the MPIPL path, this also clears any trapped "in-progress" bits + // *INDENT-OFF* l_data64.flush<0>() - .setBit<0, 12>() // L2 Stopped - .setBit<14, 6>(); // Quad Stopped - FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QSSR_SCOM2, l_data64)); + .setBit<0, 12>() // L2 Stopped + .setBit<14, 6>(); // Quad Stopped + // *INDENT-ON* + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QSSR_SCOM, l_data64)); fapi_try_exit: FAPI_INF("< p9_sbe_select_ex"); diff --git a/src/import/chips/p9/sw_simulation/powermgmt.act b/src/import/chips/p9/sw_simulation/powermgmt.act index 3531ac3d..69633abd 100644 --- a/src/import/chips/p9/sw_simulation/powermgmt.act +++ b/src/import/chips/p9/sw_simulation/powermgmt.act @@ -11,6 +11,15 @@ CAUSE_EFFECT { EFFECT: TARGET=[REG(0x100F0163)] OP=[BIT,ON] BIT=[62] EFFECT: TARGET=[REG(0x100F0163)] OP=[BIT,ON] BIT=[63] } +CAUSE_EFFECT CHIPLETS cache { + LABEL=[EX-L2 clock sync done] + WATCH=[REG((MYCHIPLET,0x30001))] + CAUSE: TARGET=[REG((MYCHIPLET,0x30001))] OP=[BIT,ON] BIT=[1] + CAUSE: TARGET=[REG((MYCHIPLET,0x30001))] OP=[BIT,ON] BIT=[3] + EFFECT: TARGET=[REG((MYCHIPLET,0xF0163))] OP=[BIT,ON] BIT=[36] + EFFECT: TARGET=[REG(MYCHIPLET,0xF0163)] OP=[BIT,ON] BIT=[37] +} + CAUSE_EFFECT { LABEL=[Start clock(sl+refresh clock region) via CLK_REGION] |