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-rw-r--r--src/import/chips/p9/sw_simulation/powermgmt.act9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/import/chips/p9/sw_simulation/powermgmt.act b/src/import/chips/p9/sw_simulation/powermgmt.act
index 3531ac3d..69633abd 100644
--- a/src/import/chips/p9/sw_simulation/powermgmt.act
+++ b/src/import/chips/p9/sw_simulation/powermgmt.act
@@ -11,6 +11,15 @@ CAUSE_EFFECT {
EFFECT: TARGET=[REG(0x100F0163)] OP=[BIT,ON] BIT=[62]
EFFECT: TARGET=[REG(0x100F0163)] OP=[BIT,ON] BIT=[63]
}
+CAUSE_EFFECT CHIPLETS cache {
+ LABEL=[EX-L2 clock sync done]
+ WATCH=[REG((MYCHIPLET,0x30001))]
+ CAUSE: TARGET=[REG((MYCHIPLET,0x30001))] OP=[BIT,ON] BIT=[1]
+ CAUSE: TARGET=[REG((MYCHIPLET,0x30001))] OP=[BIT,ON] BIT=[3]
+ EFFECT: TARGET=[REG((MYCHIPLET,0xF0163))] OP=[BIT,ON] BIT=[36]
+ EFFECT: TARGET=[REG(MYCHIPLET,0xF0163)] OP=[BIT,ON] BIT=[37]
+}
+
CAUSE_EFFECT {
LABEL=[Start clock(sl+refresh clock region) via CLK_REGION]
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