diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
208 files changed, 28711 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/Makefile b/src/import/chips/p9/procedures/hwp/cache/Makefile new file mode 100644 index 00000000..a95923ab --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/Makefile @@ -0,0 +1,55 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/cache/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the cache hardware procedure code. See the +# "cachehcdfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/cache +export SUB_OBJDIR = /cache + +include img_defs.mk +include cachehcdfiles.mk + +GCC-CFLAGS += -mlongcall + +OBJS := $(addprefix $(OBJDIR)/, $(CACHE_OBJECTS)) + +libcache.a: cache + $(AR) crs $(OBJDIR)/libcache.a $(OBJDIR)/*.o + +.PHONY: clean cache +cache: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk b/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk new file mode 100644 index 00000000..f8ae915e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk @@ -0,0 +1,56 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file cachehcdfiles.mk +# +# @brief mk for including cache hcode object files +# +########################################################################## +# Object Files +########################################################################## + +CACHE-CPP-SOURCES += p9_hcd_cache_arrayinit.C +CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_init.C +CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_reset.C +CACHE-CPP-SOURCES += p9_hcd_cache_dpll_setup.C +CACHE-CPP-SOURCES += p9_hcd_cache_gptr_time_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_occ_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_cache_poweron.C +CACHE-CPP-SOURCES += p9_hcd_cache_ras_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_cache_repair_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_runinit.C +CACHE-CPP-SOURCES += p9_hcd_cache_scomcust.C +CACHE-CPP-SOURCES += p9_hcd_cache_scominit.C +CACHE-CPP-SOURCES += p9_hcd_cache_startclocks.C +CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_l3_dcc_setup.C +CACHE-CPP-SOURCES += p9_hcd_cache_dpll_initf.C + +CACHE-C-SOURCES += +CACHE-S-SOURCES += + +CACHE_OBJECTS += $(CACHE-CPP-SOURCES:.C=.o) +CACHE_OBJECTS += $(CACHE-C-SOURCES:.c=.o) +CACHE_OBJECTS += $(CACHE-S-SOURCES:.S=.o) + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H new file mode 100644 index 00000000..d73007e7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache.H +/// @brief Cache Chiplet Procedure Includes +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 2 +/// + +#ifndef __P9_HCD_CACHE_H__ +#define __P9_HCD_CACHE_H__ + +#include <p9_hcd_cache_arrayinit.H> +#include <p9_hcd_cache_chiplet_init.H> +#include <p9_hcd_cache_chiplet_reset.H> +#include <p9_hcd_cache_dpll_setup.H> +#include <p9_hcd_cache_gptr_time_initf.H> +#include <p9_hcd_cache_initf.H> +#include <p9_hcd_cache_occ_runtime_scom.H> +#include <p9_hcd_cache_poweron.H> +#include <p9_hcd_cache_ras_runtime_scom.H> +#include <p9_hcd_cache_repair_initf.H> +#include <p9_hcd_cache_scomcust.H> +#include <p9_hcd_cache_scominit.H> +#include <p9_hcd_cache_startclocks.H> + +#endif // __P9_HCD_CACHE_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C new file mode 100644 index 00000000..3b2887c4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C @@ -0,0 +1,147 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.C +/// @brief EX Initialize arrays +/// +/// Procedure Summary: +/// Use ABIST engine to zero out all arrays +/// Upon completion, scan0 flush all rings +/// except Vital, Repair, GPTR, TIME and DPLL + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include <p9_quad_scom_addresses.H> +#include <p9_misc_scom_addresses.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_hcd_common.H> +#include "p9_hcd_cache_arrayinit.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +enum P9_HCD_CACHE_ARRAYINIT_Private_Constants +{ + LOOP_COUNTER = 0x0000000000042FFF, + SELECT_SRAM = 0x1, + SELECT_EDRAM = 0x0, + START_ABIST_MATCH_VALUE = 0x0000000F00000000 +}; + +//----------------------------------------------------------------------------- +// Procedure: Initialize Cache Arrays +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_hcd_cache_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_arrayinit"); + fapi2::buffer<uint64_t> l_data64; + uint16_t l_region_array; + uint16_t l_region_scan0; + uint8_t l_attr_chip_unit_pos = 0; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = + i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + l_attr_chip_unit_pos)); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET; + + FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_data64)); + FAPI_DBG("Working on cache[%d] good EXs in QCSR[%016llX]", + l_attr_chip_unit_pos, l_data64); + + l_region_array = p9hcd::SCAN0_REGION_ALL_BUT_EX_DPLL; + l_region_scan0 = p9hcd::SCAN0_REGION_ALL_BUT_EX_ANEP_DPLL; + + if (l_data64 & BIT64(l_attr_chip_unit_pos << 1)) + { + l_region_array |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR; + l_region_scan0 |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR; + } + + if (l_data64 & BIT64((l_attr_chip_unit_pos << 1) + 1)) + { + l_region_array |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR; + l_region_scan0 |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR; + } + + /// @todo add DD1 attribute control + FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0_OR, MASK_SET(34))); + +#ifndef P9_HCD_STOP_SKIP_ARRAYINIT + + FAPI_DBG("Arrayinit all regions except vital/DPLL"); + FAPI_TRY(p9_perv_sbe_cmn_array_init_module(l_perv, + l_region_array, + LOOP_COUNTER, + SELECT_SRAM, + SELECT_EDRAM, + START_ABIST_MATCH_VALUE)); + +#endif + +#ifndef P9_HCD_STOP_SKIP_FLUSH + + //-------------------------------------------- + // perform scan0 module for pervasive chiplet + //-------------------------------------------- + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest + // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has + // all stumps less than 8191, the loop can be removed. + + FAPI_DBG("Scan0 region:all_but_anep_dpll type:all_but_gptr_repr_time rings"); + + for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + l_region_scan0, + p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); + +#endif + + /// @todo add DD1 attribute control + FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0_CLEAR, MASK_SET(34))); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_arrayinit"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H new file mode 100644 index 00000000..16b97e5b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.H +/// @brief EX Initialize arrays +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_ARRAYINIT_H__ +#define __P9_HCD_CACHE_ARRAYINIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_arrayinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_arrayinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief EX Initialize arrays +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_ARRAYINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C new file mode 100644 index 00000000..2978337b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C @@ -0,0 +1,88 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.C +/// @brief Cache Flush/Initialize +/// +/// Procedure Summary: +/// Scan0 flush all configured chiplet rings except Vital, GPTR, TIME and DPLL + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include <p9_quad_scom_addresses.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_hcd_common.H> +#include "p9_hcd_cache_chiplet_init.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Cache Flush/Initialize +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_hcd_cache_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_chiplet_init"); + /* + #ifndef P9_HCD_STOP_SKIP_FLUSH + + //-------------------------------------------- + // perform scan0 module for pervasive chiplet + //-------------------------------------------- + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest + // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has + // all stumps less than 8191, the loop can be removed. + + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + + FAPI_DBG("Scan0 region:all_but_anep_dpll type:all_but_gptr_repr_time rings"); + + for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + p9hcd::SCAN0_REGION_ALL_BUT_ANEP_DPLL, + p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); + + fapi_try_exit: + + #endif + */ + FAPI_INF("<<p9_hcd_cache_chiplet_init"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H new file mode 100644 index 00000000..7b55f9ee --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.H +/// @brief Cache Flush/Initialize +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_CHIPLET_INIT_H__ +#define __P9_HCD_CACHE_CHIPLET_INIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_chiplet_init_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_init_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Cache Flush/Initialize +/// @param [in] i_target TARGET_TYPE_EQ target +/// @return FAPI2_RC_SUCCESS if success, else error code + fapi2::ReturnCode + p9_hcd_cache_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_CHIPLET_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C new file mode 100644 index 00000000..0cf09244 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C @@ -0,0 +1,83 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_chiplet_l3_dcc_setup.C +/// +/// @brief Setup L3 DCC, Drop L3 DCC bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_hcd_cache_chiplet_l3_dcc_setup.H" + +#include <p9_quad_scom_addresses.H> +#include <p9_quad_scom_addresses_fld.H> + + +fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet) +{ + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::buffer<uint64_t> l_data64; + uint8_t l_read_attr = 0; + FAPI_DBG("Entering ..."); + + FAPI_DBG("Scan eq_ana_bndy_l3dcc_bucket_26 ring"); + FAPI_TRY(fapi2::putRing(i_target_chiplet, eq_ana_bndy_l3dcc_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_l3dcc_bucket_26)"); + + FAPI_DBG("Drop L3 DCC bypass"); + //Setting NET_CTRL1 register value + l_data64.flush<1>(); + //NET_CTRL1.CLK_DCC_BYPASS_EN = 0 + l_data64.clearBit<C_NET_CTRL1_CLK_DCC_BYPASS_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, EQ_NET_CTRL1_WAND, l_data64)); + + FAPI_DBG("Check if VDMs are to be enabled. If so, power them on"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE, FAPI_SYSTEM, + l_read_attr)); + + if( l_read_attr ) + { + + l_data64.flush<0>(); + l_data64.setBit<0>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, EQ_PPM_VDMCR_OR, l_data64)); + + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H new file mode 100644 index 00000000..2033f38f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_chiplet_l3_dcc_setup.H +/// +/// @brief Setup L3 DCC, Drop L3 DCC bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_HCD_CACHE_CHIPLET_L3_DCC_SETUP_H_ +#define _P9_HCD_CACHE_CHIPLET_L3_DCC_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_l3_dcc_setup_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief * Setup L3 DCC (scan with setpulse, scan region = ANEP), attribute dependency Nimbus/Cumulus +/// * Drop L3 DCC bypass +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_EQ target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C new file mode 100644 index 00000000..8f35b4ed --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -0,0 +1,237 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_reset.C +/// @brief Cache Chiplet Reset +/// +/// Procedure Summary: +/// Reset quad chiplet logic +/// Clocking: +/// - setup cache sector buffer strength, +/// pulse mode and pulsed mode enable values +/// (attribute dependency Nimbus/Cumulus) +/// - Drop glsmux async reset +/// Scan0 flush entire cache chiplet + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_misc_scom_addresses.H> +#include <p9_quad_scom_addresses.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_hcd_common.H> +#include "p9_hcd_cache_chiplet_reset.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +enum P9_HCD_CACHE_CHIPLET_RESET_CONSTANTS +{ + // (1)PCB_EP_RESET + // (2)CLK_ASYNC_RESET + // (3)PLL_TEST_EN + // (4)PLLRST + // (5)PLLBYP + // (11)EDIS + // (12)VITL_MPW1 + // (13)VITL_MPW2 + // (14)VITL_MPW3 + // (16)VITL_THOLD + // (18)FENCE_EN + // (22)FUNC_CLKSEL + // (25)PCB_FENCE + // (26)LVLTRANS_FENCE + Q_NET_CTRL0_INIT_VECTOR = (BITS64(1, 5) | BITS64(11, 4) | BIT64(16) | + BIT64(18) | BIT64(22) | BITS64(25, 2)), + CACHE_GLSMUX_RESET_DELAY_REF_CYCLES = 40 +}; + +//------------------------------------------------------------------------------ +// Procedure: Cache Chiplet Reset +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_chiplet_reset"); + fapi2::buffer<uint64_t> l_data64; + uint16_t l_region_scan0; + uint64_t l_l2gmux_input = 0; + uint64_t l_l2gmux_reset = 0; + uint8_t l_attr_chip_unit_pos = 0; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = + i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + auto l_core_functional_vector = + i_target.getChildren<fapi2::TARGET_TYPE_CORE> + (fapi2::TARGET_STATE_FUNCTIONAL); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + l_attr_chip_unit_pos)); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET; + + FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_data64)); + FAPI_DBG("Working on cache[%d], good EXs in QCSR[%016llX]", + l_attr_chip_unit_pos, l_data64); + + l_region_scan0 = p9hcd::SCAN0_REGION_ALL_BUT_EX; + + if (l_data64 & BIT64(l_attr_chip_unit_pos << 1)) + { + l_region_scan0 |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR; + l_l2gmux_reset |= BIT64(32); + l_l2gmux_input |= BIT64(34); + } + + if (l_data64 & BIT64((l_attr_chip_unit_pos << 1) + 1)) + { + l_region_scan0 |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR; + l_l2gmux_reset |= BIT64(33); + l_l2gmux_input |= BIT64(35); + } + + //-------------------------- + // Reset cache chiplet logic + //-------------------------- + // If there is an unused, powered-off cache chiplet which needs to be + // configured in the following steps to setup the PCB endpoint. + + for(auto it : l_core_functional_vector) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + it.getParent<fapi2::TARGET_TYPE_PERV>(), + l_attr_chip_unit_pos)); + FAPI_DBG("Assert core[%d] DCC reset via NET_CTRL0[2]", + (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET)); + FAPI_TRY(putScom(l_chip, (C_NET_CTRL0_WOR + (0x1000000 * + (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET))), + MASK_SET(2))); + } + + /// @todo needs to revisit this sim workaround + FAPI_DBG("Init heartbeat hang counter via HANG_PULSE_6[2]"); + FAPI_TRY(putScom(i_target, EQ_HANG_PULSE_6_REG, MASK_SET(2))); + + FAPI_DBG("Init NET_CTRL0[1-5,11-14,16,18,22,25,26],step needed for hotplug"); + l_data64 = Q_NET_CTRL0_INIT_VECTOR; + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0, l_data64)); + + FAPI_DBG("Assert progdly/DCC bypass,L2 DCC reset via NET_CTRL1[1,2,23,24]"); + l_data64.flush<0>().insertFromRight<1, 2>(0x3).insertFromRight<23, 2>(0x3); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WOR, l_data64)); + + FAPI_DBG("Flip cache glsmux to DPLL input via PPM_CGCR[3]"); + FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_OR(0, 4, 0x9))); + + FAPI_DBG("Flip L2 glsmux to DPLL input via QPPM_EXCGCR[34:35]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, l_l2gmux_input)); + + FAPI_DBG("Assert DPLL ff_bypass via QPPM_DPLL_CTRL[2]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, MASK_SET(2))); + + FAPI_DBG("Drop vital thold via NET_CTRL0[16]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(16))); + + /// @todo optional setup sector buffer strength, pulse mode and pulsed mode enable + + FAPI_DBG("Drop cache glsmux reset via PPM_CGCR[0]"); + FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(3))); + + FAPI_DBG("Drop L2 glsmux reset via QPPM_EXCGCR[32:33]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_CLEAR, l_l2gmux_reset)); + + FAPI_TRY(fapi2::delay( + CACHE_GLSMUX_RESET_DELAY_REF_CYCLES * p9hcd::CLK_PERIOD_10NS, + CACHE_GLSMUX_RESET_DELAY_REF_CYCLES * p9hcd::SIM_CYCLE_200UD)); + + FAPI_DBG("Assert chiplet enable via NET_CTRL0[0]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(0))); + + FAPI_DBG("Drop PCB endpoint reset via NET_CTRL0[1]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(1))); + + FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(26))); + + FAPI_DBG("Drop PCB fence via NET_CTRL0[25]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25))); + + FAPI_DBG("Set scan ratio to 1:1 in bypass mode via OPCG_ALIGN[47-51]"); + FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<47, 5>(0x0); + FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64)); + +#ifndef P9_HCD_STOP_SKIP_FLUSH + //-------------------------------------------- + // perform scan0 module for pervasive chiplet + //-------------------------------------------- + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest + // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has + // all stumps less than 8191, the loop can be removed. + + // Putting in block to avoid c++ crosses initialization compile error + { + uint32_t l_loop; + + FAPI_DBG("Scan0 region:all_but_vital type:gptr_repr_time rings"); + + for(l_loop = 0; l_loop < P9_HCD_SCAN_GPTR_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + l_region_scan0, + p9hcd::SCAN0_TYPE_GPTR_REPR_TIME)); + + FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings"); + + for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + l_region_scan0, + p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); + } +#endif + + /// @todo scan_with_setpulse_module(L3 DCC) + //FAPI_DBG("Drop L3 DCC bypass via NET_CTRL1[1]"); + //FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WAND, MASK_UNSET(1))); + /// @todo add VDM_ENABLE attribute control + //FAPI_DBG("Assert vdm enable via CPPM_VDMCR[0]"); + //FAPI_TRY(putScom(i_target, EQ_PPM_VDMCR_OR, MASK_SET(0))); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_chiplet_reset"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H new file mode 100644 index 00000000..1582c76d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_reset.H +/// @brief Cache Chiplet Reset +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_CHIPLET_RESET_H__ +#define __P9_HCD_CACHE_CHIPLET_RESET_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_chiplet_reset_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_reset_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Cache Chiplet Reset +/// @param [in] i_target TARGET_TYPE_EQ target +/// @return FAPI2_RC_SUCCESS if success, else error code + fapi2::ReturnCode + p9_hcd_cache_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_CHIPLET_RESET_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C new file mode 100644 index 00000000..64b30d93 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C @@ -0,0 +1,71 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_initf.C +/// @brief Load DPLL ring for EX non-core +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: DPLL Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in +/// MVPD, but SBE image is customized with rings for booting cores + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_ring_id.h> +#include "p9_hcd_cache_dpll_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load DPLL ring for cache +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_dpll_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_dpll_initf"); + + FAPI_DBG("Scan eq_dpll_func ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_dpll_func), + "Error from putRing (eq_dpll_func)"); + +fapi_try_exit: + FAPI_INF("<<p9_hcd_cache_dpll_initf"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H new file mode 100644 index 00000000..3c48f52a --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_initf.H +/// @brief Load DPLL ring for EX non-core +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_DPLL_INITF_H__ +#define __P9_HCD_CACHE_DPLL_INITF_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_dpll_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_dpll_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Load DPLL ring for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_DPLL_RING - EX target, uint32 +/// pointer to RS4 content, VPD #R Keyword content(RS4)<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_dpll_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_DPLL_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C new file mode 100644 index 00000000..744f0ae9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -0,0 +1,206 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_setup.C +/// @brief Quad DPLL Setup +/// +/// Procedure Summary: +/// Note: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// DPLL tune bits are not dependent on frequency +/// Frequency is controlled by the Quad PPM +/// Actual frequency value for boot is stored into the Quad PPM by +/// p9_hcd_setup_evid.C in istep 2 +/// In real cache STOP exit, the frequency value is persistent +/// +/// Pre-Scan: +/// +/// Scan: +/// (TODO) Set clock controller scan ratio to 1:1 as this is done at refclk +/// (TODO) scan0 (region = DPLL and ANEP, scan_type = GPTR) +/// (TODO) scan0 (region = DPLL and ANEP, scan_type = FUNC) +/// (TODO) Set clock controller scan ratio to 8:1 for future scans +/// +/// Setup: +/// (TODO) set DPLL FREQ CTRL regitster +/// (TODO) set DPLL CTRL register +/// (Done) Drop DPLL test mode; +/// (Done) Drop DPLL into Reset; +/// (Done) Start DPLL clock via quad clock controller +/// (Done) Check for DPLL lock, Timeout: 200us +/// (Done) Remove DPLL bypass +/// (Done) Switch cache glitchless mux to use the DPLL +/// (Done) Drop ff_bypass to enable slewing +/// +/// 1) reset, dpll_func_clksel, and all SL_HLD inputs are asserted +/// 2) If grid clock connected to dpll clkout, +/// bypass also has to be asserted to allow refclk on grid + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include <p9_quad_scom_addresses.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_hcd_common.H> +#include "p9_hcd_cache_dpll_setup.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +enum P9_HCD_CACHE_DPLL_SETUP_CONSTANTS +{ + CACHE_DPLL_LOCK_TIMEOUT_IN_MS = 1, + CACHE_DPLL_CLK_START_TIMEOUT_IN_MS = 1, + CACHE_ANEP_CLK_START_TIMEOUT_IN_MS = 1 +}; + +//----------------------------------------------------------------------------- +// Procedure: Quad DPLL Setup +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_hcd_cache_dpll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_dpll_setup"); + fapi2::buffer<uint64_t> l_data64; + uint32_t l_timeout; + + //---------------------------- + // Prepare to start DPLL clock + //---------------------------- + + FAPI_DBG("Assert DPLL in mode 1,set slew rate via QPPM_DPLL_CTRL[2,6-15]"); + l_data64.flush<0>().setBit<2>().insertFromRight<6, 10>(0x40); + FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, l_data64)); + + FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2))); + + FAPI_DBG("Drop DPLL test mode and reset via NET_CTRL0[3,4]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_AND(3, 2, 0))); + + FAPI_DBG("Drop DPLL clock region fence via NET_CTRL1[14]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(14))); + + // ---------------- + // Start DPLL clock + // ---------------- + + FAPI_DBG("Clear all bits prior start DPLL clock via SCAN_REGION_TYPE"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); + + FAPI_DBG("Start DPLL clock via CLK_REGION"); + l_data64 = (p9hcd::CLK_START_CMD | + p9hcd::CLK_REGION_DPLL | + p9hcd::CLK_THOLD_ALL); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); + + FAPI_DBG("Poll for DPLL clock running via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CACHE_DPLL_CLK_START_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_DPLLCLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), + "DPLL Clock Start Timeout"); + + FAPI_DBG("Check DPLL clock running via CLOCK_STAT_SL[14]"); + FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64)); + + FAPI_ASSERT((l_data64.getBit<14>() == 0), + fapi2::PMPROC_DPLLCLKSTART_FAILED().set_EQCLKSTAT(l_data64), + "DPLL Clock Start Failed"); + FAPI_DBG("DPLL clock running now"); + + // This is necessary to ensure that the DPLL is in Mode 1(ff_bypass = 1) + // If not, the lock times will go from ~30us to 3-5ms + FAPI_DBG("Poll for DPLL to lock via QPPM_DPLL_STAT"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CACHE_DPLL_LOCK_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, EQ_QPPM_DPLL_STAT, l_data64)); + ///@todo disable poll for DPLL lock until model setting in place + break; + } + while ((l_data64.getBit<63>() != 1 ) && (--l_timeout != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_DPLL_LOCK_TIMEOUT() + .set_EQQPPMDPLLSTAT(l_data64), + "DPLL Lock Timeout"); + FAPI_DBG("DPLL is locked now"); + + //-------------------------- + // Cleaning up + //-------------------------- + + FAPI_DBG("Drop DPLL bypass via NET_CTRL0[5]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(5))); + + FAPI_DBG("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2))); + + FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2))); + + FAPI_DBG("Set scan ratio to 4:1 in non-bypass mode via OPCG_ALIGN[47-51]"); + FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<47, 5>(0x3); + FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64)); + + FAPI_DBG("Drop ANEP clock region fence via CPLT_CTRL1[10]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(10))); + + FAPI_DBG("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(22))); + + FAPI_DBG("Drop skew adjust reset via NET_CTRL0[2]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(2))); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_dpll_setup"); + return fapi2::current_err; +} + + + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H new file mode 100644 index 00000000..0da2ea3b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_setup.H +/// @brief Quad DPLL Setup +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_DPLL_SETUP_H__ +#define __P9_HCD_CACHE_DPLL_SETUP_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_dpll_setup_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_dpll_setup_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ +/// @brief Quad DPLL Setup +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_DPLL_REPAIR_RING - EQ target, uint32 +/// repair dpll ring content<br> +/// +/// @retval FAPI2_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_dpll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_DPLL_SETUP_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C new file mode 100644 index 00000000..4a2e620f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C @@ -0,0 +1,126 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.C +/// @brief Load GPTR and Time for EX non-core +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// to produce #G VPD contents +/// Check for the presence of core override GPTR ring from image +/// (this is new fvor P9) +/// if found, apply; if not, apply core GPTR from image +/// Check for the presence of core override TIME ring from image; +/// if found, apply; if not, apply core base TIME from image + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_ring_id.h> +#include "p9_hcd_cache_gptr_time_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load GPTR and Time for EX non-core +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_gptr_time_initf"); + + auto l_ex_targets = i_target.getChildren<fapi2::TARGET_TYPE_EX>(); + + FAPI_DBG("Scan eq_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_gptr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (eq_gptr)"); + + FAPI_DBG("Scan eq_time ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_time, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (eq_time)"); + + for (auto l_ex : l_ex_targets) + { + FAPI_DBG("Scan ex_l3_gptr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_gptr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l3_gptr)"); + + FAPI_DBG("Scan ex_l2_gptr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l2_gptr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l2_gptr)"); + + FAPI_DBG("Scan ex_l3_refr_gptr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_gptr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l3_refr_gptr)"); + + FAPI_DBG("Scan ex_l3_time ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_time, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l3_time)"); + + FAPI_DBG("Scan ex_l2_time ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l2_time, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l2_time)"); + + FAPI_DBG("Scan ex_l3_refr_time ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_time, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l3_refr_time)"); + } + + FAPI_DBG("Scan eq_dpll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_dpll_gptr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (eq_dpll_gptr)"); + + FAPI_DBG("Scan eq_ana_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_ana_gptr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (eq_ana_gptr)"); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_gptr_time_initf"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H new file mode 100644 index 00000000..714395cf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.H +/// @brief Load GPTR and Time for EX non-core +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_GPTR_TIME_INIT_H__ +#define __P9_HCD_CACHE_GPTR_TIME_INIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_gptr_time_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_gptr_time_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Load GPTR and Time for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_GPTR_TIME_RING - EX target, uint32 +/// pointer to RS4 content.<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_GPTR_TIME_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C new file mode 100644 index 00000000..3eb56747 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C @@ -0,0 +1,88 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.C +/// @brief EX (non-core) scan init +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// Check for the presence of cache FUNC override rings from image; +/// if found, apply; if not, apply cache base FUNC rings from image +/// Note: FASTINIT ring (eg CMSK ring) is setup at this point to limit the +/// stumps that participate in FUNC ring scanning (this is new for P9). +/// (TODO to make sure the image build support is in place) +/// Note: all caches that are in the Cache Multicast group will be +/// initialized to the same values via multicast scans + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include "p9_hcd_cache_initf.H" + +//------------------------------------------------------------------------------ +// Procedure: EX (non-core) scan init +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_initf"); + + FAPI_DBG("Scan eq_fure ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_fure), + "Error from putRing (eq_fure)"); + FAPI_DBG("Scan eq_ana_func ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_ana_func), + "Error from putRing (eq_ana_func)"); + + for (auto l_ex_target : i_target.getChildren<fapi2::TARGET_TYPE_EX>()) + { + FAPI_DBG("Scan ex_l2_fure ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_fure), + "Error from putRing (ex_l2_fure)"); + FAPI_DBG("Scan ex_l2_mode ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_mode), + "Error from putRing (ex_l2_mode)"); + FAPI_DBG("Scan ex_l3_fure ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_fure), + "Error from putRing (ex_l3_fure)"); + FAPI_DBG("Scan ex_l3_refr_fure ring"); + FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_refr_fure), + "Error from putRing (ex_l3_refr_fure)"); + } + +fapi_try_exit: + FAPI_INF("<<p9_hcd_cache_initf"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H new file mode 100644 index 00000000..1754c690 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.H +/// @brief EX (non-core) scan init +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_INITF_H__ +#define __P9_HCD_CACHE_INITF_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief EX (non-core) scan init +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_L2_FUNC_RING - EX target, uint32 +/// @attritem ATTR_CACHE_L3_FUNC_RING - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C new file mode 100644 index 00000000..d0e592a4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.C +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from OCC code that are put somewhere TBD +/// (TODO . revisit with OCC FW team) +/// OCC FW sets up value in the TBD SCOM section +/// This was not leverage in P8 with the demise of CPMs +/// Placeholder at this point +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_occ_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX OCC runtime SCOMS +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, occ_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + FAPI_INF("Launching OCC Runtime SCOM routine") + // - bsrd D0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H new file mode 100644 index 00000000..24c329f8 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.H +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_occ_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_occ_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + + +/// @brief EX OCC runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_OCC_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C new file mode 100644 index 00000000..c5193803 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C @@ -0,0 +1,92 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_poweron.C +/// @brief Cache Chiplet Power-on +/// +/// Procedure Summary: +/// Set glsmux async reset +/// Set DPLL ff_bypass +/// Command the cache PFET controller to power-on +/// Check for valid power on completion +/// Polled Timeout: 100us + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_quad_scom_addresses.H> +#include <p9_hcd_common.H> +#include <p9_common_poweronoff.H> +#include <p9_common_poweronoff.C> +#include "p9_hcd_cache_poweron.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Cache Chiplet Power-on +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_poweron"); + fapi2::buffer<uint64_t> l_data64; + + //-------------------------- + // Prepare to power on cache + //-------------------------- + + FAPI_DBG("Drop chiplet enable via NET_CTRL0[0]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(0))); + + FAPI_DBG("Assert L2 glsmux reset via EXCLK_GRID_CTRL[32:33]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, MASK_OR(32, 2, 0x3))); + + FAPI_DBG("Assert cache glsmux reset via CLOCK_GRID_CTRL[0]"); + FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(0))); + + //----------------------- + // Power on cache chiplet + //----------------------- + + FAPI_DBG("Power on cache chiplet"); + FAPI_TRY(p9_common_poweronoff<fapi2::TARGET_TYPE_EQ>(i_target, p9power::POWER_ON)); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_poweron"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H new file mode 100644 index 00000000..656616f4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_poweron.H +/// @brief Cache Chiplet Power-on +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : SBE:SGPE + +#ifndef __P9_HCD_CACHE_POWERON_H__ +#define __P9_HCD_CACHE_POWERON_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_poweron_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_poweron_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ +/// @brief Cache Chiplet Power-on +/// @param [in] i_target TARGET_TYPE_EQ target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_* +/// +/// @retval FAPI2_RC_SUCCESS if success, else error code + + fapi2::ReturnCode + p9_hcd_cache_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); +} + +#endif // __P9_HCD_CACHE_POWERON_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C new file mode 100644 index 00000000..5398597e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C @@ -0,0 +1,171 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.C +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates by FSP/Host(including HostServices and Hypervisors) +/// that are put on the cache image by STOP API calls +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (the SBE case), return +/// Else call the function at the pointer; pointer is filled in by +/// STOP image build +/// Powerbus (MCD) and L3 BAR settings +/// Runtime FIR mask updates from PRD +/// L2/L3 Repairs +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_ras_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX FSP/HOST runtime scoms +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, sp_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching SP Runtime SCOM routine") + // - bsrd D0 + // - 1: + // + + // Run the SCOM sequence if the SCOM procedure is defined. + // - la A0, host_runtime_scom + // - ld D1, 0, A0 + // - braz D1, 1f + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Disable the AISS to allow the override + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~(BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = ori D0, D0, (BIT(15)) + // = andi D0, D0, ~(BIT(21)) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + + // Branch to sub_slw_runtime_scom() + FAPI_INF("Launching Host Runtime SCOM routine") + // - bsrd D1 + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + + // - bra 2f + // - 1: + + // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - 2: + + // If using cv_multicast, we need to set the magic istep number here + // - la A0, p9_sbe_select_ex_control + // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX + // - braz D0, 3f + FAPI_DBG("Setting istep num to magic number because cv_multicast is set") + // - lpcs P1, MBOX_SBEVITAL_0x0005001C + // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) + // - 3: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H new file mode 100644 index 00000000..394fb6f6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.H +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_ras_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_ras_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief EX FSP/Host runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_RAS_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C new file mode 100644 index 00000000..b34ae956 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C @@ -0,0 +1,96 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.C +/// @brief Load Repair ring for EX non-core +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: Repair Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in +/// MVPD, but SBE image is customized with rings for booting cores + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_ring_id.h> +#include "p9_hcd_cache_repair_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load Repair ring for cache +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_repair_initf"); + + auto l_ex_targets = i_target.getChildren<fapi2::TARGET_TYPE_EX>(); + + FAPI_DBG("Scan eq_repr ring"); + FAPI_TRY(fapi2::putRing(i_target, eq_repr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (eq_repr)"); + + for (auto l_ex : l_ex_targets) + { + FAPI_DBG("Scan ex_l3_repr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_repr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l3_repr)"); + + FAPI_DBG("Scan ex_l2_repr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l2_repr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l2_repr)"); + + FAPI_DBG("Scan ex_l3_refr_repr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_repr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ex_l3_refr_repr)"); + } + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_repair_initf"); + return fapi2::current_err; +} + + + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H new file mode 100644 index 00000000..3712cafb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.H +/// @brief Load Repair ring for EX non-core +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_REPAIR_INITF_H__ +#define __P9_HCD_CACHE_REPAIR_INITF_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_repair_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_repair_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Load Repair ring for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_REPAIR_RING - EX target, uint32 +/// pointer to RS4 content, VPD #R Keyword content(RS4)<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_REPAIR_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C new file mode 100644 index 00000000..96ce825d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.C +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// If CME, request PCB Mux. +/// Poll for PCB Mux grant +/// Else (SBE) +/// Nop (as the CME is not running in bringing up the first Core) +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_scomcust.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: Core Chiplet PCB Arbitration +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_cache_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) + { + +#if 0 + + fapi2::buffer<uint64_t> data; + + //Dynamically built (and installed) routine that is inserted by the .XIP + //Customization. process. (New for P9) + //(TODO: this part of the process is a placeholder at this point) + //Dynamically built pointer where a NULL is checked before execution + //If NULL (a potential early value); return + //Else call the function at the pointer; + //pointer is filled in by XIP Customization + //Customization items: + //Epsilon settings scan flush to super safe + //Customize Epsilon settings for system config + //LCO setup (chiplet specific) + //FW setups up based victim caches + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H new file mode 100644 index 00000000..cc3e8884 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.H +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_SCOMCUST_H__ +#define __P9_HCD_CACHE_SCOMCUST_H__ +extern "C" +{ + +/// @typedef p9_hcd_cache_scomcust_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_cache_scomcust_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + + +/// @brief Core Chiplet PCB Arbitration +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_SCOMCUST_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C new file mode 100644 index 00000000..38ee4977 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C @@ -0,0 +1,119 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.C +/// @brief Cache Customization SCOMs +/// +/// Procedure Summary: +/// Apply any SCOM initialization to the cache +/// Stop L3 configuration mode +/// Configure Trace Stop on Xstop +/// DTS Initialization sequense +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_quad_scom_addresses.H> +#include <p9_hcd_common.H> +#include <p9_l2_scom.H> +#include <p9_l3_scom.H> +#include <p9_ncu_scom.H> +#include "p9_hcd_cache_scominit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Cache Customization SCOMs +//------------------------------------------------------------------------------ + + +fapi2::ReturnCode +p9_hcd_cache_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_scominit"); + fapi2::buffer<uint64_t> l_data64; + + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + auto l_ex_targets = i_target.getChildren<fapi2::TARGET_TYPE_EX>(); + fapi2::ReturnCode l_rc; + + for (auto l_iter = l_ex_targets.begin(); l_iter != l_ex_targets.end(); l_iter++) + { + FAPI_EXEC_HWP(l_rc, p9_l2_scom, *l_iter, FAPI_SYSTEM); + + if (l_rc) + { + FAPI_ERR("Error from p9_l2_scom (p9.l2.scom.initfile)"); + fapi2::current_err = l_rc; + goto fapi_try_exit; + } + + FAPI_EXEC_HWP(l_rc, p9_l3_scom, *l_iter, FAPI_SYSTEM); + + if (l_rc) + { + FAPI_ERR("Error from p9_l3_scom (p9.l3.scom.initfile)"); + fapi2::current_err = l_rc; + goto fapi_try_exit; + } + + FAPI_EXEC_HWP(l_rc, p9_ncu_scom, *l_iter, FAPI_SYSTEM); + + if (l_rc) + { + FAPI_ERR("Error from p9_ncu_scom (p9.ncu.scom.initfile)"); + fapi2::current_err = l_rc; + goto fapi_try_exit; + } + } + + /// @todo set the sample pulse count (bit 6:9) + /// enable the appropriate loops + /// (needs investigation with the Perv team on the EC wiring). + FAPI_DBG("Enable DTS sampling via THERM_MODE_REG[5]"); + FAPI_TRY(getScom(i_target, EQ_THERM_MODE_REG, l_data64)); + FAPI_TRY(putScom(i_target, EQ_THERM_MODE_REG, DATA_SET(5))); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_scominit"); + return fapi2::current_err; +} + + + + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H new file mode 100644 index 00000000..ded02249 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.H +/// @brief Cache Customization SCOMs +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_SCOMINIT_H__ +#define __P9_HCD_CACHE_SCOMINIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_scominit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_scominit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Cache Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_cache_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_SCOMINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C new file mode 100644 index 00000000..a7bc1510 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -0,0 +1,334 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.C +/// @brief Quad Clock Start +/// +/// Procedure Summary: +/// (Done) Setup L3 EDRAM/LCO +/// (Done) Setup OPCG_ALIGN +/// (Done) Drop partial good regional fences(always drop vital and pervasive) +/// (Done) Drop Vital fence +/// (Done) Reset abst clock muxsel, sync muxsel +/// (TODO) Set fabric node/chip ID from the nest version +/// (Done) module align_chiplets +/// (Done) - set flushmode_inh to exit flush mode +/// (Done) - set force align +/// (Done) - set chiplet_is_aligned +/// (Done) - clear chiplet_is_aligned +/// (Done) - wait +/// (Done) - check chiplet is aligned +/// (Done) - clear force align +/// (Done) module start_clocks +/// (Done) - Clear clock controller scan register before start +/// (Done) - Start arrays + nsl regions +/// (Done) - Start sl + refresh clock regions +/// (Done) Check for clocks started. If not, error +/// (Done) Drop the cache to PowerBus logical fence +/// (Done) Check for cache xstop, If so, error +/// (Done) Clear flushmode_inh to go into flush mode + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_misc_scom_addresses.H> +#include <p9_quad_scom_addresses.H> +#include <p9_hcd_common.H> +#include "p9_hcd_cache_startclocks.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +enum P9_HCD_CACHE_STARTCLOCKS_CONSTANTS +{ + CACHE_CLK_SYNC_TIMEOUT_IN_MS = 1, + CACHE_CLK_START_TIMEOUT_IN_MS = 1, + CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES = 255 +}; + +//------------------------------------------------------------------------------ +// Procedure: Quad Clock Start +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_cache_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + FAPI_INF(">>p9_hcd_cache_startclocks"); + fapi2::buffer<uint64_t> l_qcsr; + fapi2::buffer<uint64_t> l_data64; + uint64_t l_region_clock; + uint64_t l_l2sync_clock; + uint64_t l_l2pscom_mask; + uint64_t l_l3pscom_mask; + uint32_t l_timeout; + uint32_t l_attr_system_id = 0; + uint8_t l_attr_group_id = 0; + uint8_t l_attr_chip_id = 0; + uint8_t l_attr_chip_unit_pos = 0; + uint8_t l_attr_system_ipl_phase; + uint32_t l_attr_pg; + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = + i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys, + l_attr_system_ipl_phase)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, l_chip, + l_attr_group_id)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, l_chip, + l_attr_chip_id)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip, + l_attr_system_id)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, l_perv, + l_attr_pg)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + l_attr_chip_unit_pos)); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET; + + FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_qcsr)); + FAPI_DBG("Working on cache[%d], good EXs in QCSR[%016llX]", + l_attr_chip_unit_pos, l_qcsr); + + // ----------------------------- + // Prepare to start cache clocks + // ----------------------------- + // QCCR[0/4] EDRAM_ENABLE_DC + // QCCR[1/5] EDRAM_VWL_ENABLE_DC + // QCCR[2/6] L3_EX0/1_EDRAM_VROW_VBLH_ENABLE_DC + // QCCR[3/7] EDRAM_VPP_ENABLE_DC + // 0x0 -> 0x8 -> 0xC -> 0xE -> 0xF to turn on edram + // stagger EDRAM turn-on per EX (not both at same time) + + l_region_clock = p9hcd::CLK_REGION_ALL_BUT_EX_ANEP_DPLL; + l_l2sync_clock = 0; + l_l2pscom_mask = 0; + l_l3pscom_mask = 0; + + if (l_qcsr & BIT64(l_attr_chip_unit_pos << 1)) + { + l_region_clock |= p9hcd::CLK_REGION_EX0_L2_L3_REFR; + l_l2sync_clock |= BIT64(36); + FAPI_DBG("Sequence EX0 EDRAM enables via QPPM_QCCR[0-3]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(0))); + FAPI_TRY(fapi2::delay(12000, 200)); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(1))); + FAPI_TRY(fapi2::delay(1000, 200)); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(2))); + FAPI_TRY(fapi2::delay(4000, 200)); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(3))); + FAPI_TRY(fapi2::delay(1000, 200)); + } + else + { + l_l2pscom_mask |= (BIT64(2) | BIT64(10)); + l_l3pscom_mask |= (BIT64(4) | BIT64(6) | BIT64(8)); + } + + if (l_qcsr & BIT64((l_attr_chip_unit_pos << 1) + 1)) + { + l_region_clock |= p9hcd::CLK_REGION_EX1_L2_L3_REFR; + l_l2sync_clock |= BIT64(37); + FAPI_DBG("Sequence EX1 EDRAM enables via QPPM_QCCR[4-7]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(4))); + FAPI_TRY(fapi2::delay(12000, 200)); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(5))); + FAPI_TRY(fapi2::delay(1000, 200)); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(6))); + FAPI_TRY(fapi2::delay(4000, 200)); + FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(7))); + FAPI_TRY(fapi2::delay(1000, 200)); + } + else + { + l_l2pscom_mask |= (BIT64(3) | BIT64(11)); + l_l3pscom_mask |= (BIT64(5) | BIT64(7) | BIT64(9)); + } + + FAPI_DBG("Assert cache EX1 ID bit2 via CPLT_CTRL0[6]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(6))); + + FAPI_DBG("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]"); + FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<0, 4>(0x5). + insertFromRight<12, 8>(0x0). + insertFromRight<52, 12>(0x10); + FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64)); + + FAPI_DBG("Drop partial good fences via CPLT_CTRL1[4,5,6/7,8/9,10,11,12/13]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, + (l_region_clock | p9hcd::CLK_REGION_ANEP))); + + FAPI_DBG("Drop vital fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(3))); + + FAPI_DBG("Assert EX-L2 clock sync enables via QPPM_EXCGCR[36,37]"); + FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, l_l2sync_clock)); + + FAPI_DBG("Poll for EX-L2 clock sync dones via QPPM_QACSR[36,37]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CACHE_CLK_SYNC_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, EQ_QPPM_QACSR, l_data64)); + } + while(((l_data64 & l_l2sync_clock) != l_l2sync_clock) && + ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECLKSYNC_TIMEOUT().set_EQPPMQACSR(l_data64), + "EX-L2 Clock Sync Timeout"); + FAPI_DBG("EX-L2 clock sync done"); + + FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3))); + + FAPI_DBG("Set fabric group ID[%x] chip ID[%x] system ID[%x]", + l_attr_group_id, l_attr_chip_id, l_attr_system_id); + FAPI_TRY(getScom(i_target, EQ_CPLT_CONF0, l_data64)); + l_data64.insertFromRight<48, 4>(l_attr_group_id). + insertFromRight<52, 3>(l_attr_chip_id). + insertFromRight<56, 5>(l_attr_system_id); + FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0, l_data64)); + + // ------------------------------- + // Align chiplets + // ------------------------------- + + FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2))); + + FAPI_DBG("Assert force_align via CPLT_CTRL0[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(3))); + + FAPI_DBG("Set then unset clear_chiplet_is_aligned via SYNC_CONFIG[7]"); + FAPI_TRY(getScom(i_target, EQ_SYNC_CONFIG, l_data64)); + FAPI_TRY(putScom(i_target, EQ_SYNC_CONFIG, DATA_SET(7))); + FAPI_TRY(putScom(i_target, EQ_SYNC_CONFIG, DATA_UNSET(7))); + + FAPI_TRY(fapi2::delay( + CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + p9hcd::CLK_PERIOD_250PS / 1000, + CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + p9hcd::SIM_CYCLE_4U4D)); + + FAPI_DBG("Poll for cache chiplet aligned"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CACHE_CLK_START_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<9>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECPLTALIGN_TIMEOUT() + .set_EQCPLTSTAT0(l_data64), + "Cache Chiplets Aligned Timeout"); + FAPI_DBG("Cache chiplets aligned now"); + + FAPI_DBG("Drop force_align via CPLT_CTRL0[3]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(3))); + + // ------------------------------- + // Start cache clocks + // ------------------------------- + + FAPI_DBG("Clear all bits prior start cache clocks via SCAN_REGION_TYPE"); + FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO)); + + FAPI_DBG("Start cache clocks(all but anep+dpll) via CLK_REGION"); + l_data64 = (p9hcd::CLK_START_CMD | + l_region_clock | + p9hcd::CLK_THOLD_ALL); + FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64)); + + FAPI_DBG("Poll for cache clocks running via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CACHE_CLK_START_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64), + "Cache Clock Start Timeout"); + + FAPI_DBG("Check cache clocks running"); + FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64)); + + FAPI_ASSERT(((l_data64 & l_region_clock) == 0), + fapi2::PMPROC_CACHECLKSTART_FAILED().set_EQCLKSTAT(l_data64), + "Cache Clock Start Failed"); + FAPI_DBG("Cache clocks running now"); + + // ------------------------------- + // Cleaning up + // ------------------------------- + + if (((~l_attr_pg) & BITS32(4, 11)) && l_attr_system_ipl_phase != 4) + { + FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]"); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(18))); + } + + /// @todo ignore xstop checkstop in sim, review for lab + /* + FAPI_DBG("Check the Global Checkstop FIR"); + FAPI_TRY(getScom(i_target, EQ_XFIR, l_data64)); + FAPI_ASSERT(((l_data64 & BITS64(0, 27)) != 0), + fapi2::PMPROC_CACHE_XSTOP().set_EQXFIR(l_data64), + "Cache Chiplet Checkstop"); + */ + + FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2))); + + FAPI_DBG("Drop partial good and assert partial bad L2/L3 pscom masks"); + l_data64 = (l_l2pscom_mask | l_l3pscom_mask); + FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_data64)); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_startclocks"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H new file mode 100644 index 00000000..d0ad61d6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.H +/// @brief Quad Clock Start +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +#ifndef __P9_HCD_CACHE_STARTCLOCKS_H__ +#define __P9_HCD_CACHE_STARTCLOCKS_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_cache_startclocks_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_startclocks_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +extern "C" +{ + +/// @brief Quad Clock Start +/// @param [in] i_target TARGET_TYPE_EQ target +/// @return FAPI2_RC_SUCCESS if success, else error code + fapi2::ReturnCode + p9_hcd_cache_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + +} + +#endif // __P9_HCD_CACHE_STARTCLOCKS_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/Makefile b/src/import/chips/p9/procedures/hwp/core/Makefile new file mode 100644 index 00000000..15ace37d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/Makefile @@ -0,0 +1,55 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/core/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the core hardware procedure code. See the +# "corehcdfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/cache +export SUB_OBJDIR = /core + +GCC-CFLAGS += -mlongcall +include img_defs.mk +include corehcdfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(CORE_OBJECTS)) + +libcore.a: core + $(AR) crs $(OBJDIR)/libcore.a $(OBJDIR)/*.o + +.PHONY: clean core +core: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk new file mode 100644 index 00000000..b7c2abcc --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk @@ -0,0 +1,56 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/core/corehcdfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file corehcdfiles.mk +# +# @brief mk for including core hcode object files +# +########################################################################## +# Object Files +########################################################################## + +CORE-CPP-SOURCES += p9_hcd_core_arrayinit.C +CORE-CPP-SOURCES += p9_hcd_core_chiplet_init.C +CORE-CPP-SOURCES += p9_hcd_core_chiplet_reset.C +CORE-CPP-SOURCES += p9_hcd_core_gptr_time_initf.C +CORE-CPP-SOURCES += p9_hcd_core_initf.C +CORE-CPP-SOURCES += p9_hcd_core_occ_runtime_scom.C +CORE-CPP-SOURCES += p9_hcd_core_pcb_arb.C +CORE-CPP-SOURCES += p9_hcd_core_poweron.C +CORE-CPP-SOURCES += p9_hcd_core_ras_runtime_scom.C +CORE-CPP-SOURCES += p9_hcd_core_repair_initf.C +CORE-CPP-SOURCES += p9_hcd_core_runinit.C +CORE-CPP-SOURCES += p9_hcd_core_scomcust.C +CORE-CPP-SOURCES += p9_hcd_core_scominit.C +CORE-CPP-SOURCES += p9_hcd_core_startclocks.C +CORE-CPP-SOURCES += p9_thread_control.C +CORE-CPP-SOURCES += p9_sbe_instruct_start.C + +CORE-C-SOURCES += +CORE-S-SOURCES += + +CORE_OBJECTS += $(CORE-CPP-SOURCES:.C=.o) +CORE_OBJECTS += $(CORE-C-SOURCES:.c=.o) +CORE_OBJECTS += $(CORE-S-SOURCES:.S=.o) + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core.H new file mode 100644 index 00000000..1c766fb3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core.H +/// @brief Core Chiplet Procedure Includes +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 2 +/// + +#ifndef __P9_HCD_CORE_H__ +#define __P9_HCD_CORE_H__ + +#include <p9_hcd_core_arrayinit.H> +#include <p9_hcd_core_chiplet_init.H> +#include <p9_hcd_core_chiplet_reset.H> +#include <p9_hcd_core_gptr_time_initf.H> +#include <p9_hcd_core_initf.H> +#include <p9_hcd_core_occ_runtime_scom.H> +#include <p9_hcd_core_pcb_arb.H> +#include <p9_hcd_core_poweron.H> +#include <p9_hcd_core_ras_runtime_scom.H> +#include <p9_hcd_core_repair_initf.H> +#include <p9_hcd_core_scomcust.H> +#include <p9_hcd_core_scominit.H> +#include <p9_hcd_core_startclocks.H> + +#endif // __P9_HCD_CORE_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C new file mode 100644 index 00000000..0706e244 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C @@ -0,0 +1,123 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_arrayinit.C +/// @brief Core Initialize arrays +/// +/// Procedure Summary: +/// Use ABIST engine to zero out all arrays +/// Upon completion, scan0 flush all rings except Vital,Repair,GPTR,and TIME + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_quad_scom_addresses.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_hcd_common.H> +#include "p9_hcd_core_arrayinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +enum P9_HCD_CORE_ARRAYINIT_Private_Constants +{ + REGIONS_EXCEPT_VITAL = 0x7FF, + LOOP_COUNTER = 0x0000000000042FFF, + SELECT_SRAM = 0x1, + SELECT_EDRAM = 0x0, + START_ABIST_MATCH_VALUE = 0x0000000F00000000 +}; + +//------------------------------------------------------------------------------ +// Procedure: Core Initialize arrays +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_core_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_arrayinit"); + fapi2::buffer<uint64_t> l_data64; + +#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT) + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); +#endif + + /// @todo add DD1 attribute control + FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround"); + FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34))); + +#ifndef P9_HCD_STOP_SKIP_ARRAYINIT + + FAPI_DBG("Arrayinit all regions except vital"); + FAPI_TRY(p9_perv_sbe_cmn_array_init_module(l_perv, + REGIONS_EXCEPT_VITAL, + LOOP_COUNTER, + SELECT_SRAM, + SELECT_EDRAM, + START_ABIST_MATCH_VALUE)); + +#endif + +#ifndef P9_HCD_STOP_SKIP_FLUSH + + //-------------------------------------------- + // perform scan0 module for pervasive chiplet + //-------------------------------------------- + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest + // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has + // all stumps less than 8191, the loop can be removed. + + FAPI_DBG("Scan0 region:all_but_pll type:all_but_gptr_repr_time rings"); + + for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + p9hcd::SCAN0_REGION_ALL_BUT_PLL, + p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); + +#endif + + /// @todo add DD1 attribute control + FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround"); + FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34))); + +//#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT) +fapi_try_exit: +//#endif + + FAPI_INF("<<p9_hcd_core_arrayinit"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H new file mode 100644 index 00000000..dde880ee --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_arrayinit.H +/// @brief Core Initialize arrays +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_ARRAYINIT_H__ +#define __P9_HCD_CORE_ARRAYINIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_arrayinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_arrayinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Core Initialize arrays +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} + +#endif // __P9_HCD_CORE_ARRAYINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C new file mode 100644 index 00000000..9007a7f8 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C @@ -0,0 +1,94 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_init.C +/// @brief Core Flush/Initialize +/// +/// Procedure Summary: +/// Switch the core glitchless mux to allow DPLL clocks on the clock grid +/// Clocking: +/// - setup controls based on DPLL frequency +/// - assert PM sync_enable (4x core, 2 x L2), +/// DCCs and SkewAdjust starts aligning clocks +/// Scan0 flush all chiplet rings except VITAL, GPTR and TIME + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_quad_scom_addresses.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_hcd_common.H> +#include "p9_hcd_core_chiplet_init.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Core Flush/Initialize +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_core_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_chiplet_init"); + /* + #ifndef P9_HCD_STOP_SKIP_FLUSH + //-------------------------------------------- + // perform scan0 module for pervasive chiplet + //-------------------------------------------- + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest + // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has + // all stumps less than 8191, the loop can be removed. + + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + + FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings"); + + for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + p9hcd::SCAN0_REGION_PERV_CORE, + p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); + + fapi_try_exit: + + #endif + */ + FAPI_INF("<<p9_hcd_core_chiplet_init"); + return fapi2::current_err; +} + + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H new file mode 100644 index 00000000..c86b128c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_init.H +/// @brief Core Flush/Initialize +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_CHIPLET_INIT_H__ +#define __P9_HCD_CORE_CHIPLET_INIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_chiplet_init_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_init_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Core Flush/Initialize +/// @param [in] i_target TARGET_TYPE_CORE target +/// @return FAPI2_RC_SUCCESS if success, else error code + fapi2::ReturnCode + p9_hcd_core_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} + +#endif // __P9_HCD_CORE_CHIPLET_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C new file mode 100644 index 00000000..c3bd9567 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C @@ -0,0 +1,176 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_reset.C +/// @brief Core Chiplet Reset +/// +/// Procedure Summary: +/// Reset core chiplet logic +/// (TODO: check with Andreas on the effect of a CME based Endpoint reset +/// relative to the CorePPM path) +/// Clocking: +/// - setup cache sector buffer strength, +/// pulse mode and pulsed mode enable values +/// (attribute dependency Nimbus/Cumulus) +/// - Drop glsmux async reset +/// Scan0 flush entire core chiplet + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_quad_scom_addresses.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_hcd_common.H> +#include "p9_hcd_core_chiplet_reset.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +enum P9_HCD_CORE_CHIPLET_RESET_CONSTANTS +{ + // (1)PCB_EP_RESET + // (2)CLK_ASYNC_RESET + // (3)PLL_TEST_EN + // (4)PLLRST + // (5)PLLBYP + // (11)EDIS + // (12)VITL_MPW1 + // (13)VITL_MPW2 + // (14)VITL_MPW3 + // (16)VITL_THOLD + // (18)FENCE_EN + // (22)FUNC_CLKSEL + // (25)PCB_FENCE + // (26)LVLTRANS_FENCE + C_NET_CTRL0_INIT_VECTOR = (BIT64(1) | BITS64(3, 3) | BITS64(11, 4) | + BIT64(16) | BIT64(18) | BIT64(22) | BITS64(25, 2)), + CORE_GLSMUX_RESET_DELAY_CORE_CYCLES = 200 +}; + +//------------------------------------------------------------------------------ +// Procedure: Core Chiplet Reset +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_core_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_chiplet_reset"); + fapi2::buffer<uint64_t> l_data64; + + //-------------------------- + // Reset core chiplet logic + //-------------------------- + // If there is an unused, powered-off core chiplet which needs to be + // configured in the following steps to setup the PCB endpoint. + + FAPI_DBG("Init NET_CTRL0[1,3-5,11-14,16,18,22,25,26],step needed for hotplug"); + l_data64 = C_NET_CTRL0_INIT_VECTOR; + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WOR, l_data64)); + l_data64 |= BIT64(2); // make sure bit 2 is untouched + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, l_data64)); + + FAPI_DBG("Flip core glsmux to refclk via PPM_CGCR[3]"); + FAPI_TRY(putScom(i_target, C_PPM_CGCR, MASK_SET(0))); + + FAPI_DBG("Assert core progdly and DCC bypass via NET_CTRL1[1,2]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL1_WOR, MASK_OR(1, 2, 3))); + + FAPI_DBG("Drop vital thold via NET_CTRL0[16]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(16))); + + /// @todo optional setup sector buffer strength, pulse mode and pulsed mode enable + + FAPI_DBG("Drop core glsmux reset via PPM_CGCR[0]"); + FAPI_TRY(putScom(i_target, C_PPM_CGCR, 0)); + + FAPI_TRY(fapi2::delay( + CORE_GLSMUX_RESET_DELAY_CORE_CYCLES * p9hcd::CLK_PERIOD_250PS / 1000, + CORE_GLSMUX_RESET_DELAY_CORE_CYCLES * p9hcd::SIM_CYCLE_4U4D)); + + FAPI_DBG("Flip core glsmux to DPLL via PPM_CGCR[3]"); + FAPI_TRY(putScom(i_target, C_PPM_CGCR, MASK_SET(3))); + + FAPI_DBG("Assert chiplet enable via NET_CTRL0[0]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WOR, MASK_SET(0))); + + FAPI_DBG("Drop PCB endpoint reset via NET_CTRL0[1]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(1))); + + FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(26))); + + FAPI_DBG("Drop PCB fence via NET_CTRL0[25]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(25))); + +#ifndef P9_HCD_STOP_SKIP_FLUSH + //-------------------------------------------- + // perform scan0 module for pervasive chiplet + //-------------------------------------------- + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest + // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has + // all stumps less than 8191, the loop can be removed. + + // Putting in block to avoid c++ crosses initialization compile error + { + uint32_t l_loop; + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + + FAPI_DBG("Scan0 region:all_but_vital type:gptr_repr_time rings"); + + for(l_loop = 0; l_loop < P9_HCD_SCAN_GPTR_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + p9hcd::SCAN0_REGION_ALL, + p9hcd::SCAN0_TYPE_GPTR_REPR_TIME)); + + FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings"); + + for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++) + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv, + p9hcd::SCAN0_REGION_ALL, + p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME)); + } +#endif + + /// @todo add VDM_ENABLE attribute control + FAPI_DBG("Assert vdm enable via CPPM_VDMCR[0]"); + FAPI_TRY(putScom(i_target, C_PPM_VDMCR_OR, MASK_SET(0))); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_core_chiplet_reset"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H new file mode 100644 index 00000000..9db24521 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_reset.H +/// @brief Core Chiplet Reset +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_CHIPLET_RESET_H__ +#define __P9_HCD_CORE_CHIPLET_RESET_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_chiplet_reset_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_reset_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Core Chiplet Reset +/// @param [in] i_target TARGET_TYPE_CORE target +/// @return FAPI2_RC_SUCCESS if success, else error code + fapi2::ReturnCode + p9_hcd_core_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} + +#endif // __P9_HCD_CORE_CHIPLET_RESET_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C new file mode 100644 index 00000000..fa147a3d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C @@ -0,0 +1,81 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_gptr_time_initf.C +/// @brief Load Core GPTR and Time rings +/// +/// Procedure Summary: +/// initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// to produce #G VPD contents +/// Check for the presence of core override GPTR ring from image +/// (this is new for P9) +/// if found, apply; if not, apply core GPTR from image +/// Check for the presence of core override TIME ring from image; +/// if found, apply; if not, apply core base TIME from image + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include <p9_ring_id.h> +#include "p9_hcd_core_gptr_time_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Load Core GPTR and Time rings +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_hcd_core_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_gptr_time_initf"); + + FAPI_DBG("Scan ec_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target, ec_gptr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ec_gptr)"); + + FAPI_DBG("Scan ec_time ring"); + FAPI_TRY(fapi2::putRing(i_target, ec_time, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ec_time)"); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_core_gptr_time_initf"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H new file mode 100644 index 00000000..22c88c3f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_gptr_time_initf.H +/// @brief Load Core GPTR and Time rings +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_GPTR_TIME_INIT_H__ +#define __P9_HCD_CORE_GPTR_TIME_INIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_gptr_time_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_gptr_time_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Load Core GPTR and Time rings +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_GPTR_TIME_RING - EC target, uint32 +/// pointer to RS4 content<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} + +#endif // __P9_HCD_CORE_GPTR_TIME_INIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C new file mode 100644 index 00000000..86e72aac --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C @@ -0,0 +1,72 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_initf.C +/// @brief Core scan init +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// Check for the presence of core FUNC override rings from image; +/// if found, apply; if not, apply core base FUNC rings from image +/// Note: FASTINIT ring (eg CMSK ring) is setup at this point to limit the +/// stumps that participate in FUNC ring scanning (this is new for P9). +/// (TODO to make sure the image build support is in place) +/// Note : if in fused mode, both core rings will be initialized to the same +/// values via multicast scans + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include "p9_hcd_core_initf.H" + +//----------------------------------------------------------------------------- +// Procedure: Core scan init +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_hcd_core_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_initf"); + + FAPI_DBG("Scan ec_func ring"); + FAPI_TRY(putRing(i_target, ec_func), + "Error from putRing (ec_func)"); + FAPI_DBG("Scan ec_mode ring"); + FAPI_TRY(putRing(i_target, ec_mode), + "Error from putRing (ec_mode)"); + +fapi_try_exit: + FAPI_INF("<<p9_hcd_core_initf"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H new file mode 100644 index 00000000..accbf0ea --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_initf.H +/// @brief Core scan init +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_INITF_H__ +#define __P9_HCD_CORE_INITF_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Core scan init +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_FUNC_RING - EC target, uint32 +/// pointer to RS4 content<br> +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} + +#endif // __P9_HCD_CORE_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C new file mode 100644 index 00000000..9211d7fc --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C @@ -0,0 +1,94 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_occ_runtime_scom.C +/// @brief Core OCC runtime SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from OCC code that are put somewhere TBD +/// (TODO . revisit with OCC FW team) +/// OCC FW sets up value in the TBD SCOM section +/// This was not leverage in P8 with the demise of CPMs +/// Placeholder at this point +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_occ_runtime_scom.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +#define host_runtime_scom 0 + +//----------------------------------------------------------------------------- +// Procedure: Core OCC runtime SCOMS +//----------------------------------------------------------------------------- + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_core_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) + { + +#if 0 + + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, occ_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching OCC Runtime SCOM routine") + // - bsrd D0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H new file mode 100644 index 00000000..7dad1c6e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_occ_runtime_scom.H +/// @brief Core OCC runtime SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ +#define __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_occ_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_core_occ_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core OCC runtime SCOMS +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem ATTR_CORE_OCC_SCOM_LOC - EC target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C new file mode 100644 index 00000000..729f98b7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C @@ -0,0 +1,115 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_pcb_arb.C +/// @brief Core Chiplet PCB Arbitration +/// +/// Procedure Summary: +/// If CME, +/// 1.Request PCB Mux, via write to PCB_MUX_REQ_C0 @ CCSCR_OR +/// - setBit(5) @ CME_LOCAL_CORE_STOP_CONTROL_REGISTER_OR_0510 +/// 2.Poll for PCB Mux grant, via read from +/// Polled Timeout: ns +/// - getBit() @ +/// Else (SBE), +/// Nop (as the CME is not running in bringing up the first Core) +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <p9_quad_scom_addresses.H> +#include <p9_hcd_common.H> +#include "p9_hcd_core_pcb_arb.H" + +//----------------------------------------------------------------------------- +// Constant Definitions: Core Chiplet PCB Arbitration +//----------------------------------------------------------------------------- + + +fapi2::ReturnCode +p9_hcd_core_pcb_arb( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const p9hcd::P9_HCD_CME_CORE_MASKS i_core_mask, + const p9hcd::P9_HCD_PCB_ARBITER_CTRL i_request) +{ + FAPI_INF(">>p9_hcd_core_pcb_arb: Core[%d] Req[%d]", i_core_mask, i_request); + +#ifdef P9_HCD_CME_BUILD + + FAPI_DBG("Request or Release the PCB Arbiter"); + out32((i_request ? CME_LCL_SICR_OR : CME_LCL_SICR_CLR), + (i_core_mask << SHIFT32(11))); + + FAPI_DBG("Poll for PCB Arbiter Granted"); + uint32_t l_sisr; + + do + { + l_sisr = (in32(CME_LCL_SISR) >> SHIFT32(11)); + + if(( i_request && ((i_core_mask & l_sisr) == i_core_mask)) || + ((!i_request) && ((i_core_mask & (~l_sisr)) == i_core_mask))) + { + break; + } + } + while(1); + +#else + + FAPI_DBG("Check for PCB Arbiter Granted to Core"); + + /// @todo require core to cme target conversion + /* + fapi2::buffer<uint64_t> l_data64; + FAPI_TRY(getScom(i_target, EX_0_CME_LCL_SISR_SCOM, l_data64)); + + FAPI_ASSERT(((l_data64 & (i_core_mask << SHIFT64(11))) != + (i_core_mask << SHIFT64(11))), + fapi2::PMPROC_COREPCBARB_GRANTCME().set_CMESISR(l_data64), + "PCB Arbiter is Granted to CME"); + */ + FAPI_DBG("PCB Arbiter is Granted to Core"); + + /// @todo MPIPL: if check grant to cme, consider to overide it back to core + +//fapi_try_exit: + +#endif + + FAPI_INF("<<p9_hcd_core_pcb_arb"); + + return fapi2::current_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H new file mode 100644 index 00000000..f3bfad93 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H @@ -0,0 +1,68 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_pcb_arb.H +/// @brief Core Chiplet PCB Arbitration +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_PCB_ARB_H__ +#define __P9_HCD_CORE_PCB_ARB_H__ + +#include <fapi2.H> +#include <p9_hcd_common.H> + +/// @typedef p9_hcd_core_pcb_arb_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_pcb_arb_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&, + const p9hcd::P9_HCD_CME_CORE_MASKS i_core_mask, + const p9hcd::P9_HCD_PCB_ARBITER_CTRL i_request); + +extern "C" +{ + +/// @brief Core Chiplet PCB Arbitration +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_pcb_arb( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const p9hcd::P9_HCD_CME_CORE_MASKS i_core_mask, + const p9hcd::P9_HCD_PCB_ARBITER_CTRL i_request); + +} + +#endif // __P9_HCD_CORE_PCB_ARB_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C new file mode 100644 index 00000000..5e66f673 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C @@ -0,0 +1,88 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_poweron.C +/// @brief Core Chiplet Power-on +/// +/// Procedure Summary: +/// Set glsmux async reset +/// Command the core PFET controller to power-on, via putscom to CPPM +/// Check for valid power on completion, via getscom from CPPM +/// Polled Timeout: 100us + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include <p9_quad_scom_addresses.H> +#include <p9_hcd_common.H> +#include <p9_common_poweronoff.H> +#include <p9_common_poweronoff.C> +#include "p9_hcd_core_poweron.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core Chiplet Power-on +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_hcd_core_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_poweron"); + fapi2::buffer<uint64_t> l_data64; + + //------------------------- + // Prepare to power on core + //------------------------- + + FAPI_DBG("Drop chiplet enable via NET_CTRL0[0]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(0))); + + FAPI_DBG("Assert core glsmux reset via PPM_CGCR[0]"); + FAPI_TRY(putScom(i_target, C_PPM_CGCR, MASK_SET(0))); + + //---------------------- + // Power on core chiplet + //---------------------- + + FAPI_DBG("Power on core chiplet"); + FAPI_TRY(p9_common_poweronoff<fapi2::TARGET_TYPE_CORE>(i_target, p9power::POWER_ON_VDD)); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_core_poweron"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H new file mode 100644 index 00000000..91b73cf9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_poweron.H +/// @brief Core Chiplet Power-on +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_POWERON_H__ +#define __P9_HCD_CORE_POWERON_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_poweron_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_poweron_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ +/// @brief Core Chiplet Power-on +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_* +/// +/// @retval FAPI2_RC_SUCCESS if success, else error code + fapi2::ReturnCode + p9_hcd_core_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); +} + +#endif // __P9_HCD_CORE_POWERON_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C new file mode 100644 index 00000000..6ad7100f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C @@ -0,0 +1,165 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_ras_runtime_scom.C +/// @brief FSP/Host run-time SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from FSP based PRD, etc that are put on the core image +/// by STOP API calls +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (the SBE case), return +/// Else call the function at the pointer; +/// pointer is filled in by STOP image build +/// Run-time updates from Host code that are put on the core image by +/// STOP API calls +/// Restore Hypervisor, Host PRD, etc. SCOMs +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_ras_runtime_scom.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +#define host_runtime_scom 0 + +//----------------------------------------------------------------------------- +// Procedure: FSP/Host run-time SCOMS +//----------------------------------------------------------------------------- + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_core_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) + { + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, sp_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching SP Runtime SCOM routine") + // - bsrd D0 + // - 1: + // + + // Run the SCOM sequence if the SCOM procedure is defined. + // - la A0, host_runtime_scom + // - ld D1, 0, A0 + // - braz D1, 1f + + // Prep P1 + // - setp1_mcreadand D0 +#if 0 + // Disable the AISS to allow the override + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~(BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - ori D0, D0, (BIT(15)) + // - andi D0, D0, ~(BIT(21)) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + // Branch to sub_slw_runtime_scom() + FAPI_INF("Launching Host Runtime SCOM routine") + // - bsrd D1 + + // Prep P1 + // - setp1_mcreadand D0 +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - andi D0, D0, ~(BIT(15)) + // - ori D0, D0, BIT(21) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - ori D0, D0, (BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - bra 2f + // - 1: + // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped + // - setp1_mcreadand D0 +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~BIT(1) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - andi D0, D0, ~(BIT(15)) + // - ori D0, D0, BIT(21) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - ori D0, D0, (BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - 2: + + // If using cv_multicast, we need to set the magic istep number here + // - la A0, p9_sbe_select_ex_control + // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX + // - braz D0, 3f + FAPI_DBG("Setting istep num to magic number because cv_multicast is set") + // - lpcs P1, MBOX_SBEVITAL_0x0005001C + // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) + // - 3: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H new file mode 100644 index 00000000..511b35c4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_ras_runtime_scom.H +/// @brief FSP/Host run-time SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ +#define __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_ras_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_core_ras_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief FSP/Host run-time SCOMS +/// +/// @param [in] i_target TARGET_TYPE_CORE target +// +/// @attr +/// @attritem ATTR_CORE_RAS_SCOM_LOC - EC target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C new file mode 100644 index 00000000..b8f6be7e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C @@ -0,0 +1,76 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_repair_initf.C +/// @brief Load Repair ring for core +/// +/// Procedure Summary: +/// Load core ring images from that came from MVPD into the image +/// These rings must contain ALL chip customization data. This includes the +/// following: Array Repair and DTS calibration settings +/// Historically this was stored in MVPD keywords are #R, #G. Still stored +/// in MVPD, but SBE image is customized with rings for booting cores +/// at build time + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include <p9_ring_id.h> +#include "p9_hcd_core_repair_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Load Repair ring for core +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_hcd_core_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_repair_initf"); + + FAPI_DBG("Scan ec_repr ring"); + FAPI_TRY(fapi2::putRing(i_target, ec_repr, + fapi2::RING_MODE_HEADER_CHECK), + "Error from putRing (ec_repr)"); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_core_repair_initf"); + return fapi2::current_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H new file mode 100644 index 00000000..a998c4bd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_repair_initf.H +/// @brief Load Repair ring for core +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_REPAIR_INITF_H__ +#define __P9_HCD_CORE_REPAIR_INITF_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_repair_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_repair_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Load Repair ring for core +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_REPAIR_RING - EC target, uint32 +/// pointer to RS4 content +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} + +#endif // __P9_HCD_CORE_REPAIR_INITF_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C new file mode 100644 index 00000000..54ed6dd5 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C @@ -0,0 +1,83 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scomcust.C +/// @brief Core Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Dynamically built (and installed) routine that is inserted by the .XIP +/// Customization. process. (New for P9) (TODO: this part of the process is +/// a placeholder at this point) +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (a potential early value); return +/// Else call the function at the pointer; +/// pointer is filled in by XIP Customization +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_scomcust.H" + +//----------------------------------------------------------------------------- +// Constant Definitions: Core Customization SCOMs +//----------------------------------------------------------------------------- + +extern "C" +{ + + fapi2::ReturnCode + p9_hcd_core_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) + { + +#if 0 + + fapi2::buffer<uint64_t> data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H new file mode 100644 index 00000000..f69ce528 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scomcust.H +/// @brief Core Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_SCOMCUST_H__ +#define __P9_HCD_CORE_SCOMCUST_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_scomcust_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_hcd_core_scomcust_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} // extern C + +#endif // __P9_HCD_CORE_SCOMCUST_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C new file mode 100644 index 00000000..c05caed4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C @@ -0,0 +1,85 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scominit.C +/// @brief Core SCOM Inits +/// +/// Procedure Summary: +/// Apply any coded SCOM initialization to core +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include <p9_quad_scom_addresses.H> +#include <p9_hcd_common.H> +#include "p9_hcd_core_scominit.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core SCOM Inits +//----------------------------------------------------------------------------- + + +fapi2::ReturnCode +p9_hcd_core_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_scominit"); + fapi2::buffer<uint64_t> l_data64; + + /// @todo how about bit 6? + FAPI_DBG("Restore SYNC_CONFIG[8] for stop1"); + FAPI_TRY(getScom(i_target, C_SYNC_CONFIG, l_data64)); + FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_SET(8))); + + /// @todo set the sample pulse count (bit 6:9) + /// enable the appropriate loops + /// (needs investigation with the Perv team on the EC wiring). + FAPI_DBG("Enable DTS sampling via THERM_MODE_REG[5]"); + FAPI_TRY(getScom(i_target, C_THERM_MODE_REG, l_data64)); + FAPI_TRY(putScom(i_target, C_THERM_MODE_REG, DATA_SET(5))); + + FAPI_DBG("Set core as ready to run in STOP history register"); + FAPI_TRY(putScom(i_target, C_PPM_SSHSRC, 0)); + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_core_scominit"); + return fapi2::current_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H new file mode 100644 index 00000000..7065028e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scominit.H +/// @brief Core SCOM Inits +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_SCOMINIT_H__ +#define __P9_HCD_CORE_SCOMINIT_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_scominit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_scominit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Core SCOM Inits +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_hcd_core_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} // extern C + +#endif // __P9_HCD_CORE_SCOMINIT_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C new file mode 100644 index 00000000..3cccb8b5 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -0,0 +1,285 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_startclocks.C +/// @brief Core Clock Start +/// +/// Procedure Summary: +/// (Done) Drop partial good regional fences(always drop vital and pervasive) +/// (Done) Drop vital fence +/// (Done) Reset abst clock muxsel, sync muxsel +/// (TODO) +set fabric node/chip ID (read from nest chiplet) +/// (Done) module align_chiplets +/// (Done) - set flushmode_inh to exit flush mode +/// (Done) - set force_align +/// (Done) - set clear_chiplet_is_aligned +/// (Done) - unset clear_chiplet_is_aligned +/// (Done) - wait +/// (Done) - check chiplet_is_aligned +/// (Done) - clear force_align +/// (Done) module start_clocks +/// (Done) - set flush mode(alerady set in align_chiplets) +/// (Done) - Clear scan region type register +/// (Done) - Start arrays + nsl regions +/// (Done) - Start sl + refresh clock regions +/// (Done) Check for clocks started, If not, error +/// (Done) Drop the core to cache logical fence +/// (Done) Check for core xstop, If so, error +/// (Done) Clear flushmode_inh to go into flush mode +/// (Done) Check cache/core chiplet_is_aligned + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_quad_scom_addresses.H> +#include <p9_hcd_common.H> +#include "p9_hcd_core_startclocks.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +enum P9_HCD_CORE_STARTCLOCKS_CONSTANTS +{ + CORE_CLK_SYNC_TIMEOUT_IN_MS = 1, + CORE_CLK_START_TIMEOUT_IN_MS = 1, + CORE_CLK_ALIGN_DELAY_CACHE_CYCLES = 255 +}; + +//------------------------------------------------------------------------------ +// Procedure: Core Clock Start +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_hcd_core_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_INF(">>p9_hcd_core_startclocks"); + fapi2::buffer<uint64_t> l_data64; + uint32_t l_timeout; + uint32_t l_attr_pg; + uint8_t l_attr_chip_unit_pos; + uint8_t l_attr_system_ipl_phase; + uint8_t l_attr_runn_mode; + fapi2::Target<fapi2::TARGET_TYPE_EQ> l_quad = + i_target.getParent<fapi2::TARGET_TYPE_EQ>(); + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_target.getParent<fapi2::TARGET_TYPE_PERV>(); + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RUNN_MODE, l_sys, + l_attr_runn_mode)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys, + l_attr_system_ipl_phase)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, l_perv, + l_attr_pg)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + l_attr_chip_unit_pos)); + l_attr_chip_unit_pos = (l_attr_chip_unit_pos - + p9hcd::PERV_TO_CORE_POS_OFFSET) % 4; + + // ---------------------------- + // Prepare to start core clocks + // ---------------------------- + + if (l_attr_system_ipl_phase == + fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) + { + FAPI_DBG("Set CPLT_CTRL0[AVP_MODE] for cache-contained execution"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(5))); + } + + /// @todo add DD1 attribute control + FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround"); + FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34))); + + FAPI_DBG("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]"); + FAPI_TRY(getScom(i_target, C_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<0, 4>(0x5). + insertFromRight<12, 8>(0x0). + insertFromRight<52, 12>(0x10); + FAPI_TRY(putScom(i_target, C_OPCG_ALIGN, l_data64)); + + /// @todo partial good information via attribute, drop all fences for now + FAPI_DBG("Drop partial good fences via CPLT_CTRL1[4-13]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_CLEAR, MASK_CLR(4, 11, 0x7FF))); + + FAPI_DBG("Drop vital fence via CPLT_CTRL1[3]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_CLEAR, MASK_SET(3))); + + FAPI_DBG("Drop skew sense to skew adjust fence via NET_CTRL0[22]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(22))); + + FAPI_DBG("Assert core clock sync enable via CPPM_CACCR[15]"); + FAPI_TRY(putScom(i_target, C_CPPM_CACCR_OR, MASK_SET(15))); + + FAPI_DBG("Poll for core clock sync done via CPPM_CACSR[13]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CORE_CLK_START_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, C_CPPM_CACSR, l_data64)); + } + while((l_data64.getBit<13>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CORECLKSYNC_TIMEOUT().set_COREPPMCACSR(l_data64), + "Core Clock Sync Timeout"); + FAPI_DBG("Core clock sync done"); + + FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3))); + + // ------------------------------- + // Align chiplets + // ------------------------------- + + FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(2))); + + FAPI_DBG("Assert force_align via CPLT_CTRL0[3]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(3))); + + FAPI_DBG("Set then unset clear_chiplet_is_aligned via SYNC_CONFIG[7]"); + FAPI_TRY(getScom(i_target, C_SYNC_CONFIG, l_data64)); + FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_SET(7))); + FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_UNSET(7))); + + FAPI_TRY(fapi2::delay( + CORE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + p9hcd::CLK_PERIOD_250PS / 1000, + CORE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE * + p9hcd::SIM_CYCLE_4U4D)); + + FAPI_DBG("Poll for core chiplet aligned"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CORE_CLK_START_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<9>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CORECPLTALIGN_TIMEOUT() + .set_CORECPLTSTAT0(l_data64), + "Core Chiplets Aligned Timeout"); + FAPI_DBG("Core chiplets aligned now"); + + FAPI_DBG("Drop force_align via CPLT_CTRL0[3]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_SET(3))); + + // ------------------------------- + // Start core clocks + // ------------------------------- + + FAPI_DBG("Clear all bits prior start core clocks via SCAN_REGION_TYPE"); + FAPI_TRY(putScom(i_target, C_SCAN_REGION_TYPE, MASK_ZERO)); + + if (!l_attr_runn_mode) + { + + FAPI_DBG("Start core clocks(all but pll) via CLK_REGION"); + l_data64 = (p9hcd::CLK_START_CMD | + p9hcd::CLK_REGION_ALL_BUT_PLL | + p9hcd::CLK_THOLD_ALL); + FAPI_TRY(putScom(i_target, C_CLK_REGION, l_data64)); + + FAPI_DBG("Poll for core clocks running via CPLT_STAT0[8]"); + l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) * + CORE_CLK_START_TIMEOUT_IN_MS; + + do + { + FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64)); + } + while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0)); + + FAPI_ASSERT((l_timeout != 0), + fapi2::PMPROC_CORECLKSTART_TIMEOUT().set_CORECPLTSTAT(l_data64), + "Core Clock Start Timeout"); + + FAPI_DBG("Check core clocks running via CLOCK_STAT_SL[4-13]"); + FAPI_TRY(getScom(i_target, C_CLOCK_STAT_SL, l_data64)); + + FAPI_ASSERT(((l_data64 & p9hcd::CLK_REGION_ALL_BUT_PLL) == 0), + fapi2::PMPROC_CORECLKSTART_FAILED().set_CORECLKSTAT(l_data64), + "Core Clock Start Failed"); + FAPI_DBG("Core clocks running now"); + + } + + // ------------------------------- + // Cleaning up + // ------------------------------- + + if ((~l_attr_pg) & BITS32(4, 11)) + { + FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]"); + FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(18))); + } + + /// @todo ignore xstop checkstop in sim, review for lab + /* + FAPI_DBG("Check the Global Checkstop FIR"); + FAPI_TRY(getScom(i_target, C_XFIR, l_data64)); + FAPI_ASSERT(((l_data64 & BITS64(0, 27)) != 0), + fapi2::PMPROC_CORE_XSTOP().set_COREXFIR(l_data64), + "Core Chiplet Checkstop"); + */ + + FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); + FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_SET(2))); + + if (!l_attr_runn_mode && l_attr_system_ipl_phase != + fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) + { + FAPI_DBG("Drop Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]"); + FAPI_TRY(putScom(l_quad, + (l_attr_chip_unit_pos < 2) ? + EX_0_CME_SCOM_SICR_CLEAR : EX_1_CME_SCOM_SICR_CLEAR, + (BIT64(6 + (l_attr_chip_unit_pos % 2)) | + BIT64(8 + (l_attr_chip_unit_pos % 2))))); + } + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_core_startclocks"); + return fapi2::current_err; +} + + + + diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H new file mode 100644 index 00000000..75e94909 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_startclocks.H +/// @brief Core Clock Start +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_CORE_STARTCLOCKS_H__ +#define __P9_HCD_CORE_STARTCLOCKS_H__ + +#include <fapi2.H> + +/// @typedef p9_hcd_core_startclocks_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_startclocks_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +extern "C" +{ + +/// @brief Quad Clock Start +/// @param [in] i_target TARGET_TYPE_EX target +/// @return FAPI2_RC_SUCCESS if success, else error code + fapi2::ReturnCode + p9_hcd_core_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} + +#endif // __P9_HCD_CORE_STARTCLOCKS_H__ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C new file mode 100644 index 00000000..fb6affa0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_instruct_start.C +/// @brief +/// Starts instructions on 1 core, thread 0. +/// Thread 0 will be started at CIA scan flush value of 0. +// +// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB +// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p9_sbe_instruct_start.H> + +extern "C" +{ + +/// +/// p9_sbe_instruct_start HWP entry point (Defined in .H file) +/// + fapi2::ReturnCode p9_sbe_instruct_start( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) + { + fapi2::buffer<uint64_t> l_rasStatusReg(0); + uint64_t l_state = 0; + FAPI_DBG("Entering ..."); + + FAPI_INF("Starting instruction on thread 0"); + FAPI_TRY(p9_thread_control(i_target, 0b1000, PTC_CMD_START, false, + l_rasStatusReg, l_state), + "p9_sbe_instruct_start: p9_thread_control() returns an error"); + + fapi_try_exit: + FAPI_DBG("Exiting ..."); + return fapi2::current_err; + } + +} // extern "C" +/* End: */ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H new file mode 100644 index 00000000..d143fd43 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H @@ -0,0 +1,70 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_instruct_start.C +/// @brief Placeholder for overrides needed to step the core from cache-contained execution to expand to memory +/// +// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: HB + +#ifndef _PROC_SBE_INSTRUCT_START_H_ +#define _PROC_SBE_INSTRUCT_START_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi2.H> +#include <p9_thread_control.H> + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode +(*p9_sbe_instruct_start_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ +extern "C" +{ +//------------------------------------------------------------------------------ +// Hardware Procedure +//------------------------------------------------------------------------------ +/// +/// @brief Calls thread_control to start instruction on thread 0. +/// This is to be called during IPL (istep 5.2) +/// +/// @param[in] i_target Reference to core target +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code +/// + fapi2::ReturnCode p9_sbe_instruct_start( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} // extern "C" + +#endif // _PROC_SBE_INSTRUCT_START_H_ diff --git a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C new file mode 100644 index 00000000..529fd829 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C @@ -0,0 +1,703 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_thread_control.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_thread_control.C +/// @brief Implementation of sreset, start, stop and step +/// + +// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Quad +// *HWP Level: 2 +// Current Status: Only start function tested as working +// *HWP Consumed by: FSP:HB:HS + +#include <fapi2.H> +#include <p9_thread_control.H> + +using fapi2::TARGET_TYPE_EX; +using fapi2::TARGET_TYPE_CORE; + +using fapi2::FAPI2_RC_SUCCESS; + +// The control bits for each thread are contained in DIRECT_CONTROLS +// in regular offsets. This map allows us to go from a thread_bitset +// to a generic register with the proper bits set. We can then shift +// this result to align with the actual operation bit in the reg. +// PS. this map works for C_RAS_STATUS as well. +static const uint64_t g_control_reg_map[] = +{ + 0x0000000000000000, // b0000, no threads + 0x0000008000000000, // b0001, thread 3 + 0x0000800000000000, // b0010, thread 2 + 0x0000808000000000, // b0011, thread 2,3 + 0x0080000000000000, // b0100, thread 1 + 0x0080008000000000, // b0101, thread 1,3 + 0x0080800000000000, // b0110 + 0x0080808000000000, // b0111 + 0x8000000000000000, // b1000 + 0x8000008000000000, // b1001 + 0x8000800000000000, // b1010 + 0x8000808000000000, // b1011 + 0x8080000000000000, // b1100 + 0x8080008000000000, // b1101 + 0x8080800000000000, // b1110 + 0x8080808000000000, // b1111 +}; + +//-------------------------------------------------------------------------- +// Function definitions +//-------------------------------------------------------------------------- + +fapi2::ReturnCode p9_thread_control_sreset( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg); + +fapi2::ReturnCode p9_thread_control_start( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg); + +fapi2::ReturnCode p9_thread_control_stop( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg); + +fapi2::ReturnCode p9_thread_control_step( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg); + +fapi2::ReturnCode p9_thread_control_query( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, + fapi2::buffer<uint64_t>& o_rasStatusReg, + uint64_t& o_state); + +//-------------------------------------------------------------------------- +/// @brief threads_running : static funtion to encapsulate the running state +/// @param[in] i_target core target +/// @param[in] i_thread normal core thread bitset (0b0000..0b1111) +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @param[out] o_ok true if the threads are running +/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded +//-------------------------------------------------------------------------- +static inline fapi2::ReturnCode threads_running( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, + fapi2::buffer<uint64_t>& o_rasStatusReg, + bool& o_ok) +{ + // Running is defined as not in maint mode and not quiesced. + uint64_t l_state = 0; + FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state), + "threads_running(): p9_thread_control_query() returns an error."); + o_ok = (l_state & THREAD_STATE_RUNNING); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief threads_in_maint : static funtion to encapsulate the maint state +/// @param[in] i_target core target +/// @param[in] i_thread normal core thread bitset (0b0000..0b1111) +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @param[out] o_ok true if the threads are in maint mode +/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded +//-------------------------------------------------------------------------- +static inline fapi2::ReturnCode threads_in_maint( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, + fapi2::buffer<uint64_t>& o_rasStatusReg, + bool& o_ok) +{ + uint64_t l_state = 0; + FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state), + "threads_in_maint(): p9_thread_control_query() returns an error."); + o_ok = (l_state & THREAD_STATE_MAINT); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief all_threads_stopped : static funtion to encapsulate the stopped state +/// @param[in] i_target core target +/// @param[in] i_thread normal core thread bitset (0b0000..0b1111) +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @param[out] o_ok true if the threads are stopped +/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded +//-------------------------------------------------------------------------- +static inline fapi2::ReturnCode threads_stopped( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, + fapi2::buffer<uint64_t>& o_rasStatusReg, + bool& o_ok) +{ + // Running is defined as not in maint mode and not quiesced. + uint64_t l_state = 0; + FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state), + "threads_stopped(): p9_thread_control_query() returns an error."); + o_ok = (l_state & THREAD_STATE_STOP); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief all_threads_step_done : static funtion to encapsulate the step +/// complete state +/// @param[in] i_target core target +/// @param[in] i_thread normal core thread bitset (0b0000..0b1111) +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @param[out] o_ok true if the threads are done stepping +/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded +//-------------------------------------------------------------------------- +static inline fapi2::ReturnCode threads_step_done( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, + fapi2::buffer<uint64_t>& o_rasStatusReg, + bool& o_ok) +{ + uint64_t l_state = 0; + FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state), + "threads_step_done(): p9_thread_control_query() returns an error."); + o_ok = (l_state & THREAD_STATE_ISTEP_SUCCESS); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief threads_step_ready : static funtion to encapsulate the step +/// ready state +/// @param[in] i_target core target +/// @param[in] i_thread normal core thread bitset (0b0000..0b1111) +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @param[out] o_ok true if the threads are ready to step +/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded +//-------------------------------------------------------------------------- +static inline fapi2::ReturnCode threads_step_ready( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, + fapi2::buffer<uint64_t>& o_rasStatusReg, + bool& o_ok) +{ + uint64_t l_state = 0; + FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state), + "threads_step_ready(): p9_thread_control_query() returns an error."); + o_ok = (l_state & THREAD_STATE_ISTEP_READY); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control: utility subroutine to control thread state +//-------------------------------------------------------------------------- +fapi2::ReturnCode p9_thread_control( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const ThreadCommands i_command, + const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg, + uint64_t& o_state) +{ + FAPI_INF("p9_thread_control : Core threads: 0x%x, Command %u", i_threads, i_command); + + // Output state is only valid for PTC_CMD_QUERY command + o_state = 0; + + switch(i_command) + { + case PTC_CMD_SRESET: + FAPI_TRY(p9_thread_control_sreset(i_target, i_threads, i_warncheck, + o_rasStatusReg)); + break; + + case PTC_CMD_START: + FAPI_TRY(p9_thread_control_start(i_target, i_threads, i_warncheck, + o_rasStatusReg)); + break; + + case PTC_CMD_STOP: + FAPI_TRY(p9_thread_control_stop(i_target, i_threads, i_warncheck, + o_rasStatusReg)); + break; + + case PTC_CMD_STEP: + FAPI_TRY(p9_thread_control_step(i_target, i_threads, i_warncheck, + o_rasStatusReg)); + break; + + case PTC_CMD_QUERY: + FAPI_TRY(p9_thread_control_query(i_target, i_threads, + o_rasStatusReg, o_state)); + break; + }; + +fapi_try_exit: + FAPI_INF("p9_thread_control : Exit (core)"); + + return fapi2::current_err; + +} + +//-------------------------------------------------------------------------- +/// @brief Utility subroutine to query the state of a thread(s). +/// +/// @param[in] i_target Reference to core target +/// @param[in] i_threads Desired thread bits set +/// 0b0000 No thread (No-op) +/// 0b1000 Thread 0 +/// 0b0100 Thread 1 +/// 0b0010 Thread 2 +/// 0b0001 Thread 3 +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// Only valid for PTC_CMD_QUERY command. +/// @param[out] o_state Current thread state. See THREAD_STATE bit +/// definitions in header file. +/// +/// @return FAPI2_RC_SUCCESS if operation was successful, else error. +//-------------------------------------------------------------------------- +fapi2::ReturnCode p9_thread_control_query( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, + fapi2::buffer<uint64_t>& o_rasStatusReg, + uint64_t& o_state) +{ + FAPI_DBG("Entering: Thread bit set %u", i_threads); + + // Initializing + o_state = 0; + + // Setup mask values + const uint64_t l_running_mask = + (g_control_reg_map[i_threads] >> CORE_MAINT_MODE) | + (g_control_reg_map[i_threads] >> THREAD_QUIESCED); + const uint64_t l_step_ready_mask = + (g_control_reg_map[i_threads] >> CORE_MAINT_MODE) | + (g_control_reg_map[i_threads] >> THREAD_QUIESCED) | + (g_control_reg_map[i_threads] >> ICT_EMPTY); + + // Get C_RAS_STATUS reg + FAPI_TRY(fapi2::getScom(i_target, C_RAS_STATUS, o_rasStatusReg), + "p9_thread_control_query(): getScom() returns an error, " + "Addr C_RAS_STATUS 0x%.16llX", C_RAS_STATUS); + + // Note: all threads must meet a given condition in order for the + // bit to be set. + // Set THREAD_STATE_RUNNING + // Running is defined as not in maint mode and not quiesced. + if ( ((o_rasStatusReg & l_running_mask) == 0) ) + { + o_state |= THREAD_STATE_RUNNING; + } + // Stop is defined as in maint mode and in quiesced. + else if ( ((o_rasStatusReg & l_running_mask) == l_running_mask) ) + { + o_state |= THREAD_STATE_STOP; + } + + // Check for THREAD_STATE_MAINT + if ( o_rasStatusReg & + g_control_reg_map[i_threads] >> CORE_MAINT_MODE ) + { + o_state |= THREAD_STATE_MAINT; + } + + // Check for THREAD_STATE_QUIESCED + if ( o_rasStatusReg & + g_control_reg_map[i_threads] >> THREAD_QUIESCED ) + { + o_state |= THREAD_STATE_QUIESCED; + } + + // Check for THREAD_STATE_ICT_EMPTY + if ( o_rasStatusReg & + g_control_reg_map[i_threads] >> ICT_EMPTY ) + { + o_state |= THREAD_STATE_ICT_EMPTY; + } + + // Check for THREAD_STATE_LSU_QUIESCED + if ( o_rasStatusReg & + g_control_reg_map[i_threads] >> LSU_QUIESCED ) + { + o_state |= THREAD_STATE_LSU_QUIESCED; + } + + // Check for THREAD_STATE_ISTEP_SUCCESS + if ( o_rasStatusReg & + g_control_reg_map[i_threads] >> STEP_SUCCESS ) + { + o_state |= THREAD_STATE_ISTEP_SUCCESS; + } + + // Check for THREAD_STATE_ISTEP_READY + // All maint, quiesced and ICT empty must be set. + if ( ((o_rasStatusReg & l_step_ready_mask) == l_step_ready_mask) ) + { + o_state |= THREAD_STATE_ISTEP_READY; + } + + FAPI_DBG("C_RAS_STATUS: 0x%.16llX, Thread state 0x%.16llX", + o_rasStatusReg, o_state); + +fapi_try_exit: + FAPI_DBG("Exiting"); + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control: utility subroutine to control thread state +//------------------------------------------------------------------------- +fapi2::ReturnCode p9_thread_control( + const fapi2::Target<TARGET_TYPE_EX>& i_target, + const uint8_t i_threads, + const ThreadCommands i_command, + fapi2::buffer<uint64_t>& o_rasStatusReg, + const bool i_warncheck) +{ + uint64_t l_state = 0; + FAPI_INF("p9_thread_control : Start (ex) threads: 0x%x)", i_threads); + + // Grab the normal core children and iterate over them. + // TODO: Assumes core 0 is l_cores[0] + auto l_cores = i_target.getChildren<TARGET_TYPE_CORE>(); + uint8_t l_ordinal = 0; + + for( auto coreItr = l_cores.begin(); coreItr != l_cores.end(); ++coreItr, ++l_ordinal ) + { + // It is quite possible that this fused core bitset only has thread-bits set + // for one core or the other. Don't bother to call the control function if + // we don't have any threads to control. + const uint8_t l_thread_set = fapi2::thread_bitset_f2n(l_ordinal, i_threads); + + if (l_thread_set != 0) + { + FAPI_TRY(p9_thread_control(*coreItr, l_thread_set, i_command, + i_warncheck, o_rasStatusReg, l_state)); + } + } + +fapi_try_exit: + FAPI_INF("p9_thread_control : Exit (ex)"); + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control_sreset: utility subroutine to sreset a thread +/// @param[in] i_target core target +/// @param[in] i_threads normal core thread bitset (0b0000..0b1111) +/// @param[in] i_warncheck convert pre/post checks errors to warnings +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @return FAPI2_RC_SUCCESS if operation was successful, +/// RC_P9_THREAD_CONTROL_SRESET_FAIL if the threads aren't running, +/// else error +//-------------------------------------------------------------------------- +fapi2::ReturnCode p9_thread_control_sreset( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg) +{ + FAPI_DBG("p9_thread_control_sreset : Initiating sreset command to core PC logic for threads 0x%x", + i_threads); + // No Precondition for Sreset; power management is handled by platform + // Setup & Initiate SReset Command + { + fapi2::buffer<uint64_t> l_scom_data( + g_control_reg_map[i_threads] >> SRESET_REQUEST); + + FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_scom_data), + "p9_thread_control_sreset: putScom error when issuing sp_sreset for threads 0x%x", + i_threads); + } + + // Post-conditions check + // TODO: Check for instructions having been executed? + { + bool l_running = false; + FAPI_TRY(threads_running(i_target, i_threads, o_rasStatusReg, l_running), + "p9_thread_control_sreset: unable to determine if threads are running. threads: 0x%x", + i_threads); + + PTC_ASSERT_WARN(l_running == true, + i_warncheck, + fapi2::P9_THREAD_CONTROL_SRESET_FAIL() + .set_CORE_TARGET(i_target) + .set_THREAD(i_threads), + "p9_thread_control_sreset: ERROR: Thread SRESET issued, but the threads aren't running. " + "SReset might have failed for threads 0x%x", i_threads); + } + + FAPI_INF("p9_thread_control_sreset : sreset command issued for threads 0x%x", + i_threads); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control_start: utility subroutine to start a thread +/// @param[in] i_target core target +/// @param[in] i_threads normal core thread bitset (0b0000..0b1111) +/// @param[in] i_warncheck convert pre/post checks errors to warnings +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @return FAPI2_RC_SUCCESS if operation was successful, +/// RC_P9_THREAD_CONTROL_START_FAIL if start command failed, +/// else error +//-------------------------------------------------------------------------- +fapi2::ReturnCode p9_thread_control_start( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg) +{ + FAPI_DBG("p9_thread_control_start : Initiating start command to core PC logic for threads 0x%x", + i_threads); + + // Preconditions: Only valid when in maint mode + { + bool l_in_maint = false; + FAPI_TRY(threads_in_maint(i_target, i_threads, o_rasStatusReg, l_in_maint), + "p9_thread_control_start: unable to determine if threads are in maint mode. threads: 0x%x", + i_threads); + + PTC_ASSERT_WARN(l_in_maint == true, + i_warncheck, + fapi2::P9_THREAD_CONTROL_START_PRE_NOMAINT() + .set_CORE_TARGET(i_target) + .set_THREAD(i_threads), + "p9_thread_control_start: ERROR: Cannot issue Thread Start because the threads aren't in maint mode (threads=%x).", + i_threads); + } + + // Start the threads + { + fapi2::buffer<uint64_t> l_scom_data(g_control_reg_map[i_threads] >> CORE_START); + + FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_scom_data), + "p9_thread_control_start: putScom error when issuing sp_start for threads 0x%x", + i_threads); + } + + // Post-conditions check + // TODO: Perhaps only run this section if i_warncheck==true to save an extranious scom + // Verify understanding and desire for this funtionality before implementing in all thread_control functions + { + bool l_running = false; + FAPI_TRY(threads_running(i_target, i_threads, o_rasStatusReg, l_running), + "p9_thread_control_start: unable to determine if threads are running. threads: 0x%x", + i_threads); + + PTC_ASSERT_WARN(l_running == true, + i_warncheck, + fapi2::P9_THREAD_CONTROL_START_FAIL() + .set_CORE_TARGET(i_target) + .set_THREAD(i_threads), + "p9_thread_control_start: ERROR: Thread Start issued, but the threads aren't running. " + "Start might have failed for threads 0x%x", i_threads); + } + + FAPI_INF("p9_thread_control_start : start command issued for threads 0x%x", + i_threads); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control_stop: utility subroutine to stop a thread +/// @param[in] i_target core target +/// @param[in] i_threads normal core thread bitset (0b0000..0b1111) +/// @param[in] i_warncheck convert pre/post checks errors to warnings +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @return FAPI2_RC_SUCCESS if operation was successful, +/// RC_P9_THREAD_CONTROL_STOP_FAIL if start command failed, +/// else error +//-------------------------------------------------------------------------- +fapi2::ReturnCode p9_thread_control_stop( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg) +{ + FAPI_DBG("p9_thread_control_stop : Initiating stop command to core PC logic for threads 0x%x", + i_threads); + + // Pre-condition for stopping is that the threads are running (see figure 5.3 in the workbook) + // How to reconcile with 5.5.1 which says "invalid in maint mode?" Is that just a sub-precondition? + // TODO: Do we want to check to see if all threads are stopped and just bypass this if they are? + { + bool l_running = false; + FAPI_TRY(threads_running(i_target, i_threads, o_rasStatusReg, l_running), + "p9_thread_control_stop: unable to determine if threads are running. threads: 0x%x", + i_threads); + + PTC_ASSERT_WARN(l_running == true, + i_warncheck, + fapi2::P9_THREAD_CONTROL_STOP_PRE_NOTRUNNING() + .set_CORE_TARGET(i_target) + .set_THREAD(i_threads), + "p9_thread_control_stop: ERROR: Threads cannot be stopped because they aren't running (threads=%x).", i_threads); + } + + // Stop the threads + { + fapi2::buffer<uint64_t> l_scom_data(g_control_reg_map[i_threads] >> CORE_STOP); + + FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_scom_data), + "p9_thread_control_stop: putScom error when issuing sp_stop for threads 0x%x", + i_threads); + } + + // Post-conditions check + { + bool l_stopped = false; + FAPI_TRY(threads_stopped(i_target, i_threads, o_rasStatusReg, l_stopped), + "p9_thread_control_stop: unable to determine if threads are stopped. threads: 0x%x", + i_threads); + + PTC_ASSERT_WARN(l_stopped == true, + i_warncheck, + fapi2::P9_THREAD_CONTROL_STOP_FAIL() + .set_CORE_TARGET(i_target) + .set_THREAD(i_threads), + "p9_thread_control_stop: ERROR: Thread Stop issued, but the threads are running. " + "Stop might have failed for threads 0x%x", i_threads); + } + + FAPI_INF("p9_thread_control_stop : stop command issued for threads 0x%x", + i_threads); + +fapi_try_exit: + return fapi2::current_err; +} + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control_step: utility subroutine to single-instruction +/// step a thread +/// @param[in] i_target core target +/// @param[in] i_threads normal core thread bitset (0b0000..0b1111) +/// @param[in] i_warncheck convert pre/post checks errors to warnings +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer. +/// @return FAPI2_RC_SUCCESS if operation was successful, +/// RC_P9_THREAD_CONTROL_STEP_FAIL if start command failed, +/// else error +//-------------------------------------------------------------------------- +fapi2::ReturnCode p9_thread_control_step( + const fapi2::Target<TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg) +{ + FAPI_DBG("p9_thread_control_stop : Initiating step command to core PC logic for threads 0x%x", + i_threads); + + // Preconditions + { + bool l_step_ready = false; + FAPI_TRY(threads_step_ready(i_target, i_threads, o_rasStatusReg, l_step_ready), + "p9_thread_control_step: unable to determine if threads are ready to step. threads: 0x%x", + i_threads); + + PTC_ASSERT_WARN(l_step_ready == true, + i_warncheck, + fapi2::P9_THREAD_CONTROL_STEP_PRE_NOTSTOPPING() + .set_CORE_TARGET(i_target) + .set_THREAD(i_threads), + "p9_thread_control_step: ERROR: Thread cannot be stepped because they are not ready to step (threads=%x).", i_threads); + } + + + // Setup single step mode and issue step. + { + fapi2::buffer<uint64_t> l_mode_data; + fapi2::buffer<uint64_t> l_step_data(g_control_reg_map[i_threads] >> CORE_STEP); + + // Set single step mode. + FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data), + "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x", + i_threads); + + // i_threads is right aligned + l_mode_data |= + fapi2::buffer<uint64_t>().insertFromRight<RAS_MODE_STEP_SHIFT, 4>(i_threads); + FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data), + "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x", + i_threads); + + // Set issue the step + FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_step_data), + "p9_thread_control_step: putScom error when issuing step command for threads 0x%x", + i_threads); + } + + + // Poll for completion. + { + bool l_step_done = false; + uint8_t l_governor = PTC_STEP_COMP_POLL_LIMIT; + + do + { + FAPI_DBG("polling for step done. governor: %d", l_governor); + FAPI_TRY(threads_step_done(i_target, i_threads, o_rasStatusReg, l_step_done), + "p9_thread_control_step: thread step issued but something went wrong polling for step_done for threads 0x%x", + i_threads); + } + while((l_step_done != true) && l_governor--); + + // We ran out of tries. If the scom failed, fapi_try kicked us out long ago. + PTC_ASSERT_WARN(l_governor != 0, + i_warncheck, + fapi2::P9_THREAD_CONTROL_STEP_FAIL() + .set_CORE_TARGET(i_target) + .set_THREAD(i_threads) + .set_PTC_STEP_COMP_POLL_LIMIT(PTC_STEP_COMP_POLL_LIMIT), + "p9_thread_control_stop: ERROR: Thread Step failed. Complete bits aren't set after %d poll atempts. WARNING: C_RAS_STATUS " + "bit still in single instruction mode. Threads 0x%x", PTC_STEP_COMP_POLL_LIMIT, + i_threads); + } + + + // Reset single step mode + { + fapi2::buffer<uint64_t> l_mode_data; + + FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data), + "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x", + i_threads); + + // i_threads is right aligned + l_mode_data &= ~ + (fapi2::buffer<uint64_t>().insertFromRight<RAS_MODE_STEP_SHIFT, 4>(i_threads)); + FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data), + "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x", + i_threads); + } + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H new file mode 100755 index 00000000..14821a5c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H @@ -0,0 +1,183 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/core/p9_thread_control.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +// *! TITLE : p9_thread_control +// *! DESCRIPTION : Core Thread start/stop/step/query/activate operations +// *! Use to start (start or sreset) thread instruction execution, +// *! stop instruction execution, or single instruction step. +// *! Also used to query the state of a thread. +//------------------------------------------------------------------------------ + +// *HWP HWP Owner: Nick Klazynski <dyem@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Quad +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB:HS + +#ifndef _P9_THREAD_CONTROL_H_ +#define _P9_THREAD_CONTROL_H_ + +#include <fapi2.H> +#include <return_code.H> +#include <error_scope.H> + +#include "p9_quad_scom_addresses.H" + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Constants +//------------------------------------------------------------------------------ + const uint8_t MAX_NUM_OF_THREADS = 4; + +// THREAD_STATE bit definitions + const uint64_t THREAD_STATE_RUNNING = 0x8000000000000000ULL; + const uint64_t THREAD_STATE_STOP = 0x4000000000000000ULL; + const uint64_t THREAD_STATE_QUIESCED = 0x2000000000000000ULL; + const uint64_t THREAD_STATE_MAINT = 0x1000000000000000ULL; + const uint64_t THREAD_STATE_ICT_EMPTY = 0x0800000000000000ULL; + const uint64_t THREAD_STATE_LSU_QUIESCED = 0x0400000000000000ULL; + const uint64_t THREAD_STATE_ISTEP_SUCCESS = 0x0200000000000000ULL; + const uint64_t THREAD_STATE_ISTEP_READY = 0x0100000000000000ULL; + +// A macro to wrap the warning check boiler plate +// If the action failed and i_warncheck is set add a trace and continue anyway +#define PTC_ASSERT_WARN( __conditional__, __warning__, __ffdc__, ... ) \ + if (! (__conditional__)) \ + { \ + if (__warning__) \ + { \ + FAPI_INF(__VA_ARGS__); \ + } \ + else \ + { \ + (__ffdc__).execute(); \ + FAPI_ERR(__VA_ARGS__); \ + goto fapi_try_exit; \ + } \ + } \ + + +// ProcThreadControl input commands +// If you make this an enum, the compiler can +// check that a case statement has all the elements +// covered. + enum ThreadCommands + { + PTC_CMD_SRESET = 0, + PTC_CMD_STEP = 1, + PTC_CMD_START = 2, + PTC_CMD_STOP = 3, + PTC_CMD_QUERY = 4, + }; + + enum ThreadRasStatus + { + CORE_MAINT_MODE = 0, + THREAD_QUIESCED = 1, + ICT_EMPTY = 2, + LSU_QUIESCED = 3, + STEP_SUCCESS = 4, + }; + + enum PTC_Constants + { + RAS_MODE_STEP_SHIFT = 52, + PTC_STEP_COMP_POLL_LIMIT = 10, + }; + +// Bit positions in the DIRECT_CONTROL register + enum ThreadControl + { + CLEAR_MAINT = 3, + SRESET_REQUEST = 4, + CORE_STEP = 5, + CORE_START = 6, + CORE_STOP = 7, + }; + +/// @typedef p9_thread_control_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_thread_control_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&, + const uint8_t, const ThreadCommands, const bool, + fapi2::buffer<uint64_t>&, uint64_t&); + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control: utility subroutine to control thread state +/// @param[in] i_target ex target +/// @param[in] i_threads fused thread bitset (0b00000000..0b11111111) +/// @param[in] i_command one of +/// PTC_CMD_SRESET => initiate sreset thread command +/// PTC_CMD_START => initiate start thread command +/// PTC_CMD_STOP => initiate stop thread command +/// PTC_CMD_STEP => initiate step thread command +/// PTC_CMD_QUERY => query and return thread state +/// @param[in] i_warncheck convert pre/post checks errors to warnings +/// @return FAPI_RC_SUCCESS if operation was successful, +/// function-specific fail codes (see function definitions), +/// else error +//------------------------------------------------------------------------- +//fapi2::ReturnCode p9_thread_control(const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target, +// const uint8_t i_threads, const ThreadCommands i_command, +// const bool i_warncheck); + +//-------------------------------------------------------------------------- +/// @brief p9_thread_control: utility subroutine to control thread state +/// +/// @param[in] i_target core target +/// @param[in] i_threads Desired thread bit set, multiple thread settings +/// are allowed. +/// 0b0000 No thread (No-op) +/// 0b1000 Thread 0 +/// 0b0100 Thread 1 +/// 0b0010 Thread 2 +/// 0b0001 Thread 3 +/// @param[in] i_command one of +/// PTC_CMD_SRESET => initiate sreset thread command +/// PTC_CMD_START => initiate start thread command +/// PTC_CMD_STOP => initiate stop thread command +/// PTC_CMD_STEP => initiate step thread command +/// PTC_CMD_QUERY => query and return thread state +/// @param[in] i_warncheck convert pre/post checks errors to warnings +/// @param[out] o_rasStatusReg Complete RAS status reg 64-bit buffer after +/// executing command. +/// @param[out] o_state Thread state, only valid for PTC_CMD_QUERY command. +/// See p9_thread_control.H for THREAD_STATE bit definitions. +/// +/// @return FAPI_RC_SUCCESS if operation was successful, +/// function-specific fail codes (see function definitions), +/// else error +//-------------------------------------------------------------------------- + fapi2::ReturnCode p9_thread_control(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint8_t i_threads, const ThreadCommands i_command, + const bool i_warncheck, + fapi2::buffer<uint64_t>& o_rasStatusReg, + uint64_t& o_state); + +} // extern + +#endif // _P9_THREAD_CONTROL_H_ diff --git a/src/import/chips/p9/procedures/hwp/initfiles/Makefile b/src/import/chips/p9/procedures/hwp/initfiles/Makefile new file mode 100644 index 00000000..123518a1 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/initfiles/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the initfiles hardware procedure code. See the +# "initfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/initfiles +export SUB_OBJDIR = /initfiles + +include img_defs.mk +include initfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(INITFILES_OBJECTS)) + +libinitfiles.a: initfiles + $(AR) crs $(OBJDIR)/libinitfiles.a $(OBJDIR)/*.o + +.PHONY: clean initfiles +initfiles: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/initfiles/initfiles.mk b/src/import/chips/p9/procedures/hwp/initfiles/initfiles.mk new file mode 100644 index 00000000..9703f3e3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/initfiles.mk @@ -0,0 +1,43 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/initfiles/initfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file initfiles.mk +# +# @brief mk for including initfile object files +# +########################################################################## +# Object Files +########################################################################## + +INITFILES-CPP-SOURCES += p9_ncu_scom.C +INITFILES-CPP-SOURCES += p9_l2_scom.C +INITFILES-CPP-SOURCES += p9_l3_scom.C + +INITFILES-C-SOURCES += +INITFILES-S-SOURCES += + +INITFILES_OBJECTS += $(INITFILES-CPP-SOURCES:.C=.o) +INITFILES_OBJECTS += $(INITFILES-C-SOURCES:.c=.o) +INITFILES_OBJECTS += $(INITFILES-S-SOURCES:.S=.o) + diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C new file mode 100644 index 00000000..e85d8585 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C @@ -0,0 +1,294 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "p9_l2_scom.H" +#include <stdint.h> +#include <stddef.h> +#include <fapi2.H> + +using namespace fapi2; + +constexpr auto literal_0b0001 = 0b0001; +constexpr auto literal_0b0100 = 0b0100; +constexpr auto literal_0 = 0; +constexpr auto literal_0x001 = 0x001; +constexpr auto literal_0b0000 = 0b0000; + +fapi2::ReturnCode p9_l2_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1) +{ + fapi2::ReturnCode l_rc = 0; + + do + { + fapi2::buffer<uint64_t> l_scom_buffer; + fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE_Type l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)"); + break; + } + + fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_TGT1_ATTR_SYSTEM_IPL_PHASE; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, TGT1, l_TGT1_ATTR_SYSTEM_IPL_PHASE); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)"); + break; + } + + { + l_rc = fapi2::getScom( TGT0, 0x1001080aull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x1001080aull)"); + break; + } + + { + if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_SMALL_SYSTEM)) + { + constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_ON = 0x1; + l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_ON, 23, 1, 63 ); + } + else if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM)) + { + constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_OFF = 0x0; + l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_OFF, 23, 1, 63 ); + } + } + + { + if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME)) + { + constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_HASH_L3_ADDR_EN_ON = 0x1; + l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_HASH_L3_ADDR_EN_ON, 21, 1, 63 ); + } + } + + { + if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME)) + { + constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_CAC_ERR_REPAIR_EN_ON = 0x1; + l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_CAC_ERR_REPAIR_EN_ON, 15, 1, 63 ); + } + } + + l_rc = fapi2::putScom(TGT0, 0x1001080aull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x1001080aull)"); + break; + } + } + + { + l_rc = fapi2::getScom( TGT0, 0x1001080bull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x1001080bull)"); + break; + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0001, 4, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0100, 8, 4, 60 ); + } + + l_rc = fapi2::putScom(TGT0, 0x1001080bull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x1001080bull)"); + break; + } + } + + fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T0)"); + break; + } + + fapi2::ATTR_PROC_EPS_READ_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T1)"); + break; + } + + fapi2::ATTR_PROC_EPS_READ_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T2)"); + break; + } + + { + l_rc = fapi2::getScom( TGT0, 0x10010810ull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x10010810ull)"); + break; + } + + { + if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0, 0, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 ); + } + } + + { + if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1, 12, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 ); + } + } + + { + if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2, 24, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 24, 12, 52 ); + } + } + + l_rc = fapi2::putScom(TGT0, 0x10010810ull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x10010810ull)"); + break; + } + } + + fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T1)"); + break; + } + + fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T2)"); + break; + } + + { + l_rc = fapi2::getScom( TGT0, 0x10010811ull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x10010811ull)"); + break; + } + + { + if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1, 0, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 ); + } + } + + { + if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2, 12, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 ); + } + } + + { + constexpr auto l_EXP_L2_L2MISC_L2CERRS_EPS_CNT_USE_L2_DIVIDER_EN_OFF = 0x0; + l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_EPS_CNT_USE_L2_DIVIDER_EN_OFF, 29, 1, 63 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0000, 30, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0001, 24, 4, 60 ); + } + + { + constexpr auto l_EXP_L2_L2MISC_L2CERRS_EPS_MODE_SEL_MODE1 = 0x0; + l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_EPS_MODE_SEL_MODE1, 28, 1, 63 ); + } + + l_rc = fapi2::putScom(TGT0, 0x10010811ull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x10010811ull)"); + break; + } + } + } + while (0); + + return l_rc; +} diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H new file mode 100644 index 00000000..69653c03 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H @@ -0,0 +1,45 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef _INIT_P9_L2_SCOM_PROCEDURE_H_ +#define _INIT_P9_L2_SCOM_PROCEDURE_H_ + + +#include <stddef.h> +#include <stdint.h> +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_l2_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_EX>&, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&); + +extern "C" +{ + + fapi2::ReturnCode p9_l2_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1); + +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C new file mode 100644 index 00000000..1186e9d2 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C @@ -0,0 +1,279 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "p9_l3_scom.H" +#include <stdint.h> +#include <stddef.h> +#include <fapi2.H> + +using namespace fapi2; + +constexpr auto literal_0 = 0; +constexpr auto literal_0x001 = 0x001; +constexpr auto literal_0b0 = 0b0; +constexpr auto literal_0b0000 = 0b0000; +constexpr auto literal_0b0001 = 0b0001; +constexpr auto literal_0b0100 = 0b0100; + +fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1) +{ + fapi2::ReturnCode l_rc = 0; + + do + { + fapi2::buffer<uint64_t> l_scom_buffer; + fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T0)"); + break; + } + + fapi2::ATTR_PROC_EPS_READ_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T1)"); + break; + } + + fapi2::ATTR_PROC_EPS_READ_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T2)"); + break; + } + + { + l_rc = fapi2::getScom( TGT0, 0x10011829ull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x10011829ull)"); + break; + } + + { + if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0, 0, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 ); + } + } + + { + if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1, 12, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 ); + } + } + + { + if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2, 24, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 24, 12, 52 ); + } + } + + l_rc = fapi2::putScom(TGT0, 0x10011829ull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x10011829ull)"); + break; + } + } + + fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T1)"); + break; + } + + fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T2)"); + break; + } + + { + l_rc = fapi2::getScom( TGT0, 0x1001182aull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x1001182aull)"); + break; + } + + { + if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1, 0, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 ); + } + } + + { + if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 != literal_0)) + { + l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2, 12, 12, 52 ); + } + else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 == literal_0)) + { + l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 ); + } + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0, 34, 1, 63 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0000, 26, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0001, 30, 4, 60 ); + } + + l_rc = fapi2::putScom(TGT0, 0x1001182aull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x1001182aull)"); + break; + } + } + + fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE_Type l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)"); + break; + } + + fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_TGT1_ATTR_SYSTEM_IPL_PHASE; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, TGT1, l_TGT1_ATTR_SYSTEM_IPL_PHASE); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)"); + break; + } + + { + l_rc = fapi2::getScom( TGT0, 0x1001182bull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x1001182bull)"); + break; + } + + { + if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_SMALL_SYSTEM)) + { + constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_ON = 0x1; + l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_ON, 22, 1, 63 ); + } + else if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM)) + { + constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_OFF = 0x0; + l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_OFF, 22, 1, 63 ); + } + } + + { + if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME)) + { + constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_ADDR_HASH_EN_CFG_ON = 0x1; + l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_ADDR_HASH_EN_CFG_ON, 11, 1, 63 ); + } + } + + { + if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME)) + { + constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_RDSN_LINEDEL_UE_EN_ON = 0x1; + l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_RDSN_LINEDEL_UE_EN_ON, 2, 1, 63 ); + } + } + + { + if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME)) + { + constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_DMAP_CI_EN_CFG_OFF = 0x0; + l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_DMAP_CI_EN_CFG_OFF, 1, 1, 63 ); + } + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0001, 14, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0100, 18, 4, 60 ); + } + + l_rc = fapi2::putScom(TGT0, 0x1001182bull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x1001182bull)"); + break; + } + } + } + while (0); + + return l_rc; +} diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H new file mode 100644 index 00000000..8f8edb08 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H @@ -0,0 +1,45 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef _INIT_P9_L3_SCOM_PROCEDURE_H_ +#define _INIT_P9_L3_SCOM_PROCEDURE_H_ + + +#include <stddef.h> +#include <stdint.h> +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_l3_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_EX>&, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&); + +extern "C" +{ + + fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1); + +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C new file mode 100644 index 00000000..950a088d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "p9_ncu_scom.H" +#include <stdint.h> +#include <stddef.h> +#include <fapi2.H> + +using namespace fapi2; + +constexpr auto literal_0b0001 = 0b0001; +constexpr auto literal_0b0100 = 0b0100; +constexpr auto literal_0x8 = 0x8; +constexpr auto literal_0x10 = 0x10; + +fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1) +{ + fapi2::ReturnCode l_rc = 0; + + do + { + fapi2::buffer<uint64_t> l_scom_buffer; + fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE_Type l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE; + l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE); + + if (l_rc) + { + FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)"); + break; + } + + { + l_rc = fapi2::getScom( TGT0, 0x1001100aull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x1001100aull)"); + break; + } + + { + if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_SMALL_SYSTEM)) + { + constexpr auto l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_ON = 0x1; + l_scom_buffer.insert<uint64_t> (l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_ON, 9, 1, 63 ); + } + else if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM)) + { + constexpr auto l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_OFF = 0x0; + l_scom_buffer.insert<uint64_t> (l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_OFF, 9, 1, 63 ); + } + } + + l_rc = fapi2::putScom(TGT0, 0x1001100aull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x1001100aull)"); + break; + } + } + + { + l_rc = fapi2::getScom( TGT0, 0x1001100bull, l_scom_buffer ); + + if (l_rc) + { + FAPI_ERR("ERROR executing: getScom (0x1001100bull)"); + break; + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0001, 0, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0b0100, 4, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0x8, 8, 10, 54 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0x10, 26, 10, 54 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0x8, 18, 4, 60 ); + } + + { + l_scom_buffer.insert<uint64_t> (literal_0x8, 22, 4, 60 ); + } + + l_rc = fapi2::putScom(TGT0, 0x1001100bull, l_scom_buffer); + + if (l_rc) + { + FAPI_ERR("ERROR executing: putScom (0x1001100bull)"); + break; + } + } + } + while (0); + + return l_rc; +} diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H new file mode 100644 index 00000000..bc56a154 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H @@ -0,0 +1,45 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef _INIT_P9_NCU_SCOM_PROCEDURE_H_ +#define _INIT_P9_NCU_SCOM_PROCEDURE_H_ + + +#include <stddef.h> +#include <stdint.h> +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_ncu_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_EX>&, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&); + +extern "C" +{ + + fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1); + +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/lib/Makefile b/src/import/chips/p9/procedures/hwp/lib/Makefile new file mode 100644 index 00000000..059fb2f3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/lib/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the common library hardware procedure code. +# See the "libcommonfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/lib +export SUB_OBJDIR = /lib + +include img_defs.mk +include libcommonfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(LIB_OBJECTS)) + +libcommon.a: lib + $(AR) crs $(OBJDIR)/libcommon.a $(OBJDIR)/*.o + +.PHONY: clean lib +lib: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/lib/libcommonfiles.mk b/src/import/chips/p9/procedures/hwp/lib/libcommonfiles.mk new file mode 100644 index 00000000..cbcd12ee --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/libcommonfiles.mk @@ -0,0 +1,42 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/lib/libcommonfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file libcommonfiles.mk +# +# @brief mk for including library common object files +# +########################################################################## +# Object Files +########################################################################## + +LIB-CPP-SOURCES += p9_common_poweronoff.C +LIB-CPP-SOURCES += p9_common_pro_epi_log.C + +LIB-C-SOURCES += +LIB-S-SOURCES += + +LIB_OBJECTS += $(LIB-CPP-SOURCES:.C=.o) +LIB_OBJECTS += $(LIB-C-SOURCES:.c=.o) +LIB_OBJECTS += $(LIB-S-SOURCES:.S=.o) + diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C new file mode 100644 index 00000000..52916b7f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C @@ -0,0 +1,527 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_poweronoff.C +/// @brief common procedure for power on/off +/// +/// Procedure Summary: +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE:CME +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_quad_scom_addresses.H> +#include "p9_hcd_common.H" +#include "p9_common_poweronoff.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ +// Define only address offset to be compatible with both core and cache domain + +const uint64_t NET_CTRL0_WOR[2] = { C_NET_CTRL0_WOR, + EQ_NET_CTRL0_WOR + }; + +const uint64_t PPM_PFCS[2] = { C_PPM_PFCS_SCOM, + EQ_PPM_PFCS_SCOM + }; + +const uint64_t PPM_PFCS_CLR[2] = { C_PPM_PFCS_SCOM1, + EQ_PPM_PFCS_SCOM1 + }; + +const uint64_t PPM_PFCS_OR[2] = { C_PPM_PFCS_SCOM2, + EQ_PPM_PFCS_SCOM2 + }; + +const uint64_t PPM_PFDLY[2] = { C_PPM_PFDLY, + EQ_PPM_PFDLY + }; + +const uint64_t PPM_PFSNS[2] = { C_PPM_PFSNS, + EQ_PPM_PFSNS + }; + +enum { FSM_IDLE_POLLING_HW_NS_DELAY = 10000, + FSM_IDLE_POLLING_SIM_CYCLE_DELAY = 80000, + PFET_STATE_LENGTH = 2, + VXX_PG_SEL_LEN = 4 + }; + +enum pfetRegField { PFET_NOP = 0, + PFET_FORCE_VOFF = 1, + PFET_NOP_RESERVERD = 2, + PFET_FORCE_VON = 3 + }; + +enum pgStateOffset { PG_STATE_IDLE_OFFSET = 0, + PG_STATE_INC_OFFSET = 1, + PG_STATE_DEC_OFFSET = 2, + PG_STATE_WAIT_OFFSET = 3 + }; + + +enum PFCS_Bits { VDD_PFET_FORCE_STATE_BIT = 0, + VCS_PFET_FORCE_STATE_BIT = 2, + VDD_PFET_VAL_OVERRIDE_BIT = 4, + VDD_PFET_SEL_OVERRIDE_BIT = 5, + VCS_PFET_VAL_OVERRIDE_BIT = 6, + VCS_PFET_SEL_OVERRIDE_BIT = 7, + VDD_PFET_REGULATION_FINGER_EN_BIT = 8, + VDD_PFET_REGULATION_FINGER_VALUE_BIT = 9, + RESERVED1_BIT = 10, + VDD_PFET_ENABLE_VALUE_BIT = 12, + VDD_PFET_SEL_VALUE_BIT = 20, + VCS_PFET_ENABLE_VALUE_BIT = 24, + VCS_PFET_SEL_VALUE_BIT = 32, + RESERVED2_BIT = 36, + VDD_PG_STATE_BIT = 42, + VDD_PG_SEL_BIT = 46, + VCS_PG_STATE_BIT = 50, + VCS_PG_SEL_BIT = 54, + RESERVED3_BIT = 58 + }; + + +enum { VDD_PFETS_ENABLED_SENSE_BIT = 0, + VDD_PFETS_DISABLED_SENSE_BIT = 1, + VCS_PFETS_ENABLED_SENSE_BIT = 2, + VCS_PFETS_DISABLED_SENSE_BIT = 3 + }; + +enum { POWDN_DLY_BIT = 0, + POWUP_DLY_BIT = 4, + TP_VDD_PFET_ENABLE_ACTUAL_BIT = 16, + TP_VCS_PFET_ENABLE_ACTUAL_BIT = 24 + }; + +enum { POWDN_DLY_LENGTH = 4, + POWUP_DLY_LENGTH = 4, + TP_VDD_PFET_ENABLE_ACTUAL_LENGTH = 8, + TP_VCS_PFET_ENABLE_ACTUAL_LENGTH = 8 + }; + +// i_operation defines + + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ +template <fapi2::TargetType K> +fapi2::ReturnCode +p9_common_poweronoff( + const fapi2::Target<K>& i_target, + const p9power::powerOperation_t i_operation) +{ + uint32_t l_loopsPerMs; + + FAPI_INF(">>p9_common_poweronoff: %d", i_operation); + uint32_t l_type = 0; // Assumes core + + if((i_target.getType() & fapi2::TARGET_TYPE_EQ)) + { + l_type = 1; + } + + fapi2::buffer<uint64_t> l_data; + fapi2::buffer<uint64_t> l_temp; // extractToRight seems the require space to write into. + /////////////////////////////////////////////////////////////////////////// + // lambda functions for poweronoff procedure + /////////////////////////////////////////////////////////////////////////// + auto pollVddFSMIdle = [&] () + { + // Poll for PFETCNTLSTAT_REG[VDD_PG_STATE] for 0b1000 (FSM idle) + // – Timeout value = 1ms + FAPI_DBG("Polling for power gate sequencer state: FSM idle"); + l_loopsPerMs = 1E6 / FSM_IDLE_POLLING_HW_NS_DELAY; + + // Note that the Lamda assumes that l_data already contains the + do + { + fapi2::delay(FSM_IDLE_POLLING_HW_NS_DELAY, + FSM_IDLE_POLLING_SIM_CYCLE_DELAY); + + FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data), + "getScom failed for address PPM_PFCS"); // poll + FAPI_DBG("timeout l_loopsPerMs. %x", l_loopsPerMs); + } + while ((l_data.getBit < VDD_PG_STATE_BIT + PG_STATE_IDLE_OFFSET > () + == 0 ) && (--l_loopsPerMs != 0)); + + /* + do + { + FAPI_TRY(fapi2::getScom(i_target, PPM_PFSNS[l_type], l_data), + "getScom failed for address PPM_PFSNS"); // poll + } + while ((l_data.getBit<0>() == 0 ) && (--l_loopsPerMs != 0)); + */ + FAPI_ASSERT((l_loopsPerMs != 0), + fapi2::PMPROC_PFETLIB_TIMEOUT() + .set_ADDRESS(PPM_PFCS[l_type]), + "VDD FSM idle timeout"); + + /// (Optional) Check PFETCNTLSTAT_REG[VDD_PG_SEL]being 0x8 + // (Off encode point) +#if 0 // this field does not get set yet + l_data.extractToRight<VDD_PG_SEL_BIT, VXX_PG_SEL_LEN>(l_temp); + FAPI_ASSERT((l_temp == 8), + fapi2::PROCPM_PFET_CODE_BAD_MODE(), + "VDD_PG_SEL != 8: l_temp %0x", l_temp); + +#endif + fapi_try_exit: + return fapi2::current_err; + }; + + auto pollVcsFSMIdle = [&] () + { + // Poll for PFETCNTLSTAT_REG[VCS_PG_STATE] for 0b1000 (FSM idle) + // – Timeout value = 1ms + FAPI_DBG("Polling for power gate sequencer state: FSM idle"); + l_loopsPerMs = 1E6 / FSM_IDLE_POLLING_HW_NS_DELAY; + + do + { + fapi2::delay(FSM_IDLE_POLLING_HW_NS_DELAY, + FSM_IDLE_POLLING_SIM_CYCLE_DELAY); + + FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data), + "getScom failed for address PPM_PFCS"); // poll + //FAPI_DBG("timeout l_loopsPerMs. %x", l_loopsPerMs); + } + while ((l_data.getBit < VCS_PG_STATE_BIT + PG_STATE_IDLE_OFFSET > () + == 0 ) && (--l_loopsPerMs != 0)); + + /* + do + { + FAPI_TRY(fapi2::getScom(i_target, PPM_PFSNS[l_type], l_data), + "getScom failed for address PPM_PFSNS"); // poll + } + while ((l_data.getBit<2>() == 0 ) && (--l_loopsPerMs != 0)); + */ + FAPI_ASSERT((l_loopsPerMs != 0), + fapi2::PMPROC_PFETLIB_TIMEOUT() + .set_ADDRESS(PPM_PFCS[l_type]), + "VCS FSM idle timeout"); + + // (Optional) Check PFETCNTLSTAT_REG[VDD_PG_SEL] + // being 0x8 (Off encode point) + + +#if 0 // this field does not get set yet + l_data.extractToRight<VCS_PG_SEL_BIT, VXX_PG_SEL_LEN>(l_temp); + FAPI_ASSERT((l_temp == 8), + fapi2::PROCPM_PFET_CODE_BAD_MODE(), + "VCS_PG_SEL != 8: l_temp %0x", l_temp); + +#endif + fapi_try_exit: + return fapi2::current_err; + + }; + + + auto powerOnVdd = [&] () + { + // Command the cache PFET controller to power-on + // Write PFETCNTLSTAT_REG: + // vdd_pfet_force_state = 11 (Force Von) + // vdd_pfet_val_override = 0 (Override disabled) + // vdd_pfet_sel_override = 0 (Override disabled) + // vdd_pfet_enable_regulation_finger = 0 + // (Regulation finger controlled by FSM) + FAPI_DBG("Clear VDD PFET stage select and value override bits"); + l_data.flush<0>(). + setBit<VDD_PFET_VAL_OVERRIDE_BIT>(). + setBit<VDD_PFET_SEL_OVERRIDE_BIT>(). + setBit<VDD_PFET_REGULATION_FINGER_EN_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS"); + + FAPI_DBG("Force VDD on"); + l_data.flush<0>().insertFromRight + <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VON); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data), + "putScom failed for address PPM_PFCS_OR"); + + // Check for valid power on completion + // Polled Timeout: 100us + FAPI_TRY(pollVddFSMIdle()); + + // Write PFETCNTLSTAT_REG_WCLEAR + // vdd_pfet_force_state = 00 (No Operation); + // all fields set to 1 for WAND + // Use PPM_PFCS_CLR, + // vdd_pfet_force_state = 0b11 + FAPI_DBG("vdd_pfet_force_state = 00, or Idle"); + l_data.flush<0>().insertFromRight + <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS_CLR"); + + fapi_try_exit: + return fapi2::current_err; + + }; + + auto powerOnVcs = [&] () + { + // Command the PFET controller to power-on + // Write PFETCNTLSTAT_REG_OR with values defined below + // vcs_pfet_force_state = 11 (Force Von) + // Write to PFETCNTLSTAT_REG_CLR + // vcs_pfet_val_override = 0 (Override disabled) + // vcs_pfet_sel_override = 0 (Override disabled) + // Note there is no vcs_pfet_enable_regulation_finger + FAPI_DBG("Clear VCS PFET stage select and value override bits"); + l_data.flush<0>(). + setBit<VCS_PFET_VAL_OVERRIDE_BIT>(). + setBit<VCS_PFET_SEL_OVERRIDE_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS_CLR"); + + FAPI_DBG("Force VCS on"); + l_data.flush<0>().insertFromRight + <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VON); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data), + "putScom failed for address PPM_PFCS_OR"); + + // Check for valid power on completion + // Polled Timeout: 100us + FAPI_TRY(pollVcsFSMIdle()); + + // Write PFETCNTLSTAT_REG_WCLEAR + // vcs_pfet_force_state = 00 (No Operation); + // all fields set to 1 for WAND + // Use PPM_PFCS_CLR, vdd_pfet_force_state = ~(0b00) + FAPI_DBG("vcs_pfet_force_state = 00, or Idle"); + l_data.flush<0>().insertFromRight + <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS_CLR"); + + fapi_try_exit: + return fapi2::current_err; + }; + + auto powerOffVdd = [&] () + { + // Command the PFET controller to power-off + // Write PFETCNTLSTAT_REG: + // vdd_pfet_force_state = 01 (Force Voff) + // vdd_pfet_val_override = 0 (Override disabled) + // vdd_pfet_sel_override = 0 (Override disabled) + // vdd_pfet_enable_regulation_finger = 0 + // (Regulation finger controlled by FSM) + FAPI_DBG("Clear VDD PFET stage select and value override bits"); + l_data.flush<0>(). + setBit<VDD_PFET_VAL_OVERRIDE_BIT>(). + setBit<VDD_PFET_SEL_OVERRIDE_BIT>(). + setBit<VDD_PFET_REGULATION_FINGER_EN_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS"); + + FAPI_DBG("Force VDD off"); + l_data.flush<0>().insertFromRight + <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VOFF); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data), + "putScom failed for address PPM_PFCS"); + + // Check for valid power off completion + // Polled Timeout: 100us + FAPI_TRY(pollVddFSMIdle()); + + // Write PFETCNTLSTAT_REG_WCLEAR + // vdd_pfet_force_state = 00 (No Operation); + // all fields set to 1 for WAND + // Use PPM_PFCS_CLR, vdd_pfet_force_state = 0b11 + FAPI_DBG("vdd_pfet_force_state = 00, or Idle"); + l_data.flush<0>().insertFromRight + <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS_CLR"); + + fapi_try_exit: + return fapi2::current_err; + }; + + auto powerOffVcs = [&] () + { + // Command the PFET controller to power-off + // Write PFETCNTLSTAT_REG_OR with values defined below + // vcs_pfet_force_state = 11 (Force Voff) + // DOC BUG: ?? Write to PFETCNTLSTAT_REG_CLR + // vcs_pfet_val_override = 0 (Override disabled) + // vcs_pfet_sel_override = 0 (Override disabled) + // Note there is no vcs_pfet_enable_regulation_finger + FAPI_DBG("Clear VCS PFET stage select and value override bits"); + l_data.flush<0>(). + setBit<VCS_PFET_VAL_OVERRIDE_BIT>(). + setBit<VCS_PFET_SEL_OVERRIDE_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS_CLR"); + + FAPI_DBG("Force VCS off"); + l_data.flush<0>(). + insertFromRight + <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VOFF); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data), + "putScom failed for address PPM_PFCS_OR"); + + // Check for valid power off completion + // Polled Timeout: 100us + FAPI_TRY(pollVcsFSMIdle()); + + // Write PFETCNTLSTAT_REG_WCLEAR + // vcs_pfet_force_state = 00 (No Operation); + // all fields set to 1 for WAND + // Use PPM_PFCS_CLR, vcs_pfet_force_state = ~(0b00) + FAPI_DBG("vcs_pfet_force_state = 00, or Idle"); + l_data.flush<0>().insertFromRight + <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS_CLR"); + + fapi_try_exit: + return fapi2::current_err; + }; + + /////////////////////////////////////////////////////////////////////////// + // Initialization code + /////////////////////////////////////////////////////////////////////////// +#if 0 // unneeded for AWAN operation. Also, fails if delay field is > 8 + l_data.flush<0>().insertFromRight<POWDN_DLY_BIT, POWDN_DLY_LENGTH>(0x8). + insertFromRight<POWUP_DLY_BIT, POWUP_DLY_LENGTH>(0x8); + + FAPI_TRY(fapi2::putScom(i_target, PPM_PFDLY, l_data), + "putScom failed for address PPM_PFDLY"); +#endif + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("Assert PCB fence via NET_CTRL0[25]"); + FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(25))); + + FAPI_DBG("Assert chiplet electrical fence via NET_CTRL0[26]"); + FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(26))); + + FAPI_DBG("Assert vital thold via NET_CTRL0[16]"); + FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(16))); + + /////////////////////////////////////////////////////////////////////////// + // Procedure code + /////////////////////////////////////////////////////////////////////////// + switch(i_operation) + { + case p9power::POWER_ON: + case p9power::POWER_ON_VDD: + { + // 4.3.8.1 Power-on via Hardware FSM + + // VDD first, VCS second + + // 1) Read PFETCNTLSTAT_REG: check for bits 0:3 being 0b0000 + l_data.flush<0>(). + setBit<VCS_PFET_VAL_OVERRIDE_BIT>(). + setBit<VCS_PFET_SEL_OVERRIDE_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data), + "putScom failed for address PPM_PFCS_CLR"); + + FAPI_DBG("Make sure that we are not forcing PFET for VCS or VDD off"); + FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data), + "getScom failed for address PPM_PFCS"); + l_data.extractToRight + <VDD_PFET_FORCE_STATE_BIT, 2 * PFET_STATE_LENGTH> + (l_temp); + FAPI_ASSERT((l_temp == 0), + fapi2::PMPROC_PFETLIB_BAD_SCOM() + .set_ADDRESS(PPM_PFCS[l_type]), + "PFET_FORCE_STATE not 0"); + + // 2) Set bits to program HW to enable VDD PFET, and + // 3) Poll state bit until Pfet sequence is complete + FAPI_TRY(powerOnVdd()); + + // 4) Set bits to program HW to enable VCS PFET, and + // 5) Poll state bit until Pfet sequence is complete + + // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work. + // Created a POWER_*_VDD label to delineate Vcs and Vdd + if (i_operation == p9power::POWER_ON) + { + FAPI_TRY(powerOnVcs()); + } + + } + break; + + case p9power::POWER_OFF: + case p9power::POWER_OFF_VDD: + { + // 4.3.8.2 Power-off via Hardware FSM + // 1) Read PFETCNTLSTAT_REG: check for bits 0:3 being 0b0000 + FAPI_DBG("Make sure that we are not forcing PFET for VCS or VDD off"); + FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data), + "getScom failed for address PPM_PFCS"); + + l_data.extractToRight + <VDD_PFET_FORCE_STATE_BIT, 2 * PFET_STATE_LENGTH> + (l_temp); + FAPI_ASSERT((l_temp == 0), + fapi2::PMPROC_PFETLIB_BAD_SCOM() + .set_ADDRESS(PPM_PFCS[l_type]), + "PFET_FORCE_STATE not 0"); + + // 2) Set bits to program HW to turn off VCS PFET, and + // 3) Poll state bit until Pfet sequence is complete + + // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work. + // Created a POWER_*_VDD label to delineate Vcs and Vdd + if (i_operation == p9power::POWER_OFF) + { + FAPI_TRY(powerOffVcs()); + } + + // 4) Set bits to program HW to turn off VDD PFET, and + // 5) Poll state bit until Pfet sequence is complete + FAPI_TRY(powerOffVdd()); + + } + break; + } + + FAPI_INF("<<p9_common_poweronoff"); +fapi_try_exit: + return fapi2::current_err; +} // Procedure diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H new file mode 100644 index 00000000..9bb01bce --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H @@ -0,0 +1,140 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_poweronoff.H +/// @brief common procedure for power on/off +/// + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE:CME +// *HWP Level : 2 + +#ifndef __P9_COMMON_POWERONOFF_H__ +#define __P9_COMMON_POWERONOFF_H__ + +#include <fapi2.H> + +namespace p9power +{ +enum powerOperation_t +{ + POWER_ON = 0x0, + POWER_OFF = 0xFF, + POWER_ON_VDD = 0x1, + POWER_OFF_VDD = 0xFE +}; + + + +// For SBE, the initial power-on times are not overly time critical so they are +// hardcoded for the delay necessary when running with the fastest nest (2.4GHz). +// When these same values are used with slower nest frequencies, the delays will +// get longer (more conservative). +// +// For istep 15, the delay settings are computed based on the setting of +// ATTR_FREQ_PB +// +// pfet_delay = (1/nest_frequency_mhz)*1000*4 (PPM clock period in ns) * +// 2^(15-pfet_delay_value). +// +// or +// +// pfet_delay +// 2^(15-pfet_delay_value) = ------------------------------ +// (1/nest_frequency_mhz)*1000*4 +// +// pfet_delay * nest_frequency_mhz +// 2^(15-pfet_delay_value = ------------------------------ +// 1000*4 +// +// ( pfet_delay * nest_frequency_mhz) +// 15-pfet_delay_value = log2( ------------------------------) +// ( 1000*4 ) +// +// ( pfet_delay * nest_frequency_mhz) +// pfet_delay_value = 15 - log2( ------------------------------) +// ( 1000*4 ) +// +// ( pfet_delay * nest_frequency_mhz) +// logexp = ( ------------------------------) +// ( 1000*4 ) +// +// = pfet_delay * nest_frequency_mhz / (1000 * 4) +// = pfet_delay * (nest_frequency_mhz / (1000 * 4)) +// = pfet_delay * (2400 / (1000 * 4)) +// = pfet_delay * (.6) +// +// For core delay of 250ns per step, logexp = 250 * .6 = 150 +// --> log2(150) = 8 (rounded up to next integer) +// -- > pfet_delay_value = 15 - 8 = 7 +// +// For EQ delay of 500ns per step, logexp = 500 * .6 = 300 +// --> log2(150) = 9 (rounded up to next integer) +// -- > pfet_delay_value = 15 - 9 = 6 + + +enum pfetDelays +{ + PFET_DELAY_POWERDOWN_EQ = 0x1, + PFET_DELAY_POWERDOWN_CORE = 0x1, +#ifndef PRODUCT_DEFAULT_PFET_DELAYS + PFET_DELAY_POWERUP_EQ = 0x1, + PFET_DELAY_POWERUP_CORE = 0x1 +#else + PFET_DELAY_POWERUP_EQ = 0x6, + PFET_DELAY_POWERUP_CORE = 0x7 +#endif +}; + + +} // namespace + +/// @typedef p9_common_poweronoff_FP_t +/// function pointer typedef definition for HWP call support +/// @todo: consider template solution here +typedef fapi2::ReturnCode (*p9_common_poweronoff_FP_t) ( + const fapi2::Target < fapi2::TARGET_TYPE_EQ | + fapi2::TARGET_TYPE_CORE > &, + const p9power::powerOperation_t i_operation); + +/// @brief common procedure for power on/off +/// +/// @param [in] i_target TARGET_TYPE_EQ|TARGET_TYPE_CORE target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_TIMING - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +template <fapi2::TargetType K> +fapi2::ReturnCode +p9_common_poweronoff( + const fapi2::Target<K>& i_target, + const p9power::powerOperation_t i_operation); + +#endif // __P9_COMMON_POWERONOFF_H__ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C new file mode 100644 index 00000000..05cd69e7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_pro_epi_log.C +/// @brief common procedure prologue/epilogue routines +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +#include "p9_common_pro_epi_log.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + + fapi2::ReturnCode + p9_common_pro_epi_log( + const fapi2::Target < fapi2::TARGET_TYPE_EQ | + fapi2::TARGET_TYPE_CORE > & i_target, + int i_operation) + { + return fapi2::FAPI2_RC_SUCCESS; + + } // Procedure + + +} // extern C + + diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H new file mode 100644 index 00000000..f119bfaf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_pro_epi_log.H +/// @brief common procedure prologue/epilogue routines +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_COMMON_PRO_EPI_LOG_H__ +#define __P9_COMMON_PRO_EPI_LOG_H__ + +extern "C" +{ + +/// @typedef p9_common_pro_epi_log_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_common_pro_epi_log_FP_t) ( + const fapi2::Target < fapi2::TARGET_TYPE_EQ | + fapi2::TARGET_TYPE_CORE > &, + int); + + +/// @brief common procedure prologue/epilogue routines +/// +/// @param [in] i_target TARGET_TYPE_EQ|TARGET_TYPE_CORE target +/// @param [in] i_operation ENUM(PROLOG, EPILOG) +/// +/// @attr +/// @attritem ATTR_EX_PARIAL_GOOD - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_common_pro_epi_log( + const fapi2::Target < fapi2::TARGET_TYPE_EQ | + fapi2::TARGET_TYPE_CORE > & i_target, + int i_operation); + + +} // extern C + +#endif // __P9_COMMON_PRO_EPI_LOG_H__ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H new file mode 100644 index 00000000..d09b7014 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H @@ -0,0 +1,257 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_hcd_common.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_common.H +/// @brief common hcode includes + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE:CME +// *HWP Level : 2 + +#ifndef __P9_HCD_COMMON_H__ +#define __P9_HCD_COMMON_H__ + +//------------------------- +// Macros +//------------------------- + +// Create a multi-bit mask of \a n bits starting at bit \a b +#define BITS64(b, n) ((0xffffffffffffffffull << (64 - (n))) >> (b)) +#define BITS32(b, n) ((0xffffffff << (32 - (n))) >> (b)) +#define BITS16(b, n) ((0xffff << (16 - (n))) >> (b)) +#define BITS8(b, n) ((0xff << (8 - (n))) >> (b)) + +// Create a single bit mask at bit \a b +#define BIT64(b) BITS64((b), 1) +#define BIT32(b) BITS32((b), 1) +#define BIT16(b) BITS16((b), 1) +#define BIT8(b) BITS8((b), 1) + +// Create a amount of shift to bit location \a b +#define SHIFT64(b) (63-b) +#define SHIFT32(b) (31-b) +#define SHIFT16(b) (15-b) +#define SHIFT8(b) (7-b) + + +// The BUF_* macros apply operations to a newly constructed buffer +#define BUF_SET(bit) fapi2::buffer<uint64_t>().setBit<bit>() +#define BUF_UNSET(bit) fapi2::buffer<uint64_t>().flush<1>().clearBit<bit>() +#define BUF_INSERT(start,size,val) \ + fapi2::buffer<uint64_t>().insertFromRight<start,size>(val) +#define BUF_REPLACE(start,size,val) \ + fapi2::buffer<uint64_t>().flush<1>().insertFromRight<start,size>(val) +// The following DATA_* and MASK_* macros assume you have +// "fapi2::buffer<uint64_t> l_data64" declared + +// The DATA_* macros apply operations to a buffer contains existing data +#define DATA_BIT(buf,op,bit) buf.op##Bit<bit>() +#define DATA_SET(bit) DATA_BIT(l_data64,set,bit) +#define DATA_UNSET(bit) DATA_BIT(l_data64,clear,bit) +#define DATA_FIELD(buf,start,size,val) buf.insertFromRight<start,size>(val) +#define DATA_INSERT(start,size,val) DATA_FIELD(l_data64,start,size,val) + +// The MASK_* macros apply operations to a buffer to create a new data mask +// data previously stored in the buffer will be overwritten. +#define MASK_FLUSH(buf,mask) buf.flush<mask>() +#define MASK_ZERO MASK_FLUSH(l_data64,0) +#define MASK_ALL MASK_FLUSH(l_data64,1) +#define MASK_BIT(buf,mask,op,bit) buf.flush<mask>().op##Bit<bit>() +#define MASK_SET(bit) MASK_BIT(l_data64,0,set,bit) +#define MASK_UNSET(bit) MASK_BIT(l_data64,1,clear,bit) +#define MASK_FIELD(buf,mask,start,size,val) \ + buf.flush<mask>().insertFromRight<start,size>(val) +#define MASK_OR(start,size,val) MASK_FIELD(l_data64,0,start,size,val) +#define MASK_AND(start,size,val) MASK_FIELD(l_data64,1,start,size,val) +#define MASK_CLR(start,size,val) MASK_FIELD(l_data64,0,start,size,val) + +//------------------------- +// Constants +//------------------------- + +namespace p9hcd +{ + +// Bit masks used by CME hcode +enum P9_HCD_CME_CORE_MASKS +{ + LEFT_CORE = 0x2, + RIGHT_CORE = 0x1, + BOTH_CORES = 0x3, + NO_CORE = 0x0 +}; + +// Control parameters for PCB Aribter +enum P9_HCD_PCB_ARBITER_CTRL +{ + REQUEST_ARBITER = 1, + RELEASE_ARBITER = 0 +}; + +// Constants to calculate hcd poll timeout intervals +enum P9_HCD_TIMEOUT_CONSTANTS +{ + CYCLES_PER_MS = 500000, // PPE FREQ 500MHZ + INSTS_PER_POLL_LOOP = 8 // +}; + +// Constants to calculate the delay in nanoseconds or simcycles +// Source | Domain | Freq | cyc/ns | Period | +// DPLL | Core | 4GHz | 4 | 250ps | +// | Cache | 2GHz | 2 | 500ps | +// | PPE | 500MHz | 0.5 | 2ns | +// Refclk | Refclk | 100Mhz | 0.1 | 10ns | +enum P9_HCD_DELAY_CONSTANTS +{ + SIM_CYCLE_1U1D = 2, // fastest internal oscillator + SIM_CYCLE_4U4D = 8, // 4Ghz ideal dpll + SIM_CYCLE_150UD = 300, // 133Mhz refclk + SIM_CYCLE_200UD = 400, // 100Mhz refclk external oscillator + CLK_PERIOD_250PS = 250, // 4GHZ dpll + CLK_PERIOD_10NS = 10, // 100Mhz refclk + CLK_PERIOD_CORE2CACHE = 2, + CLK_PERIOD_CORE2PPE = 8, + CLK_PERIOD_CORE2REF = 40 +}; + +// Chip Position Constants +enum P9_HCD_CHIP_POS_CONSTANTS +{ + PERV_TO_EQ_POS_OFFSET = 0x10, + PERV_TO_CORE_POS_OFFSET = 0x20 +}; + +// EX Constants +enum P9_HCD_EX_CTRL_CONSTANTS +{ + ODD_EX = 1, + EVEN_EX = 2, + BOTH_EX = 3, + QCSR_MASK_EX0 = (BIT64(0) | BIT64(2) | BIT64(4) | + BIT64(6) | BIT64(8) | BIT64(10)), + QCSR_MASK_EX1 = (BIT64(1) | BIT64(3) | BIT64(5) | + BIT64(7) | BIT64(9) | BIT64(11)) +}; + +// Multicast Constants +enum P9_HCD_MULTICAST_CONSTANTS +{ + MULTICAST_GROUP_4 = 4, // QUAD + MULTICAST_GROUP_5 = 5, // EX0 + MULTICAST_GROUP_6 = 6 // EX1 +}; + +// Clock Control Constants +enum P9_HCD_CLK_CTRL_CONSTANTS +{ + CLK_STOP_CMD = BIT64(0), + CLK_START_CMD = BIT64(1), + CLK_REGION_ANEP = BIT64(10), + CLK_REGION_DPLL = BIT64(14), + CLK_REGION_REFR = BITS64(12, 2), + CLK_REGION_L3_REFR = BITS64(6, 2) | BITS64(12, 2), + CLK_REGION_EX0_L3 = BIT64(6), + CLK_REGION_EX1_L3 = BIT64(7), + CLK_REGION_EX0_L2 = BIT64(8), + CLK_REGION_EX1_L2 = BIT64(9), + CLK_REGION_EX0_REFR = BIT64(12), + CLK_REGION_EX1_REFR = BIT64(13), + CLK_REGION_EX0_L2_L3_REFR = BIT64(6) | BIT64(8) | BIT64(12), + CLK_REGION_EX1_L2_L3_REFR = BIT64(7) | BIT64(9) | BIT64(13), + CLK_REGION_ALL_BUT_L3_REFR = BITS64(4, 2) | BITS64(8, 4) | BIT64(14), + CLK_REGION_ALL_BUT_L3_REFR_DPLL = BITS64(4, 2) | BITS64(8, 4), + CLK_REGION_ALL_BUT_EX = BITS64(4, 2) | BITS64(10, 2) | BIT64(14), + CLK_REGION_ALL_BUT_EX_DPLL = BITS64(4, 2) | BITS64(10, 2), + CLK_REGION_ALL_BUT_EX_ANEP_DPLL = BITS64(4, 2) | BIT64(11), + CLK_REGION_ALL_BUT_PLL = BITS64(4, 10), + CLK_REGION_ALL_BUT_PLL_REFR = BITS64(4, 8), + CLK_REGION_ALL = BITS64(4, 11), + CLK_THOLD_ALL = BITS64(48, 3) +}; + +// Scan Flush Constants +enum P9_HCD_SCAN0_CONSTANTS +{ + SCAN0_REGION_ALL = 0x7FF, + SCAN0_REGION_ALL_BUT_PLL = 0x7FE, + SCAN0_REGION_ALL_BUT_EX = 0x619, + SCAN0_REGION_ALL_BUT_EX_DPLL = 0x618, + SCAN0_REGION_ALL_BUT_EX_ANEP_DPLL = 0x608, + SCAN0_REGION_EX0_L2_L3_REFR = 0x144, + SCAN0_REGION_EX1_L2_L3_REFR = 0x0A2, + SCAN0_TYPE_GPTR_REPR_TIME = 0x230, + SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME = 0xDCF +}; + +//OCC FLag defines +enum PM_GPE_OCCFLG_DEFS +{ + SGPE_ACTIVE = 8 +}; + +// XSR defines +enum XSR_DEFS +{ + HALTED_STATE = 0 +}; + +// XCR defines +enum XCR_DEFS +{ + CLEAR_DEBUG_STATUS = 0, + HALT = 1, + RESUME = 2, + SINGLE_STEP = 3, + TOGGLE_XSR_TRH = 4, + SOFT_RESET = 5, + HARD_RESET = 6, + FORCE_HALT = 7 +}; + + +} // END OF NAMESPACE p9hcd + + +#define P9_HCD_SCAN_FUNC_REPEAT 1 +#define P9_HCD_SCAN_GPTR_REPEAT 1 + +/// @todo remove these once correct header contains them +/// Scom addresses missing from p9_quad_scom_addresses.H +#define PU_OCB_OCI_QSSR_CLEAR PU_OCB_OCI_QSSR_SCOM1 +#define PU_OCB_OCI_QSSR_OR PU_OCB_OCI_QSSR_SCOM2 +#define EQ_QPPM_QCCR_WCLEAR EQ_QPPM_QCCR_SCOM1 +#define EQ_QPPM_QCCR_WOR EQ_QPPM_QCCR_SCOM2 +#define EX_0_CME_SCOM_SICR_CLEAR EX_0_CME_SCOM_SICR_SCOM1 +#define EX_1_CME_SCOM_SICR_CLEAR EX_1_CME_SCOM_SICR_SCOM1 +#define EX_0_CME_SCOM_SICR_OR EX_0_CME_SCOM_SICR_SCOM2 +#define EX_1_CME_SCOM_SICR_OR EX_1_CME_SCOM_SICR_SCOM2 +#define CME_LCL_SICR_OR 0xc0000510 +#define CME_LCL_SICR_CLR 0xc0000518 +#define CME_LCL_SISR 0xc0000520 + +#endif // __P9_HCD_COMMON_H__ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H b/src/import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H new file mode 100644 index 00000000..38e94226 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H @@ -0,0 +1,76 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_common.H +/// @brief common hcode includes +/// + +// *HWP HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP HWP BackupeOwner : David Du <daviddu@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:HS:CRO + +#ifndef __P9_SSH_H__ +#define __P9_SSH_H__ + + +namespace p9ssh +{ + +// Note: these are not autogenerated as multiple registers have the +// same bit layout +static const uint32_t STOP_GATED_START = 0; +static const uint32_t STOP_GATED_LEN = 1; + +static const uint32_t STOP_TRANSITION_START = 2; +static const uint32_t STOP_TRANSITION_LEN = 2; + +static const uint32_t STOP_REQUESTED_LEVEL_START = 4; +static const uint32_t STOP_REQUESTED_LEVEL_LEN = 4; + +static const uint32_t STOP_ACTUAL_LEVEL_START = 8; +static const uint32_t STOP_ACTUAL_LEVEL_LEN = 4; + +static const uint32_t STOP_REQ_WRITE_EN = 12; +static const uint32_t STOP_ACT_WRITE_EN = 13; + +enum STOP_HISTORY_GATED +{ + SSH_RUNNING = 0, + SSH_GATED = 1 +}; + +enum STOP_HISTORY_TRANSITION +{ + SSH_COMPLETE = 0, + SSH_CORE_COMPLETE = 1, + SSH_ENTERING = 2, + SSH_EXITING = 3, + SSH_UNDEFINED = 255 +}; + +} // namespace +#endif // __P9_SSH_H__ diff --git a/src/import/chips/p9/procedures/hwp/nest/Makefile b/src/import/chips/p9/procedures/hwp/nest/Makefile new file mode 100644 index 00000000..8c4adc0b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/Makefile @@ -0,0 +1,58 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/nest/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the nest hardware procedure code. See the +# "nestfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/nest +export SUB_OBJDIR = /nest + +include img_defs.mk +include nestfiles.mk + +# TODO via RTC 152424 +# Adding VPATH as there are few procedures which are in +# perv folder but we are compiling them here. Refer to +# nestfiles.mk for details. +export VPATH = $(PERV_SRCDIR):$(NEST_SRCDIR) +OBJS := $(addprefix $(OBJDIR)/, $(NEST_OBJECTS)) + +libnest.a: nest + $(AR) crs $(OBJDIR)/libnest.a $(OBJDIR)/*.o + +.PHONY: clean nest +nest: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk b/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk new file mode 100644 index 00000000..b3ddbdff --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk @@ -0,0 +1,59 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/nest/nestfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file nestfiles.mk +# +# @brief mk for including nest object files +# +########################################################################## +# Object Files +########################################################################## + +NEST-CPP-SOURCES = p9_sbe_mcs_setup.C +NEST-CPP-SOURCES +=p9_sbe_scominit.C +NEST-CPP-SOURCES +=p9_sbe_fabricinit.C +NEST-CPP-SOURCES +=p9_fbc_utils.C +NEST-CPP-SOURCES +=p9_sbe_load_bootloader.C +NEST-CPP-SOURCES +=p9_pba_access.C +NEST-CPP-SOURCES +=p9_pba_coherent_utils.C +NEST-CPP-SOURCES +=p9_pba_setup.C +NEST-CPP-SOURCES +=p9_adu_access.C +NEST-CPP-SOURCES +=p9_adu_setup.C +NEST-CPP-SOURCES +=p9_adu_coherent_utils.C +# TODO via RTC 152424 +# p9_ram_core.C will go to runtime makefile. Currently this procedure is in +# perv directory. As we are putting perv procedures currently in SEEPROM. +# So compiling p9_ram_core.C in nest makefile. +NEST-CPP-SOURCES +=p9_ram_core.C +# TODO via RTC 152424 +# swicth gear proecdures are in perv directory. But these procedures needs to +# be executed from PIBMEM. So compiling these is nest makefile. +NEST-CPP-SOURCES +=p9_sbe_gear_switcher.C +NEST-CPP-SOURCES +=p9_sbe_tp_switch_gears.C +NEST-C-SOURCES = +NEST-S-SOURCES = + +NEST_OBJECTS += $(NEST-CPP-SOURCES:.C=.o) +NEST_OBJECTS += $(NEST-C-SOURCES:.c=.o) +NEST_OBJECTS += $(NEST-S-SOURCES:.S=.o) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C new file mode 100644 index 00000000..360c5837 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_access.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//-------------------------------------------------------------------------- +// +// +/// @file p9_adu_access.C +/// @brief Read coherent state of memory via the ADU (FAPI) +/// +// *HWP HWP Owner Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// +//-------------------------------------------------------------------------- + + +//-------------------------------------------------------------------------- +// Includes +//-------------------------------------------------------------------------- +#include <p9_adu_access.H> +#include <p9_adu_coherent_utils.H> + +extern "C" { + +//-------------------------------------------------------------------------- +// HWP entry point +//-------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_access(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + const bool i_firstGranule, + const bool i_lastGranule, + uint8_t io_data[]) + { + + bool l_busyBitStatus = false; + adu_status_busy_handler l_busyHandling; + + // mark HWP entry + FAPI_DBG("Entering ...\n"); + + // Process input flag + p9_ADU_oper_flag l_myAduFlag; + l_myAduFlag.getFlag(i_flags); + + if( i_lastGranule && l_myAduFlag.getAutoIncrement() ) + { + //call this function to clear the altd_auto_inc bit before the last iteration + FAPI_TRY(p9_adu_coherent_clear_autoinc(i_target), "Error from p9_adu_coherent_clear_autoinc"); + } + + if (i_rnw) + { + //read the data + FAPI_TRY(p9_adu_coherent_adu_read(i_target, i_firstGranule, i_address, l_myAduFlag, io_data), + "Error from p9_adu_coherent_adu_read"); + } + else + { + //write the data + FAPI_TRY(p9_adu_coherent_adu_write(i_target, i_firstGranule, i_address, l_myAduFlag, io_data), + "Error from p9_adu_coherent_adu_write"); + } + + //If we are not in fastmode or this is the last granule, we want to check the status + if ( (i_lastGranule) || (l_myAduFlag.getFastMode() == false) ) + { + if ( (l_myAduFlag.getAutoIncrement()) && !i_lastGranule ) + { + // Only expect ADU busy if in AUTOINC AND it's not the last granule + l_busyHandling = EXPECTED_BUSY_BIT_SET; + } + else + { + l_busyHandling = EXPECTED_BUSY_BIT_CLEAR; + } + + FAPI_TRY(p9_adu_coherent_status_check(i_target, l_busyHandling, false, + l_busyBitStatus), + "Error from p9_adu_coherent_status_check"); + + //If it's the last read/write + if (i_lastGranule) + { + FAPI_TRY(p9_adu_coherent_cleanup_adu(i_target), + "Error doing p9_adu_coherent_cleanup_adu"); + } + } + + fapi_try_exit: + fapi2::ReturnCode saveError = fapi2::current_err; + + if ( fapi2::current_err && l_myAduFlag.getOperFailCleanup() ) + { + (void) p9_adu_coherent_utils_reset_adu(i_target); + uint32_t num_attempts = l_myAduFlag.getNumLockAttempts(); + (void) p9_adu_coherent_manage_lock(i_target, false, false, num_attempts); + } + + FAPI_DBG("Exiting..."); + return saveError; + } + +} // extern "C" + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H new file mode 100644 index 00000000..0b8e1a15 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H @@ -0,0 +1,105 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_access.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +// +/// @file p9_adu_access.H +/// @brief Read coherent state of memory via the ADU (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 1 +// *HWP Consumed by: +// ---------------------------------------------------------------------------------- +// +// *! ADDITIONAL COMMENTS : +// *! +// *! The purpose of this procedure is to perform a coherent read from system +// *! memory via fabric commands issued from the ADU. +// *! +// *! Succcessful operation assumes that: +// *! o System clocks are running +// *! o Fabric is initalized +// *! +// *! +//----------------------------------------------------------------------------------- + +#ifndef _P9_ADU_ACCESS_H_ +#define _P9_ADU_ACCESS_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +#include <fapi2.H> +#include <p9_adu_constants.H> +#include <p9_pba_constants.H> + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode +(*p9_adu_access_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const uint64_t, + const bool, + const uint32_t, + const bool, + const bool, + uint8_t[] ); + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +extern "C" { + +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- + +/// @brief do the actual read/write from the ADU +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => base real address for read/write operation (expected to be 8B aligned) +/// @param[in] i_rnw => if the operation is a read not write (1 for read, 0 for write) +/// @param[in] i_flags => other information that is needed - see the p9_adu_constants adu_flags enums for bit definitions +// Note: To construct the flag you can use p9_ADU_oper_flag class +/// @param[in] i_lastGranule => if this is the last 8B of data that we are collecting (true = last granule, false = not last granule) +/// @param[in] i_firstGranule => if this is the first 8B of data that we are collecting (true = first granule, false = not first granule) +/// @param[in, out] io_data => The data is read/written +/// @return FAPI_RC_SUCCESS if the read/write completes successfully + fapi2::ReturnCode p9_adu_access( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + const bool i_firstGranule, + const bool i_lastGranule, + uint8_t io_data[]); +} //extern "C" + +#endif //_P9_ADU_ACCESS_H_ + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C new file mode 100644 index 00000000..7782cae2 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C @@ -0,0 +1,986 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +// +/// @file p9_adu_coherent_utils.C +/// @brief ADU alter/display library functions (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// +//----------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_adu_coherent_utils.H> +#include <p9_misc_scom_addresses.H> +#include <p9_fbc_utils.H> + +extern "C" +{ + //--------------------------------------------------------------------------------- + // Constant definitions + //--------------------------------------------------------------------------------- + + //ADU Delay Constants + + //ADU register field/bit definitions + + // ADU Option Register field/bit definitions + const uint32_t FBC_ALTD_WITH_PRE_QUIESCE = 23; + const uint32_t FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT = 28; // Bits 28:47 + const uint32_t FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS = 20; + + const uint32_t FBC_ALTD_WITH_POST_INIT = 51; + const uint32_t FBC_ALTD_POST_INIT_COUNT_START_BIT = 54; // Bits 54:63 + const uint32_t FBC_ALTD_POST_INIT_COUNT_NUM_OF_BITS = 10; + + // ADU Command Register field/bit definitions + const uint32_t ALTD_CMD_START_OP_BIT = 2; + const uint32_t ALTD_CMD_CLEAR_STATUS_BIT = 3; + const uint32_t ALTD_CMD_RESET_FSM_BIT = 4; + const uint32_t ALTD_CMD_RNW_BIT = 5; + const uint32_t ALTD_CMD_ADDRESS_ONLY_BIT = 6; + const uint32_t ALTD_CMD_LOCK_PICK_BIT = 10; + const uint32_t ALTD_CMD_LOCK_BIT = 11; + const uint32_t ALTD_CMD_LOCK_ID_START_BIT = 12; + const uint32_t ALTD_CMD_LOCK_ID_END_BIT = 15; + const uint32_t ALTD_CMD_SCOPE_START_BIT = 16; + const uint32_t ALTD_CMD_SCOPE_END_BIT = 18; + const uint32_t ALTD_CMD_AUTO_INC_BIT = 19; + const uint32_t ALTD_CMD_DROP_PRIORITY_BIT = 20; + const uint32_t ALTD_CMD_DROP_PRIORITY_MAX_BIT = 21; + const uint32_t ALTD_CMD_OVERWRITE_PBINIT_BIT = 22; + const uint32_t ALTD_CMD_PIB_DIRECT_BIT = 23; + const uint32_t ALTD_CMD_WITH_TM_QUIESCE_BIT = 24; + const uint32_t ALTD_CMD_TTYPE_START_BIT = 25; + const uint32_t ALTD_CMD_TTYPE_END_BIT = 31; + const uint32_t ALTD_CMD_TSIZE_START_BIT = 32; + const uint32_t ALTD_CMD_TSIZE_END_BIT = 39; + + const uint32_t ALTD_CMD_SCOPE_NUM_BITS = (ALTD_CMD_SCOPE_END_BIT - + ALTD_CMD_SCOPE_START_BIT) + 1; + const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT - + ALTD_CMD_TTYPE_START_BIT) + 1; + const uint32_t ALTD_CMD_TSIZE_NUM_BITS = (ALTD_CMD_TSIZE_END_BIT - + ALTD_CMD_TSIZE_START_BIT) + 1; + + const uint32_t ALTD_CMD_TTYPE_CL_DMA_RD = 6; //0b0000110 + const uint32_t ALTD_CMD_TTYPE_DMA_PR_WR = 38; //0b0100110 + const uint32_t ALTD_CMD_TTYPE_CI_PR_RD = 52; //0b0110100 + const uint32_t ALTD_CMD_TTYPE_CI_PR_WR = 55; //0b0110111 + const uint32_t ALTD_CMD_TTYPE_PB_OPER = 0b0111111; + const uint32_t ALTD_CMD_TTYPE_PMISC_OPER = 0b0110001; + + //these should be 1, 2, 3, 4 but they are shifted over one to the left because for + //ci_pr_rd and ci_pr_w the secondary encode is 0ttt ssss0 + const uint32_t ALTD_CMD_CI_TSIZE_1 = 2; + const uint32_t ALTD_CMD_CI_TSIZE_2 = 4; + const uint32_t ALTD_CMD_CI_TSIZE_4 = 6; + const uint32_t ALTD_CMD_CI_TSIZE_8 = 8; + //these should be 1, 2, 4, 8 but they are shifted over one to the left because for + //dma_pr_w the secondary encode is tSize & '0' + const uint32_t ALTD_CMD_DMAW_TSIZE_1 = 2; + const uint32_t ALTD_CMD_DMAW_TSIZE_2 = 4; + const uint32_t ALTD_CMD_DMAW_TSIZE_4 = 8; + const uint32_t ALTD_CMD_DMAW_TSIZE_8 = 16; + //I think that the secondary encoding should always be 0 for cl_dma_rd + const uint32_t ALTD_CMD_DMAR_TSIZE = 0; + + // Values for PB operations + const uint32_t ALTD_CMD_PB_OPERATION_TSIZE = 0b00001000; + const uint32_t ALTD_CMD_SCOPE_SYSTEM = 0b00000101; + + // Values for PMISC operations + const uint32_t ALTD_CMD_PMISC_TSIZE_1 = 0b00000010; // PMISC SWITCH + const uint32_t ALTD_CMD_PMISC_TSIZE_2 = 0b01000000; // PMISC HTM + + // OPTION reg values for SWITCH operation + const uint32_t QUIESCE_SWITCH_WAIT_COUNT = 128; + const uint32_t INIT_SWITCH_WAIT_COUNT = 128; + + // ADU Status Register field/bit definitions + const uint32_t ALTD_STATUS_BUSY_BIT = 0; + const uint32_t ALTD_STATUS_WAIT_CMD_ARBIT = 1; + const uint32_t ALTD_STATUS_ADDR_DONE_BIT = 2; + const uint32_t ALTD_STATUS_DATA_DONE_BIT = 3; + const uint32_t ALTD_STATUS_WAIT_RESP_BIT = 4; + const uint32_t ALTD_STATUS_OVERRUN_ERROR_BIT = 5; + const uint32_t ALTD_STATUS_AUTOINC_ERR_BIT = 6; + const uint32_t ALTD_STATUS_COMMAND_ERR_BIT = 7; + const uint32_t ALTD_STATUS_ADDRESS_ERR_BIT = 8; + const uint32_t ALTD_STATUS_PB_OP_HANG_ERR_BIT = 9; + const uint32_t ALTD_STATUS_PB_DATA_HANG_ERR_BIT = 10; + const uint32_t ALTD_STATUS_PB_UNEXPECT_CRESP_ERR_BIT = 11; + const uint32_t ALTD_STATUS_WAIT_PIB_DIRECT = 16; + const uint32_t ALTD_STATUS_PIB_DIRECT_DONE = 17; + const uint32_t ALTD_STATUS_PBINIT_MISSING_BIT = 18; + const uint32_t ALTD_STATUS_ECC_CE_BIT = 48; + const uint32_t ALTD_STATUS_ECC_UE_BIT = 49; + const uint32_t ALTD_STATUS_ECC_SUE_BIT = 50; + const uint32_t ALTD_STATUS_CRESP_START_BIT = 59; + const uint32_t ALTD_STATUS_CRESP_END_BIT = 63; + + const uint32_t ALTD_STATUS_CRESP_NUM_BITS = (ALTD_STATUS_CRESP_END_BIT + - ALTD_STATUS_CRESP_START_BIT + 1); + + //FORCE ECC Register field/bit definitions + const uint32_t ALTD_DATA_ITAG_BIT = 0; + const uint32_t ALTD_DATA_TX_ECC_START_BIT = 1; + const uint32_t ALTD_DATA_TX_ECC_END_BIT = 16; + const uint32_t ALTD_DATA_TX_ECC_OVERWRITE_BIT = 17; + + const uint32_t ALTD_DATA_ECC_MASK = 0xFFFFull; + + // ADU operation delay times for HW/sim + const uint32_t PROC_ADU_UTILS_ADU_HW_NS_DELAY = 100000; + const uint32_t PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY = 50000; + const uint32_t PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY = 20000; + + //--------------------------------------------------------------------------------- + // Function definitions + //--------------------------------------------------------------------------------- + + //--------------------------------------------------------------------------------- + // NOTE: description in header + //--------------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_coherent_utils_check_args( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const uint32_t i_flags) + { + FAPI_DBG("Start"); + + p9_ADU_oper_flag l_myAduFlag; + p9_ADU_oper_flag::Transaction_size_t l_transSize; + uint32_t l_actualTransSize; + + l_transSize = l_myAduFlag.getTransactionSize(); + + if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) + { + l_actualTransSize = 1; + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) + { + l_actualTransSize = 2; + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 ) + { + l_actualTransSize = 4; + } + else + { + l_actualTransSize = 8; + } + + //Check the address alignment + FAPI_ASSERT(!(i_address & (l_actualTransSize - 1)), + fapi2::P9_ADU_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( + i_address), + "Address is not cacheline aligned"); + + //Make sure the address is within the ADU bounds + FAPI_ASSERT(i_address <= P9_FBC_UTILS_FBC_MAX_ADDRESS, + fapi2::P9_ADU_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( + i_address), + "Address exceeds supported fabric real address range"); + + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + //--------------------------------------------------------------------------------- + // NOTE: description in header + //--------------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_coherent_utils_check_fbc_state( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + bool fbc_initialized = false; + bool fbc_running = false; + FAPI_DBG("Start"); + + //Make sure the fabric is initialized and running + FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, fbc_initialized, fbc_running), + "Error from p9_fbc_utils_get_fbc_state"); + FAPI_ASSERT(fbc_initialized + && fbc_running, fapi2::P9_ADU_FBC_NOT_INITIALIZED_ERR().set_TARGET(i_target).set_INITIALIZED( + fbc_initialized).set_RUNNING( + fbc_running), "Fabric is not initialized or running"); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + + } + + //--------------------------------------------------------------------------------- + // NOTE: description in header + //--------------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_coherent_utils_get_num_granules( + const uint64_t i_address, + uint32_t& o_numGranules) + { + fapi2::ReturnCode rc; + FAPI_DBG("Start"); + //From the address figure out when it is going to no longer be within the ADU bound by + //doing the max fbc address minus the address and then divide by 8 to get number of bytes + //and by 8 to get number of 8 byte granules that can be sent + o_numGranules = ((P9_FBC_UTILS_FBC_MAX_ADDRESS - i_address) / 8) / 8; + FAPI_DBG("Exiting"); + return rc; + } + + + + /// + /// @brief Setup the value for ADU option register to enable + /// quiesce & init around a switch operation. + /// + /// @param [in] i_target Proc target + /// + /// @return FAPI2_RC_SUCCESS if OK + /// + fapi2::ReturnCode setQuiesceInit( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + FAPI_DBG("Start"); + fapi2::ReturnCode l_rc; + fapi2::buffer<uint64_t> altd_option_reg_data(0); + + // Set up quiesce + altd_option_reg_data.setBit<FBC_ALTD_WITH_PRE_QUIESCE>(); + altd_option_reg_data.insertFromRight<FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT, + FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS> + (QUIESCE_SWITCH_WAIT_COUNT); + + // Setup Post-command init + altd_option_reg_data.setBit<FBC_ALTD_WITH_POST_INIT>(); + altd_option_reg_data.insertFromRight<FBC_ALTD_POST_INIT_COUNT_START_BIT, + FBC_ALTD_POST_INIT_COUNT_NUM_OF_BITS> + (INIT_SWITCH_WAIT_COUNT); + + // Write to ADU option reg + FAPI_DBG("OPTION reg value 0x%016llX", altd_option_reg_data); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_OPTION_REG, altd_option_reg_data), + "Error writing to PU_ALTD_OPTION_REG register"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + //--------------------------------------------------------------------------------- + // NOTE: description in header + //--------------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_coherent_setup_adu( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags) + { + FAPI_DBG("Start Addr 0x%.16llX, Flag 0x%.8X", i_address, i_flags); + + fapi2::ReturnCode rc; + fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0); + fapi2::buffer<uint64_t> altd_addr_reg_data(i_address); + fapi2::buffer<uint64_t> altd_data_reg_data(0x0); + fapi2::buffer<uint64_t> altd_option_reg(0x0); + p9_ADU_oper_flag l_myAduFlag; + p9_ADU_oper_flag::OperationType_t l_operType; + p9_ADU_oper_flag::Transaction_size_t l_transSize; + + // Write to the altd_cmd_reg to set the fbc_locked bit + altd_cmd_reg_data.setBit<ALTD_CMD_LOCK_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), + "Error writing the lock bit to ALTD_CMD Register"); + + //Write the address into altd_addr_reg + FAPI_DBG("Write PU_ALTD_ADDR_REG 0x%.16llX, Value 0x%.16llX", + PU_ALTD_ADDR_REG, altd_addr_reg_data); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_ADDR_REG, altd_addr_reg_data), + "Error writing to ALTD_ADDR Register"); + + // Process input flag + l_myAduFlag.getFlag(i_flags); + l_operType = l_myAduFlag.getOperationType(); + l_transSize = l_myAduFlag.getTransactionSize(); + + // --------------------------------------------- + // Setting for DMA and CI operations + // --------------------------------------------- + if ( (l_operType == p9_ADU_oper_flag::CACHE_INHIBIT) || + (l_operType == p9_ADU_oper_flag::DMA_PARTIAL) ) + { + + // --------------------------------------------- + // DMA & CI common settings + // --------------------------------------------- + // Write the altd_cmd_reg + // Set fbc_altd_rnw if it's a read + if (i_rnw) + { + altd_cmd_reg_data.setBit<ALTD_CMD_RNW_BIT>(); + } + // Clear fbc_altd_rnw if it's a write + else + { + altd_cmd_reg_data.clearBit<ALTD_CMD_RNW_BIT>(); + } + + // If auto-inc set the auto-inc bit + if (l_myAduFlag.getAutoIncrement() == true) + { + altd_cmd_reg_data.setBit<ALTD_CMD_AUTO_INC_BIT>(); + } + + // --------------------------------------------------- + // Cache Inhibit specific: TTYPE & TSIZE + // --------------------------------------------------- + if (l_operType == p9_ADU_oper_flag::CACHE_INHIBIT) + { + FAPI_DBG("ADU operation type: Cache Inhibited"); + + // Set TTYPE + if (i_rnw) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CI_PR_RD); + } + else + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CI_PR_WR); + } + + // Set TSIZE + if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_1); + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_2); + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_4); + } + else + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_8); + } + } + + // --------------------------------------------------- + // DMA specific: TTYPE & TSIZE + // --------------------------------------------------- + else if (l_operType == p9_ADU_oper_flag::DMA_PARTIAL) + { + FAPI_DBG("ADU operation type: DMA"); + + // If a read, set ALTD_CMD_TTYPE_CL_DMA_RD + // Set the tsize to ALTD_CMD_DMAR_TSIZE + if (i_rnw) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CL_DMA_RD); + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAR_TSIZE); + } + // If a write set ALTD_CMD_TTYPE_DMA_PR_WR + // Set the tsize according to flag setting + else + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, + ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_DMA_PR_WR); + + // Set TSIZE + if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_1); + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_2); + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_4); + } + else + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_8); + } + } + } + } + + // --------------------------------------------- + // Setting for PB and PMISC operations + // --------------------------------------------- + if ( (l_operType == p9_ADU_oper_flag::PB_OPER) || + (l_operType == p9_ADU_oper_flag::PMISC_OPER) ) + { + + // --------------------------------------------- + // PB & PMISC common settings + // --------------------------------------------- + + // Set the start op bit + altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>(); + + // Set operation scope + altd_cmd_reg_data.insertFromRight<ALTD_CMD_SCOPE_START_BIT, + ALTD_CMD_SCOPE_NUM_BITS>(ALTD_CMD_SCOPE_SYSTEM); + + // Set DROP_PRIORITY = HIGH + altd_cmd_reg_data.setBit<ALTD_CMD_DROP_PRIORITY_BIT>(); + + // Set AXTYPE = Address only + altd_cmd_reg_data.setBit<ALTD_CMD_ADDRESS_ONLY_BIT>(); + + // Set OVERWRITE_PBINIT + altd_cmd_reg_data.setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>(); + + // Set TM_QUIESCE + altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>(); + + + // --------------------------------------------------- + // PB specific: TTYPE & TSIZE + // --------------------------------------------------- + if (l_operType == p9_ADU_oper_flag::PB_OPER) + { + FAPI_DBG("ADU operation type: PB"); + + // Set TTYPE + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, + ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PB_OPER); + + // TSIZE for PB operation is fixed value: 0b00001000 + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PB_OPERATION_TSIZE); + } + + // --------------------------------------------------- + // PMISC specific: TTYPE & TSIZE + // --------------------------------------------------- + else if (l_operType == p9_ADU_oper_flag::PMISC_OPER) + { + FAPI_DBG("ADU operation type: PMISC"); + + // Set TTYPE + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, + ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PMISC_OPER); + + // Set TSIZE + if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_1); + } + else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 ) + { + altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, + ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_2); + } + + // Set quiesce and init around a switch operation in option reg + FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error"); + } + } + + //This sets everything that should be set for the ALTD_CMD_Register + FAPI_DBG("CMD reg value 0x%016llX", altd_cmd_reg_data); + + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), + "Error writing to ALTD_CMD Register"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + //--------------------------------------------------------------------------------- + // NOTE: description in header + //--------------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_coherent_adu_write( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const bool i_firstGranule, + const uint64_t i_address, + p9_ADU_oper_flag& i_aduOper, + const uint8_t i_write_data[]) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> altd_cmd_reg_data; + fapi2::buffer<uint64_t> altd_status_reg_data; + fapi2::buffer<uint64_t> force_ecc_reg_data; + uint64_t write_data = 0x0ull; + int eccIndex = 8; + + // Get ADU operation info from flag + bool l_itagMode = i_aduOper.getItagMode(); + bool l_eccMode = i_aduOper.getEccMode(); + bool l_overrideEccMode = i_aduOper.getEccItagOverrideMode(); + bool l_autoIncMode = i_aduOper.getAutoIncrement(); + bool l_accessForceEccReg = (l_itagMode | l_eccMode | l_overrideEccMode); + + // Dump ADU write settings + FAPI_DBG("Modes: ITAG 0x%.8X, ECC 0x%.8X, OVERRIDE_ECC 0x%.8X", + l_itagMode, l_eccMode, l_overrideEccMode); + FAPI_DBG(" AUTOINC 0x%.8X", l_autoIncMode); + + for (int i = 0; i < 8; i++) + { + write_data |= ( static_cast<uint64_t>(i_write_data[i]) << (56 - (8 * i)) ); + } + + fapi2::buffer<uint64_t> altd_data_reg_data(write_data); + + if (l_accessForceEccReg == true) + { + FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error reading the FORCE_ECC Register"); + } + + //if we want to write the itag bit set it + if (l_itagMode == true) + { + eccIndex++; + force_ecc_reg_data.setBit<ALTD_DATA_ITAG_BIT>(); + } + + //if we want to write the ecc data get the data + if (l_eccMode == true) + { + force_ecc_reg_data.insertFromRight < ALTD_DATA_TX_ECC_START_BIT, + (ALTD_DATA_TX_ECC_END_BIT - ALTD_DATA_TX_ECC_START_BIT) + 1 > + ((uint64_t)i_write_data[eccIndex]); + } + + //if we want to overwrite the ecc data + if (l_overrideEccMode == true) + { + force_ecc_reg_data.setBit<ALTD_DATA_TX_ECC_OVERWRITE_BIT>(); + } + + if (l_accessForceEccReg == true) + { + FAPI_TRY(fapi2::putScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error writing to the FORCE_ECC Register"); + } + + //write the data into the altd_data_reg + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_DATA_REG, altd_data_reg_data), + "Error writing to ALTD_DATA Register"); + + //Set the ALTD_CMD_START_OP bit to start the write(first granule for autoinc case or not autoinc) + if ( i_firstGranule || (l_autoIncMode == false) ) + { + //read the altd_cmd_register + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from the ALTD_CMD_REG"); + //set the start op bit + altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>(); + //write the altd_cmd_register + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG"); + } + + //delay to allow time for the write to go through before we check the status + FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY, + PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY), + "fapiDelay error"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + //--------------------------------------------------------------------------------- + // NOTE: description in header + //--------------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_coherent_adu_read( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const bool i_firstGranule, + const uint64_t i_address, + p9_ADU_oper_flag& i_aduOper, + uint8_t o_read_data[]) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> altd_cmd_reg_data; + fapi2::buffer<uint64_t> altd_status_reg_data; + fapi2::buffer<uint64_t> altd_data_reg_data; + fapi2::buffer<uint64_t> force_ecc_reg_data; + int eccIndex = 8; + + // Get ADU operation info from flag + bool l_itagMode = i_aduOper.getItagMode(); + bool l_eccMode = i_aduOper.getEccMode(); + bool l_autoIncMode = i_aduOper.getAutoIncrement(); + + // Dump ADU read settings + FAPI_DBG("Modes: ITAG 0x%.8X, ECC 0x%.8X, AUTOINC 0x%.8X", + l_itagMode, l_eccMode, l_autoIncMode); + + //Set the ALTD_CMD_START_OP bit to start the read(first granule for autoinc case or not autoinc) + if ( i_firstGranule || (l_autoIncMode == false) ) + { + //read the altd_cmd_register + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from the ALTD_CMD_REG"); + //set the start op bit + altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>(); + //write the altd_cmd_register + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG"); + } + + //delay to allow time for the read to go through before we get the data + FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY, + PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY), + "fapiDelay error"); + + + //if we want to include the itag and ecc data collect them before the read + if ( l_itagMode || l_eccMode ) + { + FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), + "Error reading from the FORCE_ECC Register"); + } + + if (l_itagMode) + { + eccIndex = 9; + o_read_data[8] = force_ecc_reg_data.getBit<ALTD_DATA_ITAG_BIT>(); + } + + if (l_eccMode) + { + o_read_data[eccIndex] = (force_ecc_reg_data >> (63 - ALTD_DATA_TX_ECC_END_BIT)) & ALTD_DATA_ECC_MASK; + } + + //read data from altd_data_reg + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_DATA_REG, altd_data_reg_data), + "Error reading from the ALTD_DATA Register"); + + for (int i = 0; i < 8; i++) + { + o_read_data[i] = (altd_data_reg_data >> (56 - (i * 8))) & 0xFFull; + } + + FAPI_DBG("o_read_data[8] = %8X", o_read_data[8]); + //o_read_data[0] = altd_data_reg_data; + FAPI_DBG("altd_data_reg_data = %lu\n", altd_data_reg_data); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_adu_coherent_utils_reset_adu( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0); + + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from ALTD_CMD Register"); + + //write altd_cmd_reg to set the reset_fsm bit + altd_cmd_reg_data.setBit<ALTD_CMD_RESET_FSM_BIT>(); + altd_cmd_reg_data.setBit<ALTD_CMD_CLEAR_STATUS_BIT>(); + altd_cmd_reg_data.setBit<ALTD_CMD_LOCK_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), + "Error setting the reset_fsm bit from the ALTD_CMD Register"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + //--------------------------------------------------------------------------------- + // NOTE: description in header + //--------------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_coherent_cleanup_adu( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0); + + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), + "Error reading from ALTD_CMD Register"); + + //write altd_cmd_reg to clear the fbc_locked bit + altd_cmd_reg_data.clearBit<ALTD_CMD_LOCK_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), + "Error clearing the fbc_locked bit from the ALTD_CMD Register"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_adu_coherent_status_check( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const adu_status_busy_handler i_busyBitHandler, + const bool i_addressOnlyOper, + bool& o_busyBitStatus) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> l_statusReg(0x0); + bool l_statusError = false; + + for (int i = 0; i < 10; i++) + { + l_statusError = false; + // Check the ALTD_STATUS_REG + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_statusReg), + "Error reading from ALTD_STATUS Register"); + FAPI_DBG("PU_ALTD_STATUS_REG reg value 0x%016llX", l_statusReg); + + // ---- Handle busy options ---- + + // Get busy bit output + o_busyBitStatus = l_statusReg.getBit<ALTD_STATUS_BUSY_BIT>(); + + // Handle busy bit according to specified input + if (o_busyBitStatus == true) + { + // Exit if busy + if (i_busyBitHandler == EXIT_ON_BUSY) + { + goto fapi_try_exit; + } + else if (i_busyBitHandler == EXPECTED_BUSY_BIT_CLEAR) + { + l_statusError = true; + } + } + else if (i_busyBitHandler == EXPECTED_BUSY_BIT_SET) + { + l_statusError = true; + } + + // ---- Check for other errors ---- + // Check the WAIT_CMD_ARBIT bit and make sure it's 0 + // Check the ADDR_DONE bit and make sure it's set + // Check the DATA_DONE bit and make sure it's set + // Check the WAIT_RESP bit to make sure it's clear + // Check the OVERRUN_ERR to make sure it's clear + // Check the AUTOINC_ERR to make sure it's clear + // Check the COMMAND_ERR to make sure it's clear + // Check the ADDRESS_ERR to make sure it's clear + // Check the COMMAND_HANG_ERR to make sure it's clear + // Check the DATA_HANG_ERR to make sure it's clear + // Check the PBINIT_MISSING to make sure it's clear + // Check the ECC_CE to make sure it's clear + // Check the ECC_UE to make sure it's clear + // Check the ECC_SUE to make sure it's clear + l_statusError = + ( l_statusError || + l_statusReg.getBit<ALTD_STATUS_WAIT_CMD_ARBIT>() || + !l_statusReg.getBit<ALTD_STATUS_ADDR_DONE_BIT>() || + l_statusReg.getBit<ALTD_STATUS_WAIT_RESP_BIT>() || + l_statusReg.getBit<ALTD_STATUS_OVERRUN_ERROR_BIT>() || + l_statusReg.getBit<ALTD_STATUS_AUTOINC_ERR_BIT>() || + l_statusReg.getBit<ALTD_STATUS_COMMAND_ERR_BIT>() || + l_statusReg.getBit<ALTD_STATUS_ADDRESS_ERR_BIT>() || + l_statusReg.getBit<ALTD_STATUS_PB_OP_HANG_ERR_BIT>() || + l_statusReg.getBit<ALTD_STATUS_PB_DATA_HANG_ERR_BIT>() || + l_statusReg.getBit<ALTD_STATUS_PBINIT_MISSING_BIT>() || + l_statusReg.getBit<ALTD_STATUS_ECC_CE_BIT>() || + l_statusReg.getBit<ALTD_STATUS_ECC_UE_BIT>() || + l_statusReg.getBit<ALTD_STATUS_ECC_SUE_BIT>() + ); + + // If Address only operation, do not check for ALTD_STATUS_DATA_DONE_BIT + if ( i_addressOnlyOper == false ) + { + l_statusError |= !l_statusReg.getBit<ALTD_STATUS_DATA_DONE_BIT>(); + } + + if (!l_statusError) + { + break; + } + + FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY, + PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY), + "fapiDelay error"); + } + + // If error, display trace + if (l_statusError) + { + FAPI_ERR("Status mismatch detected"); + + FAPI_ERR("FBC_ALTD_BUSY = %d", (o_busyBitStatus ? 1 : 0)); + FAPI_ERR("ALTD_STATUS_REG = %016llX", l_statusReg); + } + + FAPI_ASSERT( (l_statusError == false), fapi2::P9_ADU_STATUS_REG_ERR() + .set_TARGET(i_target) + .set_STATUSREG(l_statusReg), + "Status Register check error"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_adu_coherent_clear_autoinc( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> altd_cmd_reg_data; + + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), + "Error reading from ALTD_CMD Register"); + + altd_cmd_reg_data.clearBit<ALTD_CMD_AUTO_INC_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), + "Error clearing the auto_inc bit from the ALTD_CMD Register"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_adu_coherent_manage_lock(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const bool i_lock_pick, + const bool i_lock, + const uint32_t i_num_attempts) + { + FAPI_DBG("Start"); + + fapi2::ReturnCode rc; + fapi2::buffer<uint64_t> lock_control(0x0); + uint32_t attempt_count = 1; + bool lock_pick_first_time = true; + + // validate input parameters + if (i_num_attempts == 0) + { + FAPI_ERR("Invalid value %d for number of lock manipulation attempts", + i_num_attempts); + } + + // set up data buffer to perform desired lock manipulation operation + if (i_lock) + { + FAPI_DBG("Configuring lock manipulation control data buffer to perform lock acquisition"); + lock_control.setBit(ALTD_CMD_LOCK_BIT); + } + else + { + FAPI_DBG("Configuring lock manipulation control data buffer to perform lock release"); + } + + // try to lock/unlock the lock the number of times specified with i_num_attempts + while (1) + { + // write ADU command register to attempt lock manipulation + FAPI_DBG("Writing ADU Command register to attempt lock manipulation"); + rc = fapi2::putScom(i_target, PU_ALTD_CMD_REG, lock_control); + + // pass back return code to caller unless it specifically indicates + // that the ADU lock manipulation was unsuccessful and we're going + // to try again + if ((rc != fapi2::FAPI2_RC_PLAT_ERR_ADU_LOCKED) + || (attempt_count == i_num_attempts)) + { + // rc does not indicate success + if (rc) + { + // rc does not indicate lock held, exit + if (rc != fapi2::FAPI2_RC_PLAT_ERR_ADU_LOCKED) + { + FAPI_ERR("fapiPutScom error (PU_ALTD_CMD_REG)"); + break; + } + + // rc indicates lock held, out of attempts + if (attempt_count == i_num_attempts) + { + //if out of attempts but lock pick is desired try to pick the lock once and see if it works + if (i_lock_pick && i_lock && lock_pick_first_time) + { + lock_control.setBit(ALTD_CMD_LOCK_PICK_BIT); + attempt_count--; + lock_pick_first_time = false; + FAPI_DBG("Trying to do a lock pick as desired"); + } + else + { + FAPI_ERR("Desired ADU lock manipulation was not successful after %d attempts", + i_num_attempts); + break; + } + } + } + + // rc clean, lock management operation successful + FAPI_DBG("Lock manipulation successful or going to try a lock pick"); + break; + } + + // delay to provide time for ADU lock to be released + FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY, + PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY), + "fapiDelay error"); + + // increment attempt count, loop again + attempt_count++; + FAPI_DBG("Attempt %d of %d", attempt_count, + i_num_attempts); + } + + fapi_try_exit: + + //if there is an error from trying to lock/unlock + if(rc) + { + fapi2::current_err = rc; + } + + FAPI_DBG("End"); + return fapi2::current_err; + + } + +} // extern "C diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H new file mode 100644 index 00000000..667e3f6b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H @@ -0,0 +1,666 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +// *! +/// @file p9_adu_coherent_utils.H +/// @brief Common Code to support ADU get/putmem procedures (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: +// --------------------------------------------------------------------------------- +// *! ADDITIONAL COMMENTS : +// *! +// *! +//----------------------------------------------------------------------------------- + +#ifndef _P9_ADU_COHERENT_UTILS_H_ +#define _P9_ADU_COHERENT_UTILS_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +#include <fapi2.H> +#include <p9_adu_constants.H> + +// Definitions of how to handle Busy state of the ADU when +// checking its status. +enum adu_status_busy_handler +{ + EXPECTED_BUSY_BIT_CLEAR = 0, // Expect to be clear, error if not + EXPECTED_BUSY_BIT_SET = 1, // Expect to be set, error if not + EXIT_ON_BUSY = 2 // Return Busy status without checking + // any other errors. +}; + +extern"C" +{ + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------- +// Classes +//----------------------------------------------------------------------------------- +/// +/// @brief Manage ADU operation flag that is used to program the +// ADU CMD register, PU_ALTD_CMD_REG (Addr: 0x00090001) +/// + class p9_ADU_oper_flag + { + public: + + // Type of ADU operations + enum OperationType_t + { + CACHE_INHIBIT = 0, + DMA_PARTIAL = 1, + PB_OPER = 2, + PMISC_OPER = 3 + }; + + // Transaction size + enum Transaction_size_t + { + TSIZE_1 = 1, + TSIZE_2 = 2, + TSIZE_4 = 4, + TSIZE_8 = 8 + }; + + // Constructor + inline p9_ADU_oper_flag() + : iv_operType(CACHE_INHIBIT), iv_autoInc(false), iv_lockPick(false), + iv_numLockAttempts(1), iv_cleanUp(true), iv_fastMode(false), + iv_itag(false), iv_ecc(false), iv_eccItagOverwrite(false), + iv_transSize(TSIZE_1) + { + } + + /// + /// @brief Set the ADU operation type + /// + /// @param[in] i_type ADU operation type + /// + /// @return void. + /// + inline void setOperationType(const OperationType_t i_type) + { + iv_operType = i_type; + return; + } + + /// + /// @brief Get the ADU operation type setting. + /// + /// @return iv_operType. + /// + inline const OperationType_t getOperationType(void) + { + return iv_operType; + } + + /// @brief Set the Auto Increment option, for CI/DMA operations only. + /// + /// @param[in] i_value True: Enable auto inc; False: Disable + /// + /// @return void. + /// + inline void setAutoIncrement(bool i_value) + { + if ( (iv_operType != CACHE_INHIBIT) && + (iv_operType != DMA_PARTIAL) ) + { + FAPI_ERR("WARNING: Set AUTOINC for non CI/DMA operation, Operation type 0x%.8X", + iv_operType); + } + + iv_autoInc = i_value; + return; + } + + /// @brief Get the Auto Increment setting, for CI/DMA operations only. + /// + /// @return iv_autoInc. + /// + inline const bool getAutoIncrement(void) + { + if ( (iv_operType != CACHE_INHIBIT) && + (iv_operType != DMA_PARTIAL) ) + { + FAPI_ERR("WARNING: AUTOINC value is invalid for non CI/DMA operation, Operation type 0x%.8X", + iv_operType); + } + + return iv_autoInc; + } + + /// + /// @brief Set ADU lock control + /// + /// @param[in] i_value True: Attempt lock ADU before operation + /// False: No lock attempt + /// + /// @return void + /// + inline void setLockControl(bool i_value) + { + iv_lockPick = i_value; + return; + } + + /// + /// @brief Get the ADU lock control setting. + /// + /// @return iv_lockPick. + /// + inline const bool getLockControl(void) + { + return iv_lockPick; + } + + /// + /// @brief Set number of lock attempts + /// + /// @param[in] i_value Num of lock attempts to try. If still can't lock + /// ADU, return an error. + /// + /// @return void + /// + inline void setNumLockAttempts(uint8_t i_value) + { + iv_numLockAttempts = i_value; + return; + } + + /// + /// @brief Get number of lock attempts setting. + /// + /// @return iv_numLockAttempts. + /// + inline const uint8_t getNumLockAttempts(void) + { + return iv_numLockAttempts; + } + + /// + /// @brief Clean up if operation fails + /// + /// @param[in] i_value True: Clean up and release lock if oper fails. + /// False: Leave ADU in fail state. + /// + /// @return void. + /// + inline void setOperFailCleanup(bool i_value) + { + iv_cleanUp = i_value; + return; + } + + /// + /// @brief Get the clean up for failed operation setting. + /// + /// @return iv_cleanUp. + /// + inline const bool getOperFailCleanup(void) + { + return iv_cleanUp; + } + + /// + /// @brief Set fast read/write mode. + /// For fast read/write mode, no status check. Otherwise, + /// do status check after every read/write. + /// + /// @param[in] i_value True: Enable fast read/write mode. + /// False: Disable fast read/write mode. + /// + /// @return void. + /// + inline void setFastMode(bool i_value) + { + iv_fastMode = i_value; + return; + } + + /// + /// @brief Get the Fast mode setting. + /// + /// @return iv_fastMode. + /// + inline const bool getFastMode(void) + { + return iv_fastMode; + } + + /// + /// @brief Set itag collection mode. + /// Collect/set itag with each 8B read/write + /// For a write only set if itag data should be 1 + /// + /// @param[in] i_value True: Collect itag + /// False: Don't collect itag. + /// + /// @return void. + /// + inline void setItagMode(bool i_value) + { + iv_itag = i_value; + return; + } + + /// + /// @brief the ITAG collection mode. + /// + /// @return iv_itag. + /// + inline const bool getItagMode(void) + { + return iv_itag; + } + + /// + /// @brief Set Ecc mode. + /// Collect/set ecc with each 8B read/write + /// + /// @param[in] i_value True: Collect ECC + /// False: Don't collect ECC. + /// + /// @return void. + /// + inline void setEccMode(bool i_value) + { + iv_ecc = i_value; + return; + } + + /// + /// @brief Get the Ecc mode setting. + /// + /// @return iv_ecc. + /// + inline const bool getEccMode(void) + { + return iv_ecc; + } + + /// + /// @brief Overwrite ECC/ITAG data mode. + /// + /// @param[in] i_value Overwrite ECC + /// False: Don't overwrite ECC + /// + /// @return void. + /// + inline void setEccItagOverrideMode(bool i_value) + { + iv_eccItagOverwrite = i_value; + return; + } + + /// + /// @brief Get the Overwrite ECC/ITAG data mode. + /// + /// @return iv_eccItagOverwrite. + /// + inline const bool getEccItagOverrideMode(void) + { + return iv_eccItagOverwrite; + } + + /// + /// @brief Set transaction size + /// + /// @param[in] i_value Transaction size + /// + /// @return void. + /// + inline void setTransactionSize(Transaction_size_t i_value) + { + iv_transSize = i_value; + return; + } + + /// + /// @brief Get the transaction size + /// + /// @return iv_transSize. + /// + inline const Transaction_size_t getTransactionSize(void) + { + return iv_transSize; + } + + /// + /// @brief Assemble the 32-bit ADU flag based on current + /// info contained in this class. + /// This flag is to be used in ADU interface call + /// See flag bit definitions in p9_adu_constants.H + /// + /// @return uint32_t + /// + inline uint32_t setFlag(); + + /// + /// @brief Update the class instant variables with info + /// embedded in the passed in flag value. + /// + /// @return void. + /// + inline void getFlag(uint32_t i_flag); + + private: + + // Class variables + OperationType_t iv_operType; // Operation type + bool iv_autoInc; // Auto increment + bool iv_lockPick; // Lock ADU before operation + uint8_t iv_numLockAttempts; // Number of lock attempts + bool iv_cleanUp; + bool iv_fastMode; // Fast ADU read/write mode + bool iv_itag; // Itag mode + bool iv_ecc; // ECC mode + bool iv_eccItagOverwrite; // ECC/ITAG overwrite mode + Transaction_size_t iv_transSize; // Transaction size + }; + +/// +/// See doxygen in class definition +/// + uint32_t p9_ADU_oper_flag::setFlag() + { + uint32_t l_aduFlag = 0; + + // Operation type + l_aduFlag |= (iv_operType << FLAG_ADU_TTYPE_SHIFT); + + // Auto Inc + if (iv_autoInc == true) + { + l_aduFlag |= FLAG_AUTOINC; + } + + // Lock pick + if (iv_lockPick == true) + { + l_aduFlag |= FLAG_LOCK_PICK; + } + + // Lock attempts + l_aduFlag |= (iv_numLockAttempts << FLAG_LOCK_TRIES_SHIFT); + + // Leave dirty + if (iv_cleanUp == false) + { + l_aduFlag |= FLAG_LEAVE_DIRTY; + } + + // Fast mode + if (iv_fastMode == true) + { + l_aduFlag |= FLAG_ADU_FASTMODE; + } + + // Itag + if (iv_itag == true) + { + l_aduFlag |= FLAG_ITAG; + } + + // ECC + if (iv_ecc == true) + { + l_aduFlag |= FLAG_ECC; + } + + // Overwrite ECC + if (iv_eccItagOverwrite == true) + { + l_aduFlag |= FLAG_OVERWRITE_ECC; + } + + // Transaction size + if (iv_transSize == TSIZE_1) + { + l_aduFlag |= FLAG_SIZE_TSIZE_1; + } + else if (iv_transSize == TSIZE_2) + { + l_aduFlag |= FLAG_SIZE_TSIZE_2; + } + else if (iv_transSize == TSIZE_4) + { + l_aduFlag |= FLAG_SIZE_TSIZE_4; + } + else if (iv_transSize == TSIZE_8) + { + l_aduFlag |= FLAG_SIZE_TSIZE_8; + } + else + { + FAPI_ERR("Invalid transaction size: iv_transSize %d", iv_transSize); + } + + // Debug trace + FAPI_DBG("p9_ADU_oper_flag::setFlag()"); + FAPI_DBG(" iv_operType 0x%.8X, iv_autoInc 0x%.8X, iv_lockPick 0x%.8X, iv_numLockAttempts 0x%.8X", + iv_operType, iv_autoInc, iv_lockPick, iv_numLockAttempts); + FAPI_DBG(" iv_cleanUp 0x%.8X, iv_fastMode 0x%.8X, iv_itag 0x%.8X, iv_ecc 0x%.8X", + iv_cleanUp, iv_fastMode, iv_itag, iv_ecc); + FAPI_DBG(" iv_eccItagOverwrite 0x%.8X, iv_transSize 0x%.8X", + iv_eccItagOverwrite, iv_transSize); + FAPI_DBG(" ADU Flag value: 0x%.8X", l_aduFlag); + + return l_aduFlag; + } + +/// +/// See doxygen in class definition +/// + void p9_ADU_oper_flag::getFlag(const uint32_t i_flag) + { + // Decode Operation type + iv_operType = static_cast<OperationType_t> + ( (i_flag & FLAG_ADU_TTYPE) >> FLAG_ADU_TTYPE_SHIFT); + + // Auto Inc + iv_autoInc = (i_flag & FLAG_AUTOINC); + + // Lock pick + iv_lockPick = (i_flag & FLAG_LOCK_PICK); + + // Lock attempts + iv_numLockAttempts = ( (i_flag & FLAG_LOCK_TRIES) >> FLAG_LOCK_TRIES_SHIFT); + + // Leave dirty + iv_cleanUp = ~(i_flag & FLAG_LEAVE_DIRTY); + + // Fast mode + iv_fastMode = (i_flag & FLAG_ADU_FASTMODE); + + // Itag + iv_itag = (i_flag & FLAG_ITAG); + + // ECC + iv_ecc = (i_flag & FLAG_ECC); + + // Overwrite ECC + iv_eccItagOverwrite = (i_flag & FLAG_OVERWRITE_ECC); + + // Transaction size + if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_1 ) + { + iv_transSize = TSIZE_1; + } + else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_2 ) + { + iv_transSize = TSIZE_2; + } + else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_4 ) + { + iv_transSize = TSIZE_4; + } + else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_8 ) + { + iv_transSize = TSIZE_8; + } + else + { + FAPI_ERR("Invalid transaction size: iv_transSize %d", iv_transSize); + } + + // Debug trace + FAPI_DBG("p9_ADU_oper_flag::getFlag() - Flag value 0x%.8X", i_flag); + FAPI_DBG(" iv_operType 0x%.8X, iv_autoInc 0x%.8X, iv_lockPick 0x%.8X, iv_numLockAttempts 0x%.8X", + iv_operType, iv_autoInc, iv_lockPick, iv_numLockAttempts); + FAPI_DBG(" iv_cleanUp 0x%.8X, iv_fastMode 0x%.8X, iv_itag 0x%.8X, iv_ecc 0x%.8X", + iv_cleanUp, iv_fastMode, iv_itag, iv_ecc); + FAPI_DBG(" iv_eccItagOverwrite 0x%.8X, iv_transSize 0x%.8X", + iv_eccItagOverwrite, iv_transSize); + return; + } + +//----------------------------------------------------------------------------------- +// Function prototypes +//----------------------------------------------------------------------------------- + +/// @brief check that the address is cacheline aligned and within the fabric real address range +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => starting address for ADU operation +/// @return FAPI_RC_SUCCESS if arguments are valid + fapi2::ReturnCode p9_adu_coherent_utils_check_args( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const uint32_t i_flags); + +/// @brief ensure that fabric is initialized and stop control is not set +/// (by checkstop/mode switch), which if set would prohibit fabric +/// commands from being broadcasted +/// @param[in] i_target => P9 chip target +/// @return FAPI_RC_SUCCESS if fabric is not stopped + fapi2::ReturnCode p9_adu_coherent_utils_check_fbc_state( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target + ); + +/// @brief calculates the number of 8 byte granules that can be read/written before setup needs to be run again +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => starting address for ADU operation +/// @return number of 8 byte granules that can be read/written before setup needs to be run again + fapi2::ReturnCode p9_adu_coherent_utils_get_num_granules( + const uint64_t i_address, + uint32_t& o_numGranules); + +/// @brief does the setup for the ADU to set up the initial registers for a read/write +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => starting address for ADU operation +/// @param[in] i_rnw => whether the operation is a read or write +/// @param[in] i_flags => flags that contain information that the ADU needs to know to set up registers +/// @return FAPI_RC_SUCCESS if setting up the adu registers is a success + fapi2::ReturnCode p9_adu_coherent_setup_adu( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags); + +/// @brief does the write for the ADU +/// @param[in] i_target => P9 chip target +/// @param[in] i_firstGranule => the first 8B granule that we are writing +/// @param[in] i_address => address for this write +/// @param[in] i_aduOper => Contains information that the ADU needs to know to set up registers +/// @param[in] i_write_data => the data that is to be written to the ADU +/// @return FAPI_RC_SUCCESS if writing the ADU is a success + fapi2::ReturnCode p9_adu_coherent_adu_write( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const bool i_firstGranule, + const uint64_t i_address, + p9_ADU_oper_flag& i_aduOper, + const uint8_t i_write_data[]); + +/// @brief does the read for the ADU +/// @param[in] i_target => P9 chip target +/// @param[in] i_firstGranule => the first 8B granule that we are reading +/// @param[in] i_address => address for this read +/// @param[in] i_aduOper => Contains information that the ADU needs to know to set up registers +/// @param[out] o_read_data => the data that is read from the ADU +/// @return FAPI_RC_SUCCESS if reading the ADU is a success + fapi2::ReturnCode p9_adu_coherent_adu_read( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const bool i_firstGranule, + const uint64_t i_address, + p9_ADU_oper_flag& i_aduOper, + uint8_t o_read_data[]); + +/// @brief this does a reset for the ADU +/// @param[in] i_target => P9 chip target +/// @return FAPI_RC_SUCCESS if the reset is a success + fapi2::ReturnCode p9_adu_coherent_utils_reset_adu( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +/// @brief this does any cleanup for the ADU after all reads/writes have been done +/// @param[in] i_target => P9 chip target +/// @return FAPI_RC_SUCCESS if cleaning up the ADU is a success + fapi2::ReturnCode p9_adu_coherent_cleanup_adu( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +/// @brief this will remove the auto increment bit before the last iteration +/// @param[in] i_target => P9 chip target +/// @return FAPI_RC_SUCCESS if removing the auto inc bit is a success + fapi2::ReturnCode p9_adu_coherent_clear_autoinc( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +/// @brief This function checks the status of the adu. +/// If ADU is busy, it will handle +/// +/// @param[in] i_target P9 chip target +/// @param[in] i_busyBitHandler Instruction on how to handle the ADU busy +/// @param[in] i_addressOnlyOper Indicate the check is called after an Address +/// only operation +/// @param[out] o_busyStatus ADU status busy bit. +/// +/// @return FAPI_RC_SUCCESS if the status check is a success + fapi2::ReturnCode p9_adu_coherent_status_check( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const adu_status_busy_handler i_busyBitHandler, + const bool i_addressOnlyOper, + bool& o_busyBitStatus); + +/// @brief this will acquire and release a lock as well as deal with any lock picking +/// @param[in] i_target => P9 chip target +/// @param[in] i_lock_pick => If the lock does not go through should we set a lock pick +/// @param[in] i_lock => true if this is to lock the ADU false if this is to unlock the ADU +/// @param[in] i_num_attempts => number of times to try locking the ADU + fapi2::ReturnCode p9_adu_coherent_manage_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const bool i_lock_pick, + const bool i_lock, + const uint32_t i_num_attempts); + +} // extern "C" + +#endif //_P9_ADU_COHERENT_UTILS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H new file mode 100644 index 00000000..d0449e0d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_constants.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_adu_constants.H +/// @brief Constant enums to support ADU get/putmem procedures (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWp Consumed by: SBE + +#ifndef _P9_ADU_CONSTANTS_H_ +#define _P9_ADU_CONSTANTS_H_ + +//--------------------------------------------------------------------------------------------- +// Includes +//--------------------------------------------------------------------------------------------- + +extern "C" +{ + +//---------------------------------------------------------------------------------------------- +// Constant definitions +//---------------------------------------------------------------------------------------------- + +//if the flag is more than 1 bit there will be a start and end bit for the flag +//these give the bit position that is expected for the flags + enum adu_flags + { + // Operation type + // 0b000: DMA partial + // 0b001: Cache-inhibited + // 0b010: PB op + // 0b011: PMISC op + FLAG_ADU_TTYPE = 0xE0000000ull, // Bits 0:2 + + // Utilize ADU HW auto-increment function + // 0: Don't use autoinc + // 1: Use autoinc + FLAG_AUTOINC = 0x10000000ull, // Bit 3 + + // Pick ADU lock (if required) + // 0: Don't use lock pick + // 1: Use lock pick + FLAG_LOCK_PICK = 0x08000000ull, // Bit 4 + + // In case of a fail with lock held, reset + // ADU and release lock + // 0: Reset & release + // 1: Leave dirty + FLAG_LEAVE_DIRTY = 0x04000000ull, // Bit 5 + + // Check status only at the end of read/write stream + // 0: Do status check after every read/write + // 1: Don't do status check + FLAG_ADU_FASTMODE = 0x02000000ull, // Bit 6 + + // Collect/set itag with each 8B read/write + // For a write only set if itag data should be 1 + // 0: Don't collect itag + // 1: Collect itag + FLAG_ITAG = 0x01000000ull, // Bit 7 + + // Collect/set ecc with each 8B read/write + // 0: Don't collect ecc + // 1: Collect ecc + FLAG_ECC = 0x00800000ull, // Bit 8 + + // Overwrite the ecc/itag data + // 0: Don't overwrite ECC + // 1: Overwrite ECC + FLAG_OVERWRITE_ECC = 0x00400000ull, // Bit 9 + + // Transaction size (choice is 1, 2, 4, or 8) + // 0b00: TSIZE_1 + // 0b01: TSIZE_2 + // 0b10: TSIZE_4 + // 0b11: TSIZE_8 + FLAG_SIZE = 0x00300000ull, // Bits 10:11 + + // Number of ADU lock acquisitions to attempt + // before giving up or attempting lock pick + FLAG_LOCK_TRIES = 0x000F0000, // Bit 12:15 + + // Reserved bits + FLAG_NOT_USED_BITS = 0x0000FFFF, // Bit 16:31 + }; + +// Operation type values + const uint32_t FLAG_ADU_TTYPE_DMA = 0x00000000ull; // DMA partial + const uint32_t FLAG_ADU_TTYPE_CI = 0x20000000ull; // Cache inhibit + const uint32_t FLAG_ADU_TTYPE_PB = 0x40000000ull; // PB operation + const uint32_t FLAG_ADU_TTYPE_PMISC = 0x60000000ull; // Switch operation + +// Flag size values + const uint32_t FLAG_SIZE_TSIZE_1 = 0x00000000ull; + const uint32_t FLAG_SIZE_TSIZE_2 = 0x00100000ull; + const uint32_t FLAG_SIZE_TSIZE_4 = 0x00200000ull; + const uint32_t FLAG_SIZE_TSIZE_8 = 0x00300000ull; + +// Shift positions + const uint64_t FLAG_ADU_TTYPE_SHIFT = 29; + const uint64_t FLAG_LOCK_TRIES_SHIFT = 16; + const uint64_t FLAG_ADU_SIZE_SHIFT = 20; + +} //extern "C" + +#endif //_P9_ADU_CONSTANTS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C new file mode 100644 index 00000000..e270772a --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C @@ -0,0 +1,112 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//-------------------------------------------------------------------------- +// +/// @file p9_adu_setup.C +/// @brief Setup the registers for a read/write to the ADU +// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// +//-------------------------------------------------------------------------- + +//-------------------------------------------------------------------------- +// Includes +//-------------------------------------------------------------------------- +#include <p9_adu_setup.H> +#include <p9_adu_coherent_utils.H> + +extern "C" +{ + +//-------------------------------------------------------------------------- +// HWP entry point +//-------------------------------------------------------------------------- + fapi2::ReturnCode p9_adu_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> + & i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + uint32_t& o_numGranules) + { + //return code + uint32_t num_attempts = 1; + bool lock_pick = false; + + // mark HWP entry + FAPI_DBG("Entering ...\n"); + + //ADU status/control information + bool adu_is_dirty = false; + bool adu_leave_dirty = i_flags & FLAG_LEAVE_DIRTY; + + //check arguments + FAPI_TRY(p9_adu_coherent_utils_check_args(i_target, i_address, i_flags), + "Error from p9_adu_coherent_utils_check_args"); + + //ensure fabric is running + FAPI_TRY(p9_adu_coherent_utils_check_fbc_state(i_target), + "Error from p9_adu_coherent_utils_check_fbc_status"); + + //reset ADU state machines and status register + FAPI_TRY(p9_adu_coherent_utils_reset_adu(i_target), "p9_adu_setup: Error from p9_adu_coherent_utils_reset_adu"); + + //acquire ADU lock to guarantee exclusive use of the ADU resources + lock_pick = i_flags & FLAG_LOCK_PICK; + num_attempts = i_flags & FLAG_LOCK_TRIES; + FAPI_TRY(p9_adu_coherent_manage_lock(i_target, lock_pick, true, num_attempts), + "Error from p9_adu_coherent_manage_lock"); + + //figure out how many granules can be requested before setup needs to be run again + FAPI_TRY(p9_adu_coherent_utils_get_num_granules(i_address, o_numGranules), + "Error from p9_adu_coherent_utils_get_num_granules"); + + //Set dirty since we need to attempt to cleanup/release the lock so the ADU is not in a locked state if operation fails from this point + adu_is_dirty = true; + + //setup the ADU registers for the read/write + FAPI_TRY(p9_adu_coherent_setup_adu(i_target, i_address, i_rnw, i_flags), + "Error from p9_adu_coherent_setup_registers"); + + fapi_try_exit: + fapi2::ReturnCode saveError = fapi2::current_err; + + //if an error has occurred, ADU is dirty, and instructed to clean up, + //attempt to reset ADU and free lock (propogate rc of original fail) + if (fapi2::current_err && adu_is_dirty && !adu_leave_dirty) + { + (void) p9_adu_coherent_utils_reset_adu(i_target); + (void) p9_adu_coherent_manage_lock(i_target, false, false, num_attempts); + } + + FAPI_DBG("Exiting..."); + return saveError; + } + +} // extern "C" + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H new file mode 100644 index 00000000..ffdd38b0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H @@ -0,0 +1,99 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9_adu_setup.H +/// @brief Setup the adu to do reads/writes +// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 1 +// *HWP Consumed by: +//----------------------------------------------------------------------------------- +// *! ADDITIONAL COMMENTS: +// *! +// *! The purpose of this procedure is to setup the ADU to do reads/writes +// *! and to return the number of granules (number of 8B reads/writes) that +// *! can be done before setup needs to be called again +// *! +// *! Successful operation assumes that: +// *! +// *! High-level procedure flow: +// *! +// *! +//------------------------------------------------------------------------------------ + +#ifndef _P9_ADU_SETUP_H_ +#define _P9_ADU_SETUP_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +#include <fapi2.H> +#include <p9_adu_constants.H> + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode +(*p9_adu_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const uint64_t, + const bool, + const uint32_t, + uint32_t&); + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +extern "C" { + +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- + +/// @brief setup for reads/writes from the ADU +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => base real address for read/write operation (expected to be 8B aligned) +/// @param[in] i_rnw => if the operation is read not write (1 for read, 0 for write) +/// @param[in] i_flags => other information that is needed - see the p9_adu_constants adu_flags enums for bit definitions +/// Note: To construct the flag you can use p9_ADU_oper_flag class +/// @param[out] o_numGranules => number of 8B granules that can be read/written before setup needs to be called again +// +/// @return FAPI_RC_SUCCESS if the setup completes successfully, +// + fapi2::ReturnCode p9_adu_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + uint32_t& o_numGranules); +} //extern "C" + +#endif //_P9_ADU_SETUP_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C new file mode 100644 index 00000000..4c9e3a12 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -0,0 +1,264 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_fbc_utils.C +/// @brief Fabric library functions/constants (FAPI2) +/// +/// The functions in this file provide: +/// - Information about the instantaneous state of the fabric +/// - Means to restart the fabric after a checkstop condition +/// - Determination of the chip's base address in the real address map +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// @author Christy Graves <clgraves@us.ibm.com> +/// + +// +// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE,HB,FSP +// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p9_fbc_utils.H> +#include <p9_misc_scom_addresses.H> + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// ADU PMisc Register field/bit definitions +const uint32_t ALTD_SND_MODE_DISABLE_CHECKSTOP_BIT = 19; +const uint32_t ALTD_SND_MODE_MANUAL_CLR_PB_STOP_BIT = 21; +const uint32_t ALTD_SND_MODE_PB_STOP_BIT = 22; + +// FBC Mode Register field/bit definitions +const uint32_t PU_FBC_MODE_PB_INITIALIZED_BIT = 0; + +// FBC base address determination constants +// system ID (large system) +const uint8_t FABRIC_ADDR_LS_SYSTEM_ID_START_BIT = 8; +const uint8_t FABRIC_ADDR_LS_SYSTEM_ID_END_BIT = 12; +// system ID (small system) +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_START_BIT = 8; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_END_BIT = 12; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_SHIFT = 5; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_MASK = 0x1F; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_START_BIT = 15; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_END_BIT = 16; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_SHIFT = 3; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_MASK = 0x3; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_START_BIT = 19; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_END_BIT = 21; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_SHIFT = 0; +const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_MASK = 0x7; +// group ID (large system) +const uint8_t FABRIC_ADDR_LS_GROUP_ID_START_BIT = 15; +const uint8_t FABRIC_ADDR_LS_GROUP_ID_END_BIT = 18; +// group ID (small system) +const uint8_t FABRIC_ADDR_SS_GROUP_ID_START_BIT = 17; +const uint8_t FABRIC_ADDR_SS_GROUP_ID_END_BIT = 18; +// chip ID (large system) +const uint8_t FABRIC_ADDR_LS_CHIP_ID_START_BIT = 19; +const uint8_t FABRIC_ADDR_LS_CHIP_ID_END_BIT = 21; +// msel bits (large & small system) +const uint8_t FABRIC_ADDR_MSEL_START_BIT = 13; +const uint8_t FABRIC_ADDR_MSEL_END_BIT = 14; + + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +fapi2::ReturnCode p9_fbc_utils_get_fbc_state( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + bool& o_is_initialized, + bool& o_is_running) +{ + FAPI_DBG("Start"); + + // TODO: HW328175 + // fapi2::buffer<uint64_t> l_fbc_mode_data; + // FAPI_TRY(fapi2::getScom(i_target, PU_FBC_MODE_REG, l_fbc_mode_data), + // "Error reading FBC Mode Register"); + // // fabric is initialized if PB_INITIALIZED bit is one/set + // o_is_initialized = l_fbc_mode_data.getBit<PU_FBC_MODE_PB_INITIALIZED_BIT>(); + + // currently, sampling FBC init from PB Mode register is unreliable + // as init can drop perodically at runtime (based on legacy sleep backoff) + // until this issue is fixed, just return true to caller + o_is_initialized = true; + + // read ADU PMisc Mode Register state + fapi2::buffer<uint64_t> l_pmisc_mode_data; + FAPI_TRY(fapi2::getScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data), + "Error reading ADU PMisc Mode register"); + + // fabric is running if FBC_STOP bit is zero/clear + o_is_running = !(l_pmisc_mode_data.getBit<ALTD_SND_MODE_PB_STOP_BIT>()); + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} + + +fapi2::ReturnCode p9_fbc_utils_override_fbc_stop( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + FAPI_DBG("Start"); + + // read ADU PMisc Mode Register state + fapi2::buffer<uint64_t> l_pmisc_mode_data; + FAPI_TRY(fapi2::getScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data), + "Error reading ADU PMisc Mode register"); + + // set bit to disable checkstop forwarding and write back + l_pmisc_mode_data.setBit<ALTD_SND_MODE_DISABLE_CHECKSTOP_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data), + "Error writing ADU PMisc Mode register to disable checkstop forwarding to FBC"); + + // set bit to manually clear stop control and write back + l_pmisc_mode_data.setBit<ALTD_SND_MODE_MANUAL_CLR_PB_STOP_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data), + "Error writing ADU PMisc Mode register to manually clear FBC stop control"); + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} + + +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + uint64_t& o_base_address_nm0, + uint64_t& o_base_address_nm1, + uint64_t& o_base_address_m, + uint64_t& o_base_address_mmio) +{ + uint32_t l_fabric_system_id; + uint8_t l_fabric_group_id; + uint8_t l_fabric_chip_id; + uint8_t l_fabric_addr_bar_mode; + uint8_t l_mirror_policy; + fapi2::buffer<uint64_t> l_base_address; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + + + FAPI_DBG("Start"); + + // retreive attributes which statically determine chip's position in memory map + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fabric_system_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_SYSTEM_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_GROUP_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fabric_chip_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP_ID)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, FAPI_SYSTEM, l_fabric_addr_bar_mode), + "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy), + "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)"); + + // apply system ID + // occupies one field for large system map, split into three fields for small system map + if (l_fabric_addr_bar_mode == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM) + { + l_base_address.insertFromRight < FABRIC_ADDR_LS_SYSTEM_ID_START_BIT, + (FABRIC_ADDR_LS_SYSTEM_ID_END_BIT - FABRIC_ADDR_LS_SYSTEM_ID_START_BIT + 1) > (l_fabric_system_id); + } + else + { + uint32_t l_fabric_system_id_fld = (l_fabric_system_id >> FABRIC_ADDR_SS_SYSTEM_ID_FLD0_SHIFT) & + FABRIC_ADDR_SS_SYSTEM_ID_FLD0_MASK; + l_base_address.insertFromRight < FABRIC_ADDR_SS_SYSTEM_ID_FLD0_START_BIT, + (FABRIC_ADDR_SS_SYSTEM_ID_FLD0_END_BIT - FABRIC_ADDR_SS_SYSTEM_ID_FLD0_START_BIT + 1) > (l_fabric_system_id_fld); + + l_fabric_system_id_fld = (l_fabric_system_id >> FABRIC_ADDR_SS_SYSTEM_ID_FLD1_SHIFT) & + FABRIC_ADDR_SS_SYSTEM_ID_FLD1_MASK; + l_base_address.insertFromRight < FABRIC_ADDR_SS_SYSTEM_ID_FLD1_START_BIT, + (FABRIC_ADDR_SS_SYSTEM_ID_FLD1_END_BIT - FABRIC_ADDR_SS_SYSTEM_ID_FLD1_START_BIT + 1) > (l_fabric_system_id_fld); + + l_fabric_system_id_fld = (l_fabric_system_id >> FABRIC_ADDR_SS_SYSTEM_ID_FLD2_SHIFT) & + FABRIC_ADDR_SS_SYSTEM_ID_FLD2_MASK; + l_base_address.insertFromRight < FABRIC_ADDR_SS_SYSTEM_ID_FLD2_START_BIT, + (FABRIC_ADDR_SS_SYSTEM_ID_FLD2_END_BIT - FABRIC_ADDR_SS_SYSTEM_ID_FLD2_START_BIT + 1) > (l_fabric_system_id_fld); + } + + // apply group ID + if (l_fabric_addr_bar_mode == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM) + { + l_base_address.insertFromRight < FABRIC_ADDR_LS_GROUP_ID_START_BIT, + (FABRIC_ADDR_LS_GROUP_ID_END_BIT - FABRIC_ADDR_LS_GROUP_ID_START_BIT + 1) > (l_fabric_group_id); + } + else + { + l_base_address.insertFromRight < FABRIC_ADDR_SS_GROUP_ID_START_BIT, + (FABRIC_ADDR_SS_GROUP_ID_END_BIT - FABRIC_ADDR_SS_GROUP_ID_START_BIT + 1) > (l_fabric_group_id); + } + + // apply chip ID (relevant for large system map only) + if (l_fabric_addr_bar_mode == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM) + { + l_base_address.insertFromRight < FABRIC_ADDR_LS_CHIP_ID_START_BIT, + (FABRIC_ADDR_LS_CHIP_ID_END_BIT - FABRIC_ADDR_LS_CHIP_ID_START_BIT + 1) > (l_fabric_chip_id); + } + + // set output addresses based on application of msel + if (l_mirror_policy == fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) + { + // nm = 0b00/01, m = 0b10, mmio = 0b11 + o_base_address_nm0 = l_base_address(); // 00 + l_base_address.setBit<FABRIC_ADDR_MSEL_END_BIT>(); + o_base_address_nm1 = l_base_address(); // 01 + l_base_address.setBit<FABRIC_ADDR_MSEL_START_BIT>(); + l_base_address.clearBit<FABRIC_ADDR_MSEL_END_BIT>(); + o_base_address_m = l_base_address(); // 10 + l_base_address.setBit(FABRIC_ADDR_MSEL_END_BIT); + o_base_address_mmio = l_base_address(); // 11 + } + else + { + // nm = 0b01/10, m = 0b00, mmio = 0b11 + o_base_address_m = l_base_address(); // 00 + l_base_address.setBit<FABRIC_ADDR_MSEL_END_BIT>(); + o_base_address_nm0 = l_base_address(); // 01 + l_base_address.setBit<FABRIC_ADDR_MSEL_START_BIT>(); + l_base_address.clearBit<FABRIC_ADDR_MSEL_END_BIT>(); + o_base_address_nm1 = l_base_address(); // 10 + l_base_address.setBit<FABRIC_ADDR_MSEL_END_BIT>(); + o_base_address_mmio = l_base_address(); // 11 + } + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H new file mode 100644 index 00000000..af73102e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -0,0 +1,108 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_fbc_utils.H +/// @brief Fabric library functions/constants (FAPI2) +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// @author Christy Graves <clgraves@us.ibm.com> +/// + +// +// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE,HB,FSP +// + +#ifndef _P9_FBC_UTILS_H_ +#define _P9_FBC_UTILS_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// address range definitions +const uint64_t P9_FBC_UTILS_FBC_MAX_ADDRESS = ((1ULL << 56) - 1ULL); +const uint64_t P9_FBC_UTILS_CACHELINE_MASK = 0x7FULL; +const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL; + +// cacheline size = 128B +const uint64_t FABRIC_CACHELINE_SIZE = 0x80; + + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +/// +/// @brief Read FBC/ADU registers to determine state of fabric init and stop +/// control signals +/// +/// @param[in] i_target Reference to processor chip target +/// @param[out] o_is_initialized State of fabric init signal +/// @param[out] o_is_running State of fabric pervasive stop control +/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9_fbc_utils_get_fbc_state( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + bool& o_is_initialized, + bool& o_is_running); + +/// +/// @brief Use ADU pMisc Mode register to clear fabric stop signal, overriding +/// a stop condition caused by a checkstop +/// +/// @param[in] i_target Reference to processor chip target +/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9_fbc_utils_override_fbc_stop( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +/// +/// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip +/// +/// @param[in] i_target Reference to processor chip target +/// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip +/// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip +/// @param[out] o_base_address_m Mirrored base address for this chip +/// @param[out] o_base_address_mmio MMIO base address for this chip +/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + uint64_t& o_base_address_nm0, + uint64_t& o_base_address_nm1, + uint64_t& o_base_address_m, + uint64_t& o_base_address_mmio); + + +#endif // _P9_FBC_UTILS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C new file mode 100644 index 00000000..5a3970b3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C @@ -0,0 +1,117 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_access.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//-------------------------------------------------------------------------- +// +/// @file p9_pba_access.C +/// @brief Read coherent state of memory via the PBA (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +//-------------------------------------------------------------------------- + + +//-------------------------------------------------------------------------- +// Includes +//-------------------------------------------------------------------------- +#include <p9_pba_setup.H> +#include <p9_pba_coherent_utils.H> + +extern "C" { + +//-------------------------------------------------------------------------- +// HWP entry point +//-------------------------------------------------------------------------- + fapi2::ReturnCode p9_pba_access(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + const bool i_firstGranule, + const bool i_lastGranule, + uint8_t io_data[]) + { + //return codes + fapi2::ReturnCode rc; + fapi2::ReturnCode rc1; + + // mark HWP entry + FAPI_DBG("Entering ...\n"); + + // Process input flag + p9_PBA_oper_flag l_myPbaFlag; + l_myPbaFlag.getFlag(i_flags); + + //if read + if (i_rnw) + { + rc1 = p9_pba_coherent_pba_read(i_target, i_address, io_data); + } + //else if write + else + { + rc1 = p9_pba_coherent_pba_write(i_target, i_address, io_data); + } + + //If we are not in fastmode or this is the last granule, we want to check the status + if (!rc1) + { + if ( i_lastGranule || (l_myPbaFlag.getFastMode() == false) ) + { + rc1 = p9_pba_coherent_status_check(i_target); + + if (i_lastGranule) + { + //Clean up the PBA since it's the last read/write and it has been finished + FAPI_TRY(p9_pba_coherent_cleanup_pba(i_target), + "Error doing p9_pba_coherent_cleanup_pba"); + } + } + } + + // mark HWP exit + fapi_try_exit: + + //Handling error. PBA access is the main error if there's one. + if (rc1) + { + //Commit error from clean up (secondary) + if (rc) + { + //fapi2::fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + } + + //Set return error to pba access error + fapi2::current_err = rc1; + } + + FAPI_DBG("Exit ...\n"); + return fapi2::current_err; + } + +} // extern "C" + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.H new file mode 100644 index 00000000..7e02c926 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.H @@ -0,0 +1,104 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_access.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +// +/// @file p9_pba_access.H +/// @brief Read coherent state of memory via the PBA (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// ---------------------------------------------------------------------------------- +// +// *! ADDITIONAL COMMENTS : +// *! +// *! The purpose of this procedure is to perform a coherent read or write from system +// *! memory via fabric commands issued from the PBA. +// *! +// *! Succcessful operation assumes that: +// *! o System clocks are running +// *! o Fabric is initalized +// *! +// *! +//----------------------------------------------------------------------------------- + +#ifndef _P9_PBA_ACCESS_H_ +#define _P9_PBA_ACCESS_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +#include <fapi2.H> +#include <p9_pba_constants.H> +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode +(*p9_pba_access_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const uint64_t, + const bool, + const uint32_t, + const bool, + const bool, + uint8_t[]); + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +extern "C" { + +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- + +/// @brief setup for reads/writes from the PBA +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => base real address for read/write operation (expected to be 128B aligned) +/// @param[in] i_rnw => if the operation is read not write (1 for read, 0 for write) +/// @param[in] i_flags => other information that is needed - see the p9_pba_constants pba_flags enums for bit definitions +/// Note: to construct the flag you can use the p9_PBA_oper_flag class +/// @param[in] i_lastGranule => is this the last granule that is to be read/written +/// @param[in] i_firstGranule => first granule that is to be read/written NOT USED FOR PBA +/// @param[in, out] io_data => The data that is read/written +/// @return FAPI_RC_SUCCESS if the setup completes successfully, + + fapi2::ReturnCode p9_pba_access( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + const bool i_firstGranule, + const bool i_lastGranule, + uint8_t io_data[]); +} //extern "C" + +#endif //_P9_PBA_ACCESS_H_ + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C new file mode 100644 index 00000000..c4f32d8c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C @@ -0,0 +1,491 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +// +/// @file p9_pba_coherent_utils.C +/// @brief PBA alter/display library functions (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// +//----------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_pba_coherent_utils.H> +#include <p9_misc_scom_addresses.H> +#include <p9_quad_scom_addresses.H> +#include <p9_fbc_utils.H> + +extern "C" +{ + //--------------------------------------------------------------------------------- + // Constant definitions + //--------------------------------------------------------------------------------- + + //PBA Delay Constants + const uint32_t PBA_SLVRST_DELAY_HW_NS = 1000; + const uint32_t PBA_SLVRST_DELAY_SIM_CYCLES = 200; + const uint32_t WRITE_DELAY_HW_NS = 100; + const uint32_t WRITE_DELAY_SIM_CYCLES = 20; + const uint32_t PBA_BAR_SCOPE_LOCAL_NODE = 0; + +//PBA Slave Control register field/bit definitions + const uint32_t PBA_SLVCTL_ENABLE_BIT = 0; + const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_START_BIT = 1; + const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_END_BIT = 3; + const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT = 5; + const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_END_BIT = 7; + const uint32_t PBA_SLVCTL_WRITE_TTYPE_START_BIT = 8; + const uint32_t PBA_SLVCTL_WRITE_TTYPE_END_BIT = 10; + const uint32_t PBA_SLVCTL_READ_TTYPE_BIT = 15; + const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT = 16; + const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_END_BIT = 17; + const uint32_t PBA_SLVCTL_READ_BUF_INVALIDATE_CTL_BIT = 18; + const uint32_t PBA_SLVCTL_WRITE_BUF_PAIR_ALLOCATION_BIT = 19; + const uint32_t PBA_SLVCTL_READ_BUF_PAIR_A_ALLOCATION_BIT = 20; + const uint32_t PBA_SLVCTL_READ_BUF_PAIR_B_ALLOCATION_BIT = 21; + const uint32_t PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT = 22; + const uint32_t PBA_SLVCTL_DISABLE_WRITE_GATHER_BIT = 24; + const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT = 25; + const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_END_BIT = 27; + const uint32_t PBA_SLVCTL_WRITE_TSIZE_START_BIT = 28; + const uint32_t PBA_SLVCTL_WRITE_TSIZE_END_BIT = 35; + const uint32_t PBA_SLVCTL_EXT_ADDR_START_BIT = 36; + const uint32_t PBA_SLVCTL_EXT_ADDR_END_BIT = 49; + + const uint32_t PBA_SLVCTL_EXTADDR_SHIFT = 27; + const uint32_t PBA_SLVCTL_EXTADDR_MASK = 0x3fff; + +//PBA Slave Reset register field/bit definitions + const uint32_t PBA_SLVRST_SET_START_BIT = 0; + const uint32_t PBA_SLVRST_SET_END_BIT = 2; + const uint32_t PBA_SLVRST_SLVCTL0_IN_PROG = 4; + const uint32_t PBA_SLVRST_SLVCTL1_IN_PROG = 5; + const uint32_t PBA_SLVRST_SLVCTL2_IN_PROG = 6; + const uint32_t PBA_SLVRST_SLVCTL3_IN_PROG = 7; + const uint32_t PBA_SLVRST_IN_PROG_START_BIT = 4; + const uint32_t PBA_SLVRST_IN_PROG_END_BIT = 7; + const uint32_t PBA_SLVRST_BUSY_START_BIT = 8; + const uint32_t PBA_SLVRST_BUSY_END_BIT = 11; + //mask to check if there is a PBA slave rest in progress and if the PBA Slave Control is busy + //if it is not all these bits 4:11 should be set to 0 + const uint64_t PBA_SLVRST_BUSY_IN_PROG_MASK = 0xFF0000000000000ull; + +//PBA Read Buffer Valid Status field/bit definitions + const uint32_t PBA_RD_BUF_VALID_START_BIT = 33; + const uint32_t PBA_RD_BUF_VALID_END_BIT = 39; + const uint64_t PBA_RD_BUF_VALID_MASK = 0x7F000000ull; + const uint64_t PBA_RD_BUF_EMPTY = 0x1000000ull; + const uint64_t PBA_RD_BUF_VALID = 0x4000000ull; + const uint64_t PBA_RD_BUF_VALIDWFP = 0x8000000ull; + +//PBA Write Buffer Valid Status field/bit definitions + const uint32_t PBA_WR_BUF_VALID_START_BIT = 35; + const uint32_t PBA_WR_BUF_VALID_END_BIT = 39; + const uint64_t PBA_WR_BUF_VALID_MASK = 0x1F000000ull; + const uint64_t PBA_WR_BUF_EMPTY = 0x1000000ull; + +//PBA BAR register field/bit definitions + const uint32_t PBA_BAR_SCOPE_START_BIT = 0; + const uint32_t PBA_BAR_SCOPE_END_BIT = 2; + const uint32_t PBA_BAR_BASE_ADDRESS_START_BIT = 8; + const uint32_t PBA_BAR_BASE_ADDRESS_END_BIT = 43; + const uint32_t PBA_BAR_BASE_ADDRESS_SHIFT = 20; + const uint64_t PBA_BAR_BASE_ADDRESS_MASK = 0xFFFFFFFFFull; + +//PBA BAR Mask register field/bit definitions + const uint32_t PBA_BAR_MASK_START_BIT = 23; + const uint32_t PBA_BAR_MASK_END_BIT = 43; + +//OCB3_ADDRESS field/bit definitions + const uint32_t OCB3_ADDRESS_REG_ADDR_SHIFT = 32; + + //--------------------------------------------------------------------------------- + // Function definitions + //--------------------------------------------------------------------------------- + + fapi2::ReturnCode p9_pba_coherent_utils_check_args( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address) + { + + FAPI_DBG("Start"); + + //Check the address alignment + FAPI_ASSERT(!(i_address & P9_FBC_UTILS_CACHELINE_MASK), + fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( + i_address), + "Address is not cacheline aligned"); + + //Make sure the address is within the PBA bounds + FAPI_ASSERT(i_address <= P9_FBC_UTILS_FBC_MAX_ADDRESS, + fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( + i_address), + "Address exceeds supported fabric real address range"); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_pba_coherent_utils_check_fbc_state( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + bool fbc_initialized = false; + bool fbc_running = false; + FAPI_DBG("Start"); + + //Make sure the fabric is initialized and running + FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, fbc_initialized, fbc_running), + "Error from p9_fbc_utils_get_fbc_state"); + FAPI_ASSERT(fbc_initialized + && fbc_running, fapi2::P9_PBA_FBC_NOT_INITIALIZED_ERR().set_TARGET(i_target).set_INITIALIZED( + fbc_initialized).set_RUNNING( + fbc_running), "Fabric is not initialized or running"); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_pba_coherent_utils_get_num_granules( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + uint32_t& o_numGranules) + { + uint64_t oci_address_mask; + uint64_t maximumAddress; + //First set up the pba_bar_mask + fapi2::buffer<uint64_t> pba_bar_mask_data; + //Set the PBA BAR mask to allow as much of the OCI address to pass through directly as possible + //by setting bits 23:43 to 0b1. + uint64_t pba_bar_mask_attr = 0x1FFFFF00000ull; + + FAPI_DBG("Start"); + + pba_bar_mask_data.insertFromRight<0, 64>(pba_bar_mask_attr); + + //write the PBA Bar Mask Register + FAPI_TRY(fapi2::putScom(i_target, PU_PBABARMSK3, pba_bar_mask_data), + "Error writing to the PBA Bar Mask Attribute"); + + + //maximum size before we need to rerun setup - this is the number if the PBA Bar Mask is set with bits 23:43 to 0b1 + maximumAddress = 0x8000000ull; + //mask to mask away bits 37:63 of the input address + oci_address_mask = 0x7FFFFFFull; + + //subtract the oci part of the address from this maximum number and divide by 8 to get the number of bytes + //then divide by 128 to get the number of 128 bye granules that can be sent + o_numGranules = ((maximumAddress - (i_address & oci_address_mask)) / 8) / 128; + FAPI_DBG("o_numGranules = %016x", o_numGranules); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_pba_coherent_setup_pba( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags) + { + uint32_t extaddr; + uint64_t ocb3_addr_data; + uint64_t chiplet_number = 0x0ull; + fapi2::buffer<uint64_t> ocb_status_ctl_data; + fapi2::buffer<uint64_t> ocb3_addr; + fapi2::buffer<uint64_t> pba_slave_ctl_data; + fapi2::buffer<uint64_t> l3_mode_reg1; + + p9_PBA_oper_flag l_myPbaFlag; + p9_PBA_oper_flag::OperationType_t l_operType; + + FAPI_DBG("Start"); + + // Process input flag + l_myPbaFlag.getFlag(i_flags); + l_operType = l_myPbaFlag.getOperationType(); + + //Write the OCB3 Status Control Register + //Configure linear stream mode (auto-increment +8 with each data register read/write) + //set bit 4 and unset bit 5 of OCB3 Status Control Register + ocb_status_ctl_data.flush<0>().setBit<5>(); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_CLEAR, + ocb_status_ctl_data), + "Error writing to the OCB3 Status Control Register with and mask"); + ocb_status_ctl_data.flush<0>().setBit<4>(); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_OR, + ocb_status_ctl_data), + "Error writing to the OCB3 Status Control Register with or mask"); + + //Write the address to OCB3_ADDRESS Register + ocb3_addr_data = 0xB000000000000000 | ((i_address & 0x7FFFFFFull) << OCB3_ADDRESS_REG_ADDR_SHIFT); + ocb3_addr.insertFromRight<0, 64>(ocb3_addr_data); + + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBAR3, ocb3_addr), + "Error writing the OCB3_ADDRESS Register"); + + //Write the PBA Slave Control Register that controls the tsize, fastmode, etc + //set bit 0 to enable OCI Base Address Range Enabled + pba_slave_ctl_data.setBit<PBA_SLVCTL_ENABLE_BIT>(); + //set bits 1:3 to 110 for setting MasterID Match = OCB + pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_MASTER_ID_MATCH_START_BIT, + (PBA_SLVCTL_MASTER_ID_MATCH_END_BIT - PBA_SLVCTL_MASTER_ID_MATCH_START_BIT) + 1 > + (6); + //set bits 5:7 to 111 so that MasterID Care Match limits to ONLY the OCB + pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT, + (PBA_SLVCTL_MASTER_ID_CARE_MASK_END_BIT - + PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT) + 1 > (7); + + //set the write ttype bits 8:10 to whatever is in the flags + pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_TTYPE_START_BIT, + (PBA_SLVCTL_WRITE_TTYPE_END_BIT - PBA_SLVCTL_WRITE_TTYPE_START_BIT) + 1 > (l_operType); + + //it's not cache-inhibited so set bit 15 to cl_rd_nc (0) + pba_slave_ctl_data.clearBit<PBA_SLVCTL_READ_TTYPE_BIT>(); + //set bits 16:17 to No prefetch 01 TODO May need to change this later if we want to use prefetch + pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT, + (PBA_SLVCTL_READ_PREFETCH_CTL_END_BIT - PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT) + + 1 > (1); + //unset bit 18 - no auto-invalidate + pba_slave_ctl_data.clearBit<PBA_SLVCTL_READ_BUF_INVALIDATE_CTL_BIT>(); + //set bit 19 - write buffer pair allocation bit to 1 + pba_slave_ctl_data.setBit<PBA_SLVCTL_WRITE_BUF_PAIR_ALLOCATION_BIT>(); + //set bit 21 - read buffer pair b allocation bit to 1 + pba_slave_ctl_data.setBit<PBA_SLVCTL_READ_BUF_PAIR_B_ALLOCATION_BIT>(); + //unset bits 20, 22, and 23 + pba_slave_ctl_data.clearBit<PBA_SLVCTL_READ_BUF_PAIR_A_ALLOCATION_BIT>().clearBit<PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT>().clearBit<PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT>(); + //unset bit 24 to allow write gather + pba_slave_ctl_data.clearBit<PBA_SLVCTL_DISABLE_WRITE_GATHER_BIT>(); + //set bits 25:27 to 000 for write gather timeout NA + pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT, + (PBA_SLVCTL_WRITE_GATHER_TIMEOUT_END_BIT - + PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT) + 1 > (0); + + //set bits 28:35 for the tsize to 0 - when this is an lco_m write need to do the chiplet ID of the L3 cache in the form of 00cc_ccc0 + if (l_operType == p9_PBA_oper_flag::LCO && !i_rnw) + { + FAPI_TRY(fapi2::getScom(i_ex_target, EX_L3_MODE_REG1, l3_mode_reg1), "Error reading from the L3 Mode Register"); + l3_mode_reg1.extractToRight(chiplet_number, 1, 5); + } + + pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_TSIZE_START_BIT, + (PBA_SLVCTL_WRITE_TSIZE_END_BIT - PBA_SLVCTL_WRITE_TSIZE_START_BIT) + 1 > (chiplet_number); + //set bits 36:49 to the ext addr + extaddr = ((uint32_t) (i_address >> PBA_SLVCTL_EXTADDR_SHIFT)) & + PBA_SLVCTL_EXTADDR_MASK; + + pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_EXT_ADDR_START_BIT, + (PBA_SLVCTL_EXT_ADDR_END_BIT - PBA_SLVCTL_EXT_ADDR_START_BIT) + 1 > (extaddr); + + FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL3_SCOM, pba_slave_ctl_data), + "Error writing the PBA Slave Control Register"); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_pba_coherent_setup_pba_bar( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_baseAddress) + { + fapi2::buffer<uint64_t> pba_bar_data; + + FAPI_DBG("Start"); + + //Validate the input parameters + //Check the address alignment + FAPI_ASSERT(!(i_baseAddress & P9_FBC_UTILS_CACHELINE_MASK), + fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( + i_baseAddress), + "Base Address is not cacheline aligned"); + //Make sure the address is within the PBA bounds + FAPI_ASSERT(i_baseAddress <= P9_FBC_UTILS_FBC_MAX_ADDRESS, + fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS( + i_baseAddress), + "Base Address exceeds supported fabric real address range"); + + //set command scope to local node scope + pba_bar_data.insertFromRight < PBA_BAR_SCOPE_START_BIT, + (PBA_BAR_SCOPE_END_BIT - PBA_BAR_SCOPE_START_BIT) + 1 > + (PBA_BAR_SCOPE_LOCAL_NODE); + + //set base address bits 8:43 + pba_bar_data.insertFromRight < PBA_BAR_BASE_ADDRESS_START_BIT, + (PBA_BAR_BASE_ADDRESS_END_BIT - PBA_BAR_BASE_ADDRESS_START_BIT) + 1 > (( + i_baseAddress >> PBA_BAR_BASE_ADDRESS_SHIFT) & PBA_BAR_BASE_ADDRESS_MASK); + + //write the register + FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR3, pba_bar_data), + "Error writing the PBA Bar Register"); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + + } + + fapi2::ReturnCode p9_pba_coherent_pba_write( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const uint8_t i_write_data[]) + { + fapi2::ReturnCode rc; + uint64_t write_data = 0x0ull; + FAPI_DBG("Start"); + + //Perform a 128B write -- need to do 16 8B writes since it's in linear mode which can only do 8B... + for (int i = 0; i < 16; i++) + { + write_data = 0x0ull; + + for (int j = 0; j < 8; j++) + { + write_data = write_data + ((uint64_t)(i_write_data[(i * 8) + j]) << (56 - (8 * j))); + } + + fapi2::buffer<uint64_t> data(write_data); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBDR3, data), + "Error writing to the PBA via the OCB"); + } + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_pba_coherent_pba_read( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + uint8_t o_read_data[]) + { + fapi2::buffer<uint64_t> data; + + FAPI_DBG("Start"); + + //Perform a 128B read -- need to do 16 8B reads since it's in linear mode which can only do 8B... + for (int i = 0; i < 16; i++) + { + FAPI_TRY(fapi2::getScom(i_target, PU_OCB_PIB_OCBDR3, data), + "Error reading from the PBA via the OCB"); + + for (int j = 0; j < 8; j++) + { + o_read_data[(i * 8) + j] = (data >> (56 - (j * 8))) & 0xFFull;; + } + } + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_pba_coherent_cleanup_pba( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> data; + + //Clean up the PBA register by resetting PBASLVCTL3 by writing to the PBASLVRST + data.insertFromRight < PBA_SLVRST_SET_START_BIT, + (PBA_SLVRST_SET_END_BIT - PBA_SLVRST_SET_START_BIT) + 1 > (7); + FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVRST_SCOM, data), + "Error writing to the PBA Slave Reset register"); + + //Wait a little bit and make sure that the reset is no longer in progress + FAPI_TRY(fapi2::delay(PBA_SLVRST_DELAY_HW_NS, PBA_SLVRST_DELAY_SIM_CYCLES), + "Error from PBA Slave Reset delay"); + + FAPI_TRY(fapi2::getScom(i_target, PU_PBASLVRST_SCOM, data), + "Error reading from the PBA Slave Reset register"); + + FAPI_ASSERT(!data.getBit<PBA_SLVRST_SLVCTL3_IN_PROG>(), + fapi2::P9_PBA_COHERENT_UTILS_RESET_ERR().set_TARGET(i_target).set_RDDATA( + data), + "Error in resetting the PBA Slave Reset register"); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + + fapi2::ReturnCode p9_pba_coherent_status_check( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> rd_buf2_valid; + fapi2::buffer<uint64_t> rd_buf3_valid; + fapi2::buffer<uint64_t> wr_buf0_valid; + fapi2::buffer<uint64_t> wr_buf1_valid; + fapi2::buffer<uint64_t> reset_buf; + + //Check the 2 PBA Read Buffer Valid Status (2 and 3 since we set Buffer pair "B")by reading the read buffer status (bits 33:39) and making sure it's 1 + FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL2, rd_buf2_valid), + "Error reading from the PBA Read Buffer Valid 2 Status Register"); + FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL3, rd_buf3_valid), + "Error reading from the PBA Read Buffer Valid 3 Status Register"); + + //Check the 2 PBA Write Buffer Valid Status by reading the write buffer status (bits 35:39) and making sure it's 1 + FAPI_TRY(fapi2::getScom(i_target, PU_PBAWBUFVAL0, wr_buf0_valid), + "Error reading from the PBA Write Buffer Valid 0 Status Register"); + FAPI_TRY(fapi2::getScom(i_target, PU_PBAWBUFVAL1, wr_buf1_valid), + "Error reading from the PBA Write Buffer Valid 1 Status Register"); + + //Check the PBA Slave Reset Register for if things are still in progress + FAPI_TRY(fapi2::getScom(i_target, PU_PBASLVRST_SCOM, reset_buf), + "Error reading from the PBA Slave Reset Register"); + + //If there are any errors in the Status registers that we got above, collect all of the data and send an error + FAPI_ASSERT((((((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY) + || ((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALID) + || ((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALIDWFP)) ) + && (((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY) + || ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALID) + || ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALIDWFP) ) + && ((wr_buf0_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY) + && ((wr_buf1_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY) + && ((reset_buf & PBA_SLVRST_BUSY_IN_PROG_MASK) == 0)), + fapi2::P9_PBA_STATUS_ERR().set_TARGET(i_target).set_RDBUF2( + rd_buf2_valid).set_RDBUF3(rd_buf3_valid).set_WRBUF0( + wr_buf0_valid).set_WRBUF1(wr_buf1_valid).set_SLVRSTDATA(reset_buf), + "Error in checking the PBA Reset, PBA Read Buffer, or PBA Write Buffer Registers"); + + fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; + } + +} //extern "C" diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H new file mode 100644 index 00000000..e4be1c65 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H @@ -0,0 +1,285 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +// *! +/// @file p9_pba_coherent_utils.H +/// @brief Common Code to support PBA get/putmem procedures (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// --------------------------------------------------------------------------------- +// *! ADDITIONAL COMMENTS : +// *! +// *! +//----------------------------------------------------------------------------------- + +#ifndef _P9_PBA_COHERENT_UTILS_H_ +#define _P9_PBA_COHERENT_UTILS_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +#include <fapi2.H> +#include <p9_pba_constants.H> + +extern "C" +{ + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------- +// Classes +//----------------------------------------------------------------------------------- + +/// +/// @brief Manage PBA operation flag that is used to program the +/// PU_PBASLVCTL3_SCOM register. +/// + class p9_PBA_oper_flag + { + public: + + // Type of PBA operations + enum OperationType_t + { + DMA = 0, + LCO = 1, + ATOMIC = 2, + INJ = 3, + CI = 4, + }; + + // Constructor + inline p9_PBA_oper_flag(): iv_operType(DMA), iv_fastMode(false) + { + } + + /// + /// @brief Set the PBA operation type + /// + /// @param[in] i_type PBA operation type + /// + /// @return void. + /// + inline void setOperationType(const OperationType_t i_type) + { + iv_operType = i_type; + return; + } + + /// + /// @brief Get the PBA operation type setting. + /// + /// @return iv_operType. + /// + inline const OperationType_t getOperationType(void) + { + return iv_operType; + } + + /// + /// @brief Set fast read/write mode. + /// For fast read/write mode, no error check until + /// last granule. + /// + /// @param[in] i_value True: Enable fast read/write mode. + /// False: Disable fast read/write mode. + /// + /// @return void. + /// + inline void setFastMode(bool i_value) + { + iv_fastMode = i_value; + return; + } + + /// + /// @brief Get the PBA operation fast mode setting. + /// + /// @return iv_fastMode. + /// + inline const bool getFastMode(void) + { + return iv_fastMode; + } + + /// + /// @brief Assemble the 32-bit PBA flag based on current + /// info contained in this class. + /// This flag is to be used in PBA interface call + /// See flag bit definitions in p9_pba_constants.H + /// + /// @return uint32_t + /// + inline uint32_t setFlag(); + + /// + /// @brief Update the PBA class instant variables with info + /// embedded in the passed in flag value. + /// + /// @return void. + /// + inline void getFlag(uint32_t i_flag); + + private: + + // Class variables + OperationType_t iv_operType; // Operation type + bool iv_fastMode; // Fast PBA read/write mode + }; + +/// +/// See doxygen in class definition +/// + uint32_t p9_PBA_oper_flag::setFlag() + { + uint32_t l_pbaFlag = 0; + + // Operation type + l_pbaFlag |= (iv_operType << FLAG_PBA_TTYPE_SHIFT); + + // Fast mode + if (iv_fastMode == true) + { + l_pbaFlag |= FLAG_PBA_FASTMODE; + } + + // Debug trace + FAPI_DBG("p9_PBA_oper_flag::setFlag()"); + FAPI_DBG(" iv_operType 0x%.8X, iv_fastMode 0x%.8X", iv_operType, iv_fastMode); + FAPI_DBG(" PBA Flag value: 0x%.8X", l_pbaFlag); + + return l_pbaFlag; + } + +/// +/// See doxygen in class definition +/// + void p9_PBA_oper_flag::getFlag(const uint32_t i_flag) + { + // Decode Operation type + iv_operType = static_cast<OperationType_t> + ( (i_flag & FLAG_PBA_TTYPE) >> FLAG_PBA_TTYPE_SHIFT); + + // Fast mode + iv_fastMode = (i_flag & FLAG_PBA_FASTMODE); + + // Debug trace + FAPI_DBG("p9_PBA_oper_flag::getFlag() - Flag value 0x%.8X", i_flag); + FAPI_DBG(" iv_operType 0x%.8X, iv_fastMode 0x%.8X", + iv_operType, iv_fastMode); + return; + } + +//----------------------------------------------------------------------------------- +// Function prototypes +//----------------------------------------------------------------------------------- + +/// @brief does the setup for the PBA to set up the initial registers for a read/write +/// @param[in] i_target => P9 chip target +/// @param[in] i_ex_target => Ex target for which L3 we are targeting +/// @param[in] i_address => starting address for PBA operation +/// @param[in] i_rnw => whether the operation is a read or write +/// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers +/// @return FAPI_RC_SUCCESS if setting up the pba registers is a success + fapi2::ReturnCode p9_pba_coherent_setup_pba( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags); + +/// @brief does the write for the PBA +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => address for this write +/// @param[in] i_write_data => the data that is to be written to the PBA +/// @return FAPI_RC_SUCCESS if writing the PBA is a success + fapi2::ReturnCode p9_pba_coherent_pba_write( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + const uint8_t i_write_data[]); + +/// @brief does the read for the PBA +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => address for this write +/// @param[out] o_read_data => the data that is read from the PBA +/// @return FAPI_RC_SUCCESS if reading the PBA is a success + fapi2::ReturnCode p9_pba_coherent_pba_read( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + uint8_t o_read_data[]); + +/// @brief calculates the number of 128 byte granules that can be read/written before setup needs to be run again +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => starting address for PBA operation +/// @return number of 128 byte granules that can be read/written before setup needs to be run again + fapi2::ReturnCode p9_pba_coherent_utils_get_num_granules( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address, + uint32_t& o_numGranules); + +/// @brief ensure that fabric is initialized and stop control is not set +/// (by checkstop/mode switch), which if set would prohibit fabric +/// commands from being broadcasted +/// @param[in] i_target => P9 chip target +/// @return FAPI_RC_SUCCESS if fabric is not stopped + fapi2::ReturnCode p9_pba_coherent_utils_check_fbc_state( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +/// @brief check that the address is cacheline aligned and within the fabric real address range +/// @param[in] i_target => P9 chip target +/// @param[in] i_address => starting address for PBA operation +/// @return FAPI_RC_SUCCESS if arguments are valid + fapi2::ReturnCode p9_pba_coherent_utils_check_args( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_address); +/// @brief this checks the PBA/OCB status registers - this is for use at the end of each write/read or at the end of each stream +/// @return FAPI_RC_SUCCESS if the status check is a success + fapi2::ReturnCode p9_pba_coherent_status_check( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +/// @brief this does any cleanup for the PBA after all reads/writes have been done +/// @param[in] i_target => P9 chip target +/// @return FAPI_RC_SUCCESS if cleaning up the PBA is a success + fapi2::ReturnCode p9_pba_coherent_cleanup_pba( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +///@brief sets up the PBA Bar +///@param[in] i_target => P9 chip target +///@param[in] i_address => address for this read/write +///@return FAPI_RC_SUCCESS if writing the PBA is a success + fapi2::ReturnCode p9_pba_coherent_setup_pba_bar( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint64_t i_baseAddress); + +} //extern "C" + +#endif //_P9_PBA_COHERENT_UTILS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H new file mode 100644 index 00000000..f7914672 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H @@ -0,0 +1,71 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_constants.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pba_constants.H +/// @brief Constant enums to support PBA get/putmem procedures (FAPI) +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWp Consumed by: SBE + +#ifndef _P9_PBA_CONSTANTS_H_ +#define _P9_PBA_CONSTANTS_H_ + +//--------------------------------------------------------------------------------------------- +// Includes +//--------------------------------------------------------------------------------------------- + +extern "C" +{ + +//---------------------------------------------------------------------------------------------- +// Constant definitions +//---------------------------------------------------------------------------------------------- + enum pba_flags + { + // Fastmode flag + // If this flag is set it means we will not check for errors until + // the very last granule for the read/write + FLAG_PBA_FASTMODE = 0x80000000ull, + + // TTYPE flag + // PBA operation type + // 0b000: DMA + // 0b001: LCO_M + // 0b010: ATOMIC + // 0b011: CACHE_INJ + // 0b100: CI_PR_W + // Same as in the documentation and how they will be passed to the register + FLAG_PBA_TTYPE = 0x70000000ull + }; + +// TTYPE shift position + const uint64_t FLAG_PBA_TTYPE_SHIFT = 28; + const uint64_t FLAG_PBA_TTYPE_MASK = 0b111; + +} //extern "C" + +#endif //_P9_PBA_CONSTANTS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C new file mode 100644 index 00000000..32df239e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C @@ -0,0 +1,95 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//-------------------------------------------------------------------------- +// +// +/// @file p9_pba_setup.C +/// @brief Setup the registers for a read/write to the PBA +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// +//-------------------------------------------------------------------------- + + +//-------------------------------------------------------------------------- +// Includes +//-------------------------------------------------------------------------- +#include <p9_pba_setup.H> +#include "p9_pba_coherent_utils.H" + +extern "C" +{ + +//-------------------------------------------------------------------------- +// HWP entry point +//-------------------------------------------------------------------------- + fapi2::ReturnCode p9_pba_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> + & i_target, + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + uint32_t& o_numGranules) + { + // mark HWP entry + FAPI_DBG("Entering ...\n"); + + //check arguments + FAPI_TRY(p9_pba_coherent_utils_check_args(i_target, i_address), + "Error from p9_pba_coherent_utils_check_args"); + + //ensure fabric is running + FAPI_TRY(p9_pba_coherent_utils_check_fbc_state(i_target), + "Error from p9_pba_coherent_utils_check_fbc_state"); + + //reset the ADU - cleanup just calls reset + //TODO Joe had made a comment on this about resetting the PBA as part of the setup process - I need to test + //this more before I'm willing to actually put this in - I got some errors when I had it in earlier. + //FAPI_TRY(p9_pba_coherent_cleanup_pba(i_target), "p9_pba_setup: Error from p9_pba_cleanup_pba"); + + //The PBA Bar and PBA Bar Mask need to be setup before getting the number of granules because how they get setup affects the number of granules that can be read/written + //setup the PBA Bar + FAPI_TRY(p9_pba_coherent_setup_pba_bar(i_target, i_address), + "Error from p9_pba_coherent_setup_pba_bar"); + + //setup the PBA for reading/writing + FAPI_TRY(p9_pba_coherent_setup_pba(i_target, i_ex_target, i_address, i_rnw, i_flags), + "Error from p9_pba_coherent_setup_pba"); + + //figure out the number of 128B granules that can be read/written + FAPI_TRY(p9_pba_coherent_utils_get_num_granules(i_target, i_address, + o_numGranules), + "Error from p9_pba_coherent_utils_get_num_granules"); + + fapi_try_exit: + FAPI_DBG("Exiting..."); + return fapi2::current_err; + } +} // extern "C" + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H new file mode 100644 index 00000000..96ce4025 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H @@ -0,0 +1,100 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9_pba_setup.H +/// @brief Setup the PBA to do reads/writes +/// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// ---------------------------------------------------------------------------------- +// *! +// *! ADDITIONAL COMMENTS: +// *! +// *! The purpose of this procedure is to setup the PBA to do reads/writes +// *! and to return the number of granules (number of 128B reads/writes) that +// *! can be done before setup needs to be called again +// *! +// *! Successful operation assumes that: +// *! +// *! High-level procedure flow: +// *! +// *! +// *!--------------------------------------------------------------------------------- + +#ifndef _P9_PBA_SETUP_H_ +#define _P9_PBA_SETUP_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +#include <fapi2.H> +#include <p9_pba_constants.H> + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- +typedef fapi2::ReturnCode +(*p9_pba_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const fapi2::Target<fapi2::TARGET_TYPE_EX>&, + const uint64_t, + const bool, + const uint32_t, + uint32_t&); + +// Constant definitions +//----------------------------------------------------------------------------------- + +extern "C" { + +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- + +/// @brief setup for reads/writes from the PBA +/// @param[in] i_target => P9 chip target +/// @param[in] i_ex_target => P9 EX Target for use with lco_m operations +/// @param[in] i_address => base real address for read/write operation (expected to be 128B aligned) +/// @param[in] i_rnw => if the operation is read not write (1 for read, 0 for write) +/// @param[in] i_flags => other information that is needed - see the p9_pba_constants pba_flags enums for bit definitions +/// Note: to construct the flag you can use the p9_PBA_oper_flag class +/// @param[out] o_numGranules => number of 128B granules that can be read/written before setup needs to be called again +// +/// @return FAPI_RC_SUCCESS if the setup completes successfully, +// + fapi2::ReturnCode p9_pba_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target, + const uint64_t i_address, + const bool i_rnw, + const uint32_t i_flags, + uint32_t& o_numGranules); +} //extern "C" + +#endif //_P9_PBA_SETUP_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C new file mode 100755 index 00000000..840ad79b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C @@ -0,0 +1,186 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_fabricinit.C +/// @brief Initialize island-mode fabric configuration (FAPI2) +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// @author Christy Graves <clgraves@us.ibm.com> +/// + +// +// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p9_sbe_fabricinit.H> +#include <p9_fbc_utils.H> +#include <p9_misc_scom_addresses.H> + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// FBC SCOM register address definitions +// TODO: these are currently not present in the generated SCOM adddress header +// including locally defined address constants here for testing purposes +const uint64_t PU_FBC_MODE_REG = 0x05011C0A; + +// ADU delay/polling constants +const uint64_t FABRICINIT_DELAY_HW_NS = 1000; // 1us +const uint64_t FABRICINIT_DELAY_SIM_CYCLES = 200; + +// ADU Command Register field/bit definitions +const uint32_t ALTD_CMD_START_OP_BIT = 2; +const uint32_t ALTD_CMD_CLEAR_STATUS_BIT = 3; +const uint32_t ALTD_CMD_RESET_FSM_BIT = 4; +const uint32_t ALTD_CMD_ADDRESS_ONLY_BIT = 6; +const uint32_t ALTD_CMD_LOCK_BIT = 11; +const uint32_t ALTD_CMD_SCOPE_START_BIT = 16; +const uint32_t ALTD_CMD_SCOPE_END_BIT = 18; +const uint32_t ALTD_CMD_DROP_PRIORITY_BIT = 20; +const uint32_t ALTD_CMD_OVERWRITE_PBINIT_BIT = 22; +const uint32_t ALTD_CMD_TTYPE_START_BIT = 25; +const uint32_t ALTD_CMD_TTYPE_END_BIT = 31; +const uint32_t ALTD_CMD_TSIZE_START_BIT = 32; +const uint32_t ALTD_CMD_TSIZE_END_BIT = 39; + +const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT - ALTD_CMD_TTYPE_START_BIT + 1); +const uint32_t ALTD_CMD_TSIZE_NUM_BITS = (ALTD_CMD_TSIZE_END_BIT - ALTD_CMD_TSIZE_START_BIT + 1); +const uint32_t ALTD_CMD_SCOPE_NUM_BITS = (ALTD_CMD_SCOPE_END_BIT - ALTD_CMD_SCOPE_START_BIT + 1); + +const uint32_t ALTD_CMD_TTYPE_PBOP_EN_ALL = 0x3F; +const uint32_t ALTD_CMD_TSIZE_PBOP_EN_ALL = 0x0B; +const uint32_t ALTD_CMD_SCOPE_GROUP = 0x3; + +// ADU Status Register field/bit definitions +const uint32_t ALTD_STATUS_ADDR_DONE_BIT = 2; +const uint32_t ALTD_STATUS_PBINIT_MISSING_BIT = 18; +const uint32_t ALTD_STATUS_CRESP_START_BIT = 59; +const uint32_t ALTD_STATUS_CRESP_END_BIT = 63; + +const uint32_t ALTD_STATUS_CRESP_NUM_BITS = (ALTD_STATUS_CRESP_END_BIT - ALTD_STATUS_CRESP_START_BIT + 1); + +const uint32_t ALTD_STATUS_CRESP_ACK_DONE = 0x04; + + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + + +fapi2::ReturnCode +p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + FAPI_INF("Start"); + + fapi2::buffer<uint64_t> l_cmd_data; + fapi2::buffer<uint64_t> l_status_data_act; + fapi2::buffer<uint64_t> l_status_data_exp; + bool l_fbc_is_initialized, l_fbc_is_running; + + // check state of fabric pervasive stop control signal + // if set, this would prohibit all fabric commands from being broadcast + FAPI_DBG("Checking status of FBC stop ..."); + FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, l_fbc_is_initialized, l_fbc_is_running), + "Error from p9_fbc_utils_get_fbc_state"); + FAPI_ASSERT(l_fbc_is_running, + fapi2::P9_SBE_FABRICINIT_FBC_STOPPED_ERR(). + set_TARGET(i_target). + set_FBC_RUNNING(l_fbc_is_running), + "Pervasive stop control is asserted, so fabricinit will not run!"); + + // write ADU Command Register to attempt lock acquisition + // hold lock until finished with sequence + FAPI_DBG("Lock and reset ADU ..."); + l_cmd_data.setBit<ALTD_CMD_LOCK_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data), + "Error writing ADU Command Register to acquire lock"); + + // clear ADU status/reset state machine + l_cmd_data.setBit<ALTD_CMD_CLEAR_STATUS_BIT>() + .setBit<ALTD_CMD_RESET_FSM_BIT>(); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data), + "Error writing ADU Command Register to clear status and reset state machine"); + + // launch init command + FAPI_INF("Launching fabric init command via ADU ..."); + l_cmd_data.setBit<ALTD_CMD_START_OP_BIT>() + .clearBit<ALTD_CMD_CLEAR_STATUS_BIT>() + .clearBit<ALTD_CMD_RESET_FSM_BIT>() + .setBit<ALTD_CMD_ADDRESS_ONLY_BIT>() + .setBit<ALTD_CMD_DROP_PRIORITY_BIT>() + .setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>(); + l_cmd_data.insertFromRight<ALTD_CMD_SCOPE_START_BIT, ALTD_CMD_SCOPE_NUM_BITS>(ALTD_CMD_SCOPE_GROUP); + l_cmd_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PBOP_EN_ALL); + l_cmd_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_TSIZE_PBOP_EN_ALL); + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data), + "Error writing ADU Command Register to launch init operation"); + + // delay prior to checking for completion + FAPI_TRY(fapi2::delay(FABRICINIT_DELAY_HW_NS, FABRICINIT_DELAY_SIM_CYCLES), + "Error from delay"); + + // read ADU Status Register and check for expected pattern + FAPI_DBG("Checking status of ADU operation ..."); + FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_status_data_act), + "Error polling ADU Status Register"); + + l_status_data_exp.setBit<ALTD_STATUS_ADDR_DONE_BIT>(); + l_status_data_exp.insertFromRight<ALTD_STATUS_CRESP_START_BIT, ALTD_STATUS_CRESP_NUM_BITS>(ALTD_STATUS_CRESP_ACK_DONE); + + FAPI_ASSERT(l_status_data_exp == l_status_data_act, + fapi2::P9_SBE_FABRICINIT_FAILED_ERR().set_TARGET(i_target). + set_ADU_STATUS_EXP(l_status_data_act). + set_ADU_STATUS_ACT(l_status_data_act), + "Fabric init failed, or mismatch in expected ADU status!"); + + // clear ADU Command Register to release lock + FAPI_DBG("Success! Releasing ADU lock ..."); + l_cmd_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data), + "Error writing ADU Command Register to release lock"); + + // confirm that fabric was successfully initialized + FAPI_DBG("Verifying status of FBC init/stop ..."); + FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, l_fbc_is_initialized, l_fbc_is_running), + "Error from p9_fbc_utils_get_fbc_state"); + FAPI_ASSERT(l_fbc_is_initialized && l_fbc_is_running, + fapi2::P9_SBE_FABRICINIT_NO_INIT_ERR(). + set_TARGET(i_target). + set_FBC_INITIALIZED(l_fbc_is_initialized). + set_FBC_RUNNING(l_fbc_is_running), + "ADU command succeded, but fabric was not cleanly initialized!"); + +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H new file mode 100755 index 00000000..ee1acf4a --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H @@ -0,0 +1,109 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_fabricinit.H +/// @brief Initialize island-mode fabric configuration (FAPI2) +/// +/// The purpose of this procedure is to initalize the fabric. +/// +/// In the post scan flush/init state, the fabric command/data init lines on +/// each chip are held de-asserted; this stops all local arbitration for +/// command/data requests from attached units. At the conclusion of this +/// procedure, the fabric command/data init lines on the target chip +/// will be asserted. Units on the target chip may make fabric requests that +/// will be processed and broadcast out to the SMP (consisting of the target +/// chip only), based upon the defined fabric broadcast protocols. +/// +/// The initialization is accomplished by injecting an init command (special +/// ttype/tsize) into the fabric from the Alter Display Unit (ADU). This +/// command is permitted to be broadcast (even though the target chip is not +/// yet initialized), because the ADU is considered a trusted unit allowed +/// to broadcast commands at any time. +/// +/// When the init reflected command is observed by the fabric snooper logic +/// (with target chip configured as fabric master), it will provide an +/// lpc_ack partial response that generates a clean combined response +/// (ack_done). Upon observation of the clean combined response broadcast, +/// the fabric snooper logic will assert its command/data init lines to +/// permit locally mastered requests to be arbitrated. +/// +/// High-level procedure flow: +/// - Check state of tc_pb_stop (set by checkstop), which if +/// set would prohibit the init command from being broadcast +/// - Acquire the ADU lock to guarantee exclusive use of ADU resources +/// - Clear the ADU status register, reset ADU state machine +/// - Program the ADU to issue & launch the init command +/// - Check the status of the init command +/// - Release the ADU lock +/// - Confirm state of fabric init control +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// @author Christy Graves <clgraves@us.ibm.com> +/// + +// +// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// + +#ifndef _P9_SBE_FABRICINIT_H_ +#define _P9_SBE_FABRICINIT_H_ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_fabricinit_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ + +/// +/// @brief Initialize fabric (in single chip 'island mode' configuration) by mastering +/// an init command (ttype=pbop.init_all) from the Alter Display Unit (ADU) +/// +/// @param[in] i_target Reference to processor chip target +/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// + fapi2::ReturnCode p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +} // extern "C" + +#endif // _P9_SBE_FABRICINIT_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H new file mode 100644 index 00000000..0fd5b531 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9_sbe_hb_structures.H +/// @brief Structures that the SBE and HB will both use +// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE, HB +//----------------------------------------------------------------------------------- + +#ifndef _SBE_HB_STRUCTURES_H_ +#define _SBE_HB_STRUCTURES_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +// Structure starts at the bootloader zero address +struct BootloaderConfigData_t +{ + uint32_t version; // Some kind of version field so we know if there is new data being added + uint8_t sbeBootSide; // 0=SBE side 0, 1=SBE side 1 [ATTR_SBE_BOOT_SIDE] + uint8_t pnorBootSide; // 0=PNOR side A, 1=PNOR side B [ATTR_PNOR_BOOT_SIDE] + uint16_t pnorSizeMB; // Size of PNOR in MB [ATTR_PNOR_SIZE] + uint64_t blLoadSize; // Size of Load (Exception vectors and Bootloader) +}; + +#endif diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C new file mode 100644 index 00000000..10380058 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -0,0 +1,327 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//-------------------------------------------------------------------------- +// +// @file p9_sbe_load_bootloader.C +// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA +// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Writer: Murey A Luna Torres malunato@us.ibm.com, Joseph McGill jmcgill@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// +//-------------------------------------------------------------------------- + +//-------------------------------------------------------------------------- +// Includes +//-------------------------------------------------------------------------- +#include <p9_sbe_load_bootloader.H> +#include <p9_pba_setup.H> +#include <p9_pba_access.H> +#include <p9_fbc_utils.H> +#include <p9_pba_coherent_utils.H> +#include <p9_quad_scom_addresses.H> +#include <p9_quad_scom_addresses_fld.H> +#include <p9_ram_core.H> + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +// PBA setup/access HWP call constants +const bool PBA_HWP_WRITE_OP = false; +const int EXCEPTION_VECTOR_NUM_CACHELINES = 96; +const uint32_t SBE_BOOTLOADER_VERSION = 0x901; +const uint8_t PERV_TO_CORE_POS_OFFSET = 0x20; +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- + +fapi2::ReturnCode p9_sbe_load_bootloader( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target, + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_ex_target, + const uint64_t i_payload_size, + uint8_t* i_payload_data) +{ + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + //the branching instruction for 12KB past where it currently is (1024 * 12 = 12288 = 0x3000) + //The branch instruction is 0100 10_address to branch to_ 0 0 + // 0 6 29 30 31 + //bit 30 is for absolute address (since it is not set this is relative) + const uint32_t l_branch_to_12 = 0x48003000ull; + const uint32_t C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0 = 18; + uint64_t l_bootloader_offset; + uint64_t l_hostboot_hrmor_offset; + uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1; + uint64_t l_chip_base_address_m; + uint64_t l_chip_base_address_mmio; + uint64_t l_target_address; + uint32_t l_exception_instruction; + bool l_firstAccess = true; + uint32_t l_num_cachelines_to_roll; + uint8_t l_data_to_pass_to_pba_array[FABRIC_CACHELINE_SIZE]; + uint32_t l_exception_vector_size = 0; + uint8_t l_master_core = 0; + int l_cacheline_num = 0; + p9_PBA_oper_flag l_myPbaFlag; + fapi2::buffer<uint64_t> l_dataBuf; + fapi2::Target<fapi2::TARGET_TYPE_CORE> l_coreTarget; + bool l_coreFoundMatch = false; + + FAPI_DBG("Start"); + + //Find the master core for writing the HRMOR later + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MASTER_CORE, i_master_chip_target, l_master_core), "Error getting ATTR_MASTER_CORE"); + + for ( auto l_current_core : i_master_ex_target.getChildren<fapi2::TARGET_TYPE_CORE>()) + { + uint8_t l_attr_chip_unit_pos = 0; + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = l_current_core.getParent<fapi2::TARGET_TYPE_PERV>(); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos), + "Error getting ATTR_CHIP_UNIT_POS"); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - PERV_TO_CORE_POS_OFFSET; + FAPI_DBG("l_attr_chip_unit_pos = %d, l_attr_chip_unit_pos = %d, l_master_core = %d", l_attr_chip_unit_pos, + l_attr_chip_unit_pos, l_master_core); + + if (l_attr_chip_unit_pos == l_master_core) + { + l_coreTarget = l_current_core; + l_coreFoundMatch = true; + break; + } + } + + FAPI_ASSERT(l_coreFoundMatch, fapi2::P9_MASTER_CORE_NOT_FOUND().set_CHIP_TARGET(i_master_chip_target).set_EX_TARGET( + i_master_ex_target).set_MASTER_CORE(l_master_core) , "Error in finding the master core"); + + // read platform initialized attributes needed to determine target base address + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOTLOADER_OFFSET, FAPI_SYSTEM, l_bootloader_offset), + "Error from FAPI_ATTR_GET (ATTR_SBE_BOOTLOADER_OFFSET)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, FAPI_SYSTEM, l_hostboot_hrmor_offset), + "Error from FAPI_ATTR_GET (ATTR_HOSTBOOT_HRMOR_OFFSET)"); + + // target base address = (chip non-mirrored base address) + + // (hostboot HRMOR offset) + + // (bootloader offset) + FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target, + l_chip_base_address_nm0, + l_chip_base_address_nm1, + l_chip_base_address_m, + l_chip_base_address_mmio), + "Error from p9_fbc_utils_get_chip_base_address"); + + // add hostboot HRMOR offset and bootloader offset contributions + l_chip_base_address_nm0 += l_hostboot_hrmor_offset; + l_chip_base_address_nm0 += l_bootloader_offset; + + // check that base address is cacheline aligned + FAPI_ASSERT(!(l_chip_base_address_nm0 % FABRIC_CACHELINE_SIZE), + fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS(). + set_CHIP_TARGET(i_master_chip_target). + set_EX_TARGET(i_master_ex_target). + set_TARGET_BASE_ADDRESS(l_chip_base_address_nm0). + set_HRMOR_OFFSET(l_hostboot_hrmor_offset). + set_BOOTLOADER_OFFSET(l_bootloader_offset), + "Target base address is not cacheline aligned!"); + + //Check to see if we need to populate the exception vectors + //Check the SBE_HBBL_EXCEPTION_INSTRUCT attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT, FAPI_SYSTEM, l_exception_instruction), + "fapiGetAttribute of ATTR_SBE_HBBL_EXCEPTION_INSTRUCT failed!"); + + l_target_address = l_chip_base_address_nm0; + + BootloaderConfigData_t l_bootloader_config_data; + + l_bootloader_config_data.version = SBE_BOOTLOADER_VERSION; + + //At address X + 0x8 put whatever is in ATTR_SBE_BOOT_SIDE + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.sbeBootSide), + "fapiGetAttribute of ATTR_SBE_BOOT_SIDE failed!"); + + //At address X + 0x9 put whatever is in ATTR_PNOR_BOOT_SIDE + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.pnorBootSide), + "fapiGetAttribute of ATTR_PNOR_BOOT_SIDE failed!"); + + //At address X + 0xA put whatever is in ATTR_PNOR_SIZE + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_SIZE, FAPI_SYSTEM, l_bootloader_config_data.pnorSizeMB), + "fapiGetAttribute of ATTR_PNOR_SIZE failed!"); + + // check that the payload size is non-zero and evenly divisible into cachelines + FAPI_ASSERT(i_payload_size && !(i_payload_size % FABRIC_CACHELINE_SIZE), + fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_PAYLOAD_SIZE(). + set_CHIP_TARGET(i_master_chip_target). + set_EX_TARGET(i_master_ex_target). + set_PAYLOAD_SIZE(i_payload_size), + "Payload size is invalid!"); + + // adjust exception vector size + if (l_exception_instruction != 0x0) + { + l_exception_vector_size = EXCEPTION_VECTOR_NUM_CACHELINES * FABRIC_CACHELINE_SIZE; + } + + // Pass size of load including exception vectors and Bootloader + l_bootloader_config_data.blLoadSize = l_exception_vector_size + i_payload_size; + + // move data using PBA setup/access HWPs + l_myPbaFlag.setFastMode(true); // FASTMODE + l_myPbaFlag.setOperationType(p9_PBA_oper_flag::LCO); // LCO operation + + while (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)) + { + // invoke PBA setup HWP to prep stream + FAPI_TRY(p9_pba_setup( i_master_chip_target, + i_master_ex_target, + l_target_address, + PBA_HWP_WRITE_OP, + l_myPbaFlag.setFlag(), + l_num_cachelines_to_roll), "Error from p9_pba_setup"); + + l_firstAccess = true; + + // call PBA access HWP per cacheline to move payload data + while (l_num_cachelines_to_roll && + (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size))) + { + if ((l_cacheline_num == 0) && (l_exception_instruction != 0)) + { + //This is for the first cacheline of data that has the branch, pnor_size, and pnor_boot_side in it + //The rest of the exception vector is what was in SBE_HBBL_EXCEPTION_INSTRUCT replicated multiple times (until the end of 12KB of exception vector data) + for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++) + { + //At address X put whatever is in l_branch_to_12 + if (i < 4) + { + l_data_to_pass_to_pba_array[i] = (l_branch_to_12 >> (24 - 8 * i )) & 0xFF; + } + //At address X + 0x4 put the HBBL_STRUCT_VERSION + else if (i < 8) + { + l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.version >> (24 - 8 * ((i - 4) % 4))) & 0xFF; + } + //At address X + 0x8 put the SBE_BOOT_SIDE + else if (i == 8) + { + l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.sbeBootSide; + } + //At address X + 0x9 put the PNOR_BOOT_SIDE + else if (i == 9) + { + l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorBootSide; + } + //At address X + 0xA pu the PNOR_SIZE + else if (i == 10) + { + l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB >> 8 & 0xFF; + } + else if (i == 11) + { + l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB & 0xFF; + } + //At address X + 0xC put the total load size + else if (i < 20) + { + l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.blLoadSize >> (56 - 8 * ((i - 12) % 8))) & 0xFF; + } + //Fill the rest with the exception vector instruction + else + { + l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF; + } + } + } + else if ((l_cacheline_num == 1) && (l_exception_instruction != 0)) + { + //This is for the other 95 cachelines that we are sending + for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++) + { + l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF; + } + } + else if ((l_cacheline_num >= EXCEPTION_VECTOR_NUM_CACHELINES) || (l_exception_instruction == 0)) + { + //This is for the data after the exception vector + for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++) + { + l_data_to_pass_to_pba_array[i] = i_payload_data[((l_cacheline_num - (l_exception_vector_size / FABRIC_CACHELINE_SIZE)) * + FABRIC_CACHELINE_SIZE) + + i]; + } + } + + FAPI_TRY(p9_pba_access(i_master_chip_target, + l_target_address, + PBA_HWP_WRITE_OP, + l_myPbaFlag.setFlag(), + l_firstAccess, + (l_num_cachelines_to_roll == 1) || + ((l_target_address + FABRIC_CACHELINE_SIZE) >= + (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)), + l_data_to_pass_to_pba_array), "Error from p9_pba_access"); + l_firstAccess = false; + // decrement count of cachelines remaining in current stream + l_num_cachelines_to_roll--; + + // stride address/payload data pointer offset to next cacheline + l_target_address += FABRIC_CACHELINE_SIZE; + l_cacheline_num++; + } + } + + { + //instantiate the basic RamCore class + RamCore ram(l_coreTarget, 0); + + //Set the HRMOR + //Override PM_EXIT on master core bit 4 is for core 0 bit 5 is for core 1 + if (l_master_core % 2 == 0) + { + l_dataBuf.flush<0>().setBit<EQ_CME_SCOM_SICR_PM_EXIT_C0>(); + } + else + { + l_dataBuf.flush<0>().setBit<EQ_CME_SCOM_SICR_PM_EXIT_C1>(); + } + + FAPI_TRY(fapi2::putScom(i_master_ex_target, EX_0_CME_SCOM_SICR_SCOM2, l_dataBuf), + "Error overriding PM_EXIT"); + //Set ram_thread_active for t0 + l_dataBuf.flush<0>().setBit<C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0>(); + FAPI_TRY(fapi2::putScom(l_coreTarget, C_0_THREAD_INFO, l_dataBuf), + "Error setting thread active for t0"); + l_dataBuf.flush<0>().insertFromRight<0, 64>(l_chip_base_address_nm0); + //call RamCore put_reg method + FAPI_TRY(ram.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR"); + } + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H new file mode 100644 index 00000000..e5536789 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H @@ -0,0 +1,99 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------------ +// +/// @file p9_sbe_load_bootloader.H +/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA +// +// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com +// *HWP HWP Writer: Murey A Luna Torres malunato@us.ibm.com, Joseph McGill jmcgill@us.ibm.com +// *HWP FW Owner: Thi Tran thi@us.ibm.com +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +//----------------------------------------------------------------------------------- +// *! ADDITIONAL COMMENTS: +// *! +// *! This hardware procedure is used to load a bootloader image from seeprom into +// *! L3 of master core via PBA unit. +// *! +// *! Successful operation assumes that: +// *! PBA communication is available +// *! +// *! High-level procedure flow: +// *! +//------------------------------------------------------------------------------------ + +#ifndef _SBE_BOOTLOADER_H_ +#define _SBE_BOOTLOADER_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- + +#include <fapi2.H> +#include <p9_sbe_hb_structures.H> +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- + +//function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode(*p9_sbe_load_bootloader_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const fapi2::Target<fapi2::TARGET_TYPE_EX>&, + const uint64_t, + uint8_t*); + +//----------------------------------------------------------------------------------- +// Constant definitions +//----------------------------------------------------------------------------------- + +extern "C" { + + //----------------------------------------------------------------------------------- + // Function prototype + //----------------------------------------------------------------------------------- + // +/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA +/// @param[in] i_master_chip_target Reference to master processor chip target +/// @param[in] i_master_ex_target Reference to master ex unit target +/// @param[in] i_payload_size Size of image payload load to load, in B +/// @param[in] i_payload_data Pointer to image payload data +/// +/// @return FAPI_RC_SUCCESS if success, else error code +/// + fapi2::ReturnCode p9_sbe_load_bootloader( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target, + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_eq_target, + const uint64_t i_payload_size, + uint8_t* i_payload_data); + +} //extern "C" + +#endif //_SBE_BOOTLOADER_H_ + + + + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C new file mode 100644 index 00000000..1fe5dc4f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C @@ -0,0 +1,197 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_mcs_setup.C +/// @brief Configure MC unit to support HB execution (FAPI2) +/// + +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// + +// +// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p9_sbe_mcs_setup.H> +#include <p9_fbc_utils.H> +#include <p9_mc_scom_addresses.H> +#include <p9_mc_scom_addresses_fld.H> + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ +const uint8_t MCS_MCFGP_BASE_ADDRESS_START_BIT = 8; + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +/// +/// @brief Set hostboot dcbz MC configuration for one unit target +/// +/// @param[in] i_target Reference to an MC target (MCS/MI) +/// @param[in] i_chip_base_address Chip non-mirrored base address +////// @return FAPI2_RC_SUCCESS if success, else error code. +/// +template<fapi2::TargetType T> +fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<T>& i_target, + const uint64_t i_chip_base_address); + + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + + +// specialization for MCS target type +template<> +fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + const uint64_t i_chip_base_address) +{ + FAPI_DBG("Start"); + fapi2::buffer<uint64_t> l_mcfgp; + fapi2::buffer<uint64_t> l_mcmode1; + fapi2::buffer<uint64_t> l_mcfirmask_and; + + // MCFGP -- set BAR valid, configure single MC group with minimum size at chip base address + FAPI_TRY(fapi2::getScom(i_target, MCS_MCFGP, l_mcfgp), + "Error from getScom (MCS_MCFGP)"); + l_mcfgp.setBit<MCS_MCFGP_VALID>(); + l_mcfgp.clearBit<MCS_MCFGP_MC_CHANNELS_PER_GROUP, + MCS_MCFGP_MC_CHANNELS_PER_GROUP_LEN>(); + l_mcfgp.clearBit<MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION, + MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN>(); + l_mcfgp.clearBit<MCS_MCFGP_GROUP_SIZE, MCS_MCFGP_GROUP_SIZE_LEN>(); + // group base address field covers RA 8:31 + l_mcfgp.insert(i_chip_base_address, + MCS_MCFGP_GROUP_BASE_ADDRESS, + MCS_MCFGP_GROUP_BASE_ADDRESS_LEN, + MCS_MCFGP_BASE_ADDRESS_START_BIT); + FAPI_TRY(fapi2::putScom(i_target, MCS_MCFGP, l_mcfgp), + "Error from putScom (MCS_MCFGP)"); + + // MCMODE1 -- disable speculation + FAPI_TRY(fapi2::getScom(i_target, MCS_MCMODE1, l_mcmode1), + "Error from getScom (MCS_MCMODE1)"); + l_mcmode1.setBit<MCS_MCMODE1_DISABLE_ALL_SPEC_OPS>(); + l_mcmode1.setBit<MCS_MCMODE1_DISABLE_SPEC_OP, + MCS_MCMODE1_DISABLE_SPEC_OP_LEN>(); + FAPI_TRY(fapi2::putScom(i_target, MCS_MCMODE1, l_mcmode1), + "Error from putScom (MCS_MCMODE1)"); + + // MCFIRMASK -- unmask command list/channel timeout errors (so a checkstop will + // occur if we break cache containment, but hit against the BAR) + l_mcfirmask_and.flush<1>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_COMMAND_LIST_TIMEOUT>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC>(); + l_mcfirmask_and.clearBit<MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR>(); + FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRMASK_AND, l_mcfirmask_and), + "Error from putScom (MCS_MCFIRMASK_AND)"); + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} + + +// specialization for MI target type +template<> +fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_target, + const uint64_t i_chip_base_address) +{ + // TODO: implement for Cumulus (MI target) + return fapi2::current_err; +} + + +// HWP entry point +fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + FAPI_INF("Start"); + + uint8_t l_is_master_sbe; + uint8_t l_is_mpipl; + uint8_t l_ipl_type; + uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, l_chip_base_address_mmio; + + auto l_mcs_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCS>(); + auto l_mi_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MI>(); + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + + // configure one MC on master chip (only if IPL is loading hostboot, and is not memory + // preserving) + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target, l_is_master_sbe), + "Error from FAPI_ATTR_GET (ATTR_PROC_SBE_MASTER_CHIP)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl), + "Error from FAPI_ATTR_GET (ATTR_IS_MPIPL)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_ipl_type), + "Error from FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)"); + + if ((l_ipl_type == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL) && + l_is_master_sbe && + !l_is_mpipl) + { + FAPI_ASSERT(l_mcs_chiplets.size() || l_mi_chiplets.size(), + fapi2::P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR().set_CHIP(i_target), + "No functional MC unit target found"); + + // determine base address + FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, + l_chip_base_address_nm0, + l_chip_base_address_nm1, + l_chip_base_address_m, + l_chip_base_address_mmio), + "Error from p9_fbc_utils_get_chip_base_addrs"); + + if (l_mcs_chiplets.size()) + { + FAPI_TRY(set_hb_dcbz_config(l_mcs_chiplets.front(), + l_chip_base_address_nm0), + "Error from set_hb_dcbz_config (MCS)"); + } + else + { + FAPI_TRY(set_hb_dcbz_config(l_mi_chiplets.front(), + l_chip_base_address_nm0), + "Error from set_hb_dcbz_config (MI)"); + } + } + +fapi_try_exit: + FAPI_INF("End"); + return fapi2::current_err; + +} + diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H new file mode 100644 index 00000000..d3017dcf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H @@ -0,0 +1,77 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_mcs_setup.H +/// @brief Configure MC unit to support HB execution (FAPI2) +/// +/// Configure MC unit on the master chip to lpc_ack dcbz operations +/// executed by hostboot code (while still running cache contained prior +/// to configuration of system memory) +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// + +// +// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// + +#ifndef _P9_SBE_MCS_SETUP_H_ +#define _P9_SBE_MCS_SETUP_H_ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_mcs_setup_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ + +/// +/// @brief Set MC configuration to enable initial phase of hostboot execution +/// +/// @param[in] i_target Reference to processor chip target +/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. + + fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); +} // extern "C" + +#endif // _P9_SBE_MCS_SETUP_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C new file mode 100644 index 00000000..a2510582 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -0,0 +1,405 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// +/// @file p9_sbe_scominit.C +/// @brief Peform SCOM initialization required for fabric & HBI operation (FAPI2) +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// @author Christy Graves <clgraves@us.ibm.com> +/// + +// +// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: Nest +// *HWP Level: 2 +// *HWP Consumed by: SBE +// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p9_sbe_scominit.H> +#include <p9_fbc_utils.H> + +#include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// XSCOM/LPC BAR constants +const uint64_t XSCOM_BAR_MASK = 0xFF000003FFFFFFFFULL; +const uint64_t LPC_BAR_MASK = 0xFF000000FFFFFFFFULL; + +// FBC FIR constants +const uint64_t FBC_CENT_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t FBC_CENT_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_CENT_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_WEST_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t FBC_WEST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_WEST_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_EAST_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t FBC_EAST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t FBC_EAST_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; + +// PBA FIR constants +const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL; +const uint64_t PBA_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL; +const uint64_t PBA_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL; + +// chiplet pervasive FIR constants +const uint64_t PERV_LFIR_ACTION0[15] = +{ + 0x0000000000000000ULL, // TP + 0x0000000000000000ULL, // N0 + 0x0000000000000000ULL, // N1 + 0x0000000000000000ULL, // N2 + 0x0000000000000000ULL, // N3 + 0x0000000000000000ULL, // X + 0x0000000000000000ULL, // - + 0x0000000000000000ULL, // - + 0x0000000000000000ULL, // OB0 + 0x0000000000000000ULL, // OB1 + 0x0000000000000000ULL, // OB2 + 0x0000000000000000ULL, // OB3 + 0x0000000000000000ULL, // PCI0 + 0x0000000000000000ULL, // PCI1 + 0x0000000000000000ULL // PCI2 +}; + +const uint64_t PERV_LFIR_ACTION1[15] = +{ + 0x0000000000000000ULL, // TP + 0xFFFFFFFFFFFFFFFFULL, // N0 + 0xFFFFFFFFFFFFFFFFULL, // N1 + 0xFFFFFFFFFFFFFFFFULL, // N2 + 0xFFFFFFFFFFFFFFFFULL, // N3 + 0xFFFFFFFFFFFFFFFFULL, // X + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // OB0 + 0xFFFFFFFFFFFFFFFFULL, // OB1 + 0xFFFFFFFFFFFFFFFFULL, // OB2 + 0xFFFFFFFFFFFFFFFFULL, // OB3 + 0xFFFFFFFFFFFFFFFFULL, // PCI0 + 0xFFFFFFFFFFFFFFFFULL, // PCI1 + 0xFFFFFFFFFFFFFFFFULL // PCI2 +}; + +const uint64_t PERV_LFIR_MASK[15] = +{ + 0xFFFFFFFFFFFFFFFFULL, // TP + 0xFFFFFFFFFFFFFFFFULL, // N0 + 0xFFFFFFFFFFFFFFFFULL, // N1 + 0xFFFFFFFFFFFFFFFFULL, // N2 + 0xFFFFFFFFFFFFFFFFULL, // N3 + 0xFFFFFFFFFFFFFFFFULL, // X + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // OB0 + 0xFFFFFFFFFFFFFFFFULL, // OB1 + 0xFFFFFFFFFFFFFFFFULL, // OB2 + 0xFFFFFFFFFFFFFFFFULL, // OB3 + 0xFFFFFFFFFFFFFFFFULL, // PCI0 + 0xFFFFFFFFFFFFFFFFULL, // PCI1 + 0xFFFFFFFFFFFFFFFFULL // PCI2 +}; + +// chiplet XIR constants +const uint64_t PERV_XFIR_MASK[15] = +{ + 0xFFFFFFFFFFFFFFFFULL, // TP + 0xFFFFFFFFFFFFFFFFULL, // N0 + 0xFFFFFFFFFFFFFFFFULL, // N1 + 0xFFFFFFFFFFFFFFFFULL, // N2 + 0xFFFFFFFFFFFFFFFFULL, // N3 + 0xFFFFFFFFFFFFFFFFULL, // X + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // - + 0xFFFFFFFFFFFFFFFFULL, // OB0 + 0xFFFFFFFFFFFFFFFFULL, // OB1 + 0xFFFFFFFFFFFFFFFFULL, // OB2 + 0xFFFFFFFFFFFFFFFFULL, // OB3 + 0xFFFFFFFFFFFFFFFFULL, // PCI0 + 0xFFFFFFFFFFFFFFFFULL, // PCI1 + 0xFFFFFFFFFFFFFFFFULL // PCI2 +}; + + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +fapi2::ReturnCode +p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + +{ + FAPI_DBG("Entering ..."); + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + uint64_t l_base_addr_nm0; + uint64_t l_base_addr_nm1; + uint64_t l_base_addr_m; + uint64_t l_base_addr_mmio; + + // set fabric topology information in each pervasive chiplet (outside of EC/EP) + { + // read fabric topology attributes + uint32_t l_fbc_system_id; + uint8_t l_fbc_group_id; + uint8_t l_fbc_chip_id; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fbc_system_id), + "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_SYSTEM_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fbc_group_id), + "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_GROUP_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fbc_chip_id), + "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_CHIP_ID)"); + + for (auto l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP | + fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + fapi2::buffer<uint64_t> l_cplt_conf0; + FAPI_TRY(fapi2::getScom(l_chplt_target, PERV_CPLT_CONF0, l_cplt_conf0), + "Error from getScom (PERV_CPLT_CONF0)"); + l_cplt_conf0.insertFromRight<PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC, PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN> + (l_fbc_system_id) + .insertFromRight<PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC, PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN>(l_fbc_group_id) + .insertFromRight<PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC, PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN>(l_fbc_chip_id); + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_CPLT_CONF0, l_cplt_conf0), + "Error from putScom (PERV_CPLT_CONF0)"); + } + } + + // determine base address of chip nm/m/mmmio regions in real address space + FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, + l_base_addr_nm0, + l_base_addr_nm1, + l_base_addr_m, + l_base_addr_mmio), + "Error from p9_fbc_utils_get_chip_base_address"); + + // set XSCOM BAR + { + fapi2::buffer<uint64_t> l_xscom_bar; + uint64_t l_xscom_bar_offset; + + FAPI_DBG("Configuring XSCOM BAR"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_xscom_bar_offset), + "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)"); + + l_xscom_bar = l_base_addr_mmio; + l_xscom_bar += l_xscom_bar_offset; + + FAPI_ASSERT((l_xscom_bar & XSCOM_BAR_MASK) == 0, + fapi2::P9_SBE_SCOMINIT_XSCOM_BAR_ATTR_ERR(). + set_TARGET(i_target). + set_XSCOM_BAR(l_xscom_bar). + set_XSCOM_BAR_OFFSET(l_xscom_bar_offset). + set_BASE_ADDR_MMIO(l_base_addr_mmio), + "Invalid XSCOM BAR configuration!"); + + FAPI_TRY(fapi2::putScom(i_target, PU_XSCOM_BASE_REG, l_xscom_bar), + "Error from putScom (PU_XSCOM_BASE_REG)"); + } + + // set LPC BAR + { + fapi2::buffer<uint64_t> l_lpc_bar; + uint64_t l_lpc_bar_offset; + + FAPI_DBG("Configuring LPC BAR"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_lpc_bar_offset), + "Error from FAPI_ATTR_GET (ATRR_PROC_LPC_BAR_BASE_ADDR_OFFSET"); + + l_lpc_bar = l_base_addr_mmio; + l_lpc_bar += l_lpc_bar_offset; + + FAPI_ASSERT((l_lpc_bar & LPC_BAR_MASK) == 0, + fapi2::P9_SBE_SCOMINIT_LPC_BAR_ATTR_ERR(). + set_TARGET(i_target). + set_LPC_BAR(l_lpc_bar). + set_LPC_BAR_OFFSET(l_lpc_bar_offset). + set_BASE_ADDR_MMIO(l_base_addr_mmio), + "Invalid LPC BAR configuration!"); + + FAPI_TRY(fapi2::putScom(i_target, PU_LPC_BASE_REG, l_lpc_bar), + "Error from putScom (PU_LPC_BASE_REG)"); + } + + // configure FBC FIRs + { + fapi2::buffer<uint64_t> l_scom_data; + + // CENT + FAPI_DBG("Configuring FBC CENT FIR"); + // clear FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_REG)"); + + // configure action/mask + l_scom_data = FBC_CENT_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG)"); + + l_scom_data = FBC_CENT_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG)"); + + l_scom_data = FBC_CENT_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG, l_scom_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG)"); + + // WEST + FAPI_DBG("Configuring FBC WEST FIR"); + // clear FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_REG)"); + + // configure action/mask + l_scom_data = FBC_WEST_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG)"); + + l_scom_data = FBC_WEST_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG)"); + + l_scom_data = FBC_WEST_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG, l_scom_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG)"); + + // EAST + FAPI_DBG("Configuring FBC EAST FIR"); + // clear FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_REG)"); + + // configure action/mask + l_scom_data = FBC_EAST_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_ACTION0_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_ACTION0_REG)"); + + l_scom_data = FBC_EAST_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_ACTION1_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_ACTION1_REG)"); + + l_scom_data = FBC_EAST_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_MASK_REG, l_scom_data), + "Error from putScom (PU_PB_EAST_FIR_MASK_REG)"); + } + + // configure PBA FIRs + { + fapi2::buffer<uint64_t> l_scom_data; + + // clear FIR + FAPI_DBG("Configuring PBA FIR"); + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIR, l_scom_data), + "Error from putScom (PU_PBAFIR)"); + + // configure action/mask + l_scom_data = PBA_FIR_ACTION0; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT0, l_scom_data), + "Error from putScom (PU_PBAFIRACT0)"); + + l_scom_data = PBA_FIR_ACTION1; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT1, l_scom_data), + "Error from putScom (PU_PBAFIRACT1)"); + + l_scom_data = PBA_FIR_MASK; + FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRMASK, l_scom_data), + "Error from putScom (PU_PBAFIRMASK)"); + } + + // configure chiplet pervasive FIRs / XFIRs + { + for (auto l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP | + fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + uint8_t l_unit_idx; + fapi2::buffer<uint64_t> l_scom_data; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_target, l_unit_idx), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + l_unit_idx--; + + + // PERV LFIR + FAPI_DBG("Configuring PERV LFIR (chiplet ID: %02X)", l_unit_idx + 1); + // reset pervasive FIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR)"); + + // configure pervasive FIR action/mask + l_scom_data = PERV_LFIR_ACTION0[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION0, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_ACTION0)"); + + l_scom_data = PERV_LFIR_ACTION1[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION1, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_ACTION1)"); + + l_scom_data = PERV_LFIR_MASK[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_MASK, l_scom_data), + "Error from putScom (PERV_LOCAL_FIR_MASK)"); + + // XFIR + FAPI_DBG("Configuring chiplet XFIR (chiplet ID: %02X)", l_unit_idx + 1); + // reset XFIR + l_scom_data = 0; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_XFIR, l_scom_data), + "Error from putScom (PERV_XFIR)"); + + // configure XFIR mask + l_scom_data = PERV_XFIR_MASK[l_unit_idx]; + FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_FIR_MASK, l_scom_data), + "Error from putScom (PERV_FIR_MASK"); + } + } + +fapi_try_exit: + FAPI_DBG("Exiting ..."); + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H new file mode 100644 index 00000000..4129098e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H @@ -0,0 +1,78 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_scominit.H +/// @brief Peform SCOM initialization required for fabric & HBI operation (FAPI2) +/// +/// @author Joe McGill <jmcgill@us.ibm.com> +/// @author Christy Graves <clgraves@us.ibm.com> +/// + +// +// *HWP HWP Owner : Joe McGill <jmcgill@us.ibm.com> +// *HWP FW Owner : Thi N. Tran <thi@us.ibm.com> +// *HWP Team : Nest +// *HWP Level : 2 +// *HWP Consumed by : SBE +// + +#ifndef _P9_SBE_SCOMINIT_H_ +#define _P9_SBE_SCOMINIT_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_scominit_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ + +/// +/// @brief Set fabric topology IDs for all configured chipets (outside of EC/EP), +/// performs BAR setup needed for HBI (XSCOM/LPC), configures selected FIRs in +/// preparation for fabric init +/// an init command (ttype=pbop.init_all) from the Alter Display Unit (ADU) +/// +/// @param[in] i_target Reference to processor chip target +/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// + fapi2::ReturnCode p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +} // extern "C" + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/Makefile b/src/import/chips/p9/procedures/hwp/perv/Makefile new file mode 100644 index 00000000..ac2ee6de --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/Makefile @@ -0,0 +1,55 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/perv/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the core hardware procedure code. See the +# "pervfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/perv +export SUB_OBJDIR = /perv + +include img_defs.mk +include pervfiles.mk + +GCC-CFLAGS += -mlongcall + +OBJS := $(addprefix $(OBJDIR)/, $(PERV_OBJECTS)) + +libperv.a: perv + $(AR) crs $(OBJDIR)/libperv.a $(OBJDIR)/*.o + +.PHONY: clean perv +perv: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C new file mode 100644 index 00000000..e850723f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C @@ -0,0 +1,173 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_dcc_skewadjust_setup.C +/// +/// @brief Drop DCCs reset and bypass, Drop skewadjust reset and bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE:SGPE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_hcd_cache_dcc_skewadjust_setup.H" +#include <p9_perv_scom_addresses.H> +#include <p9_quad_scom_addresses.H> + + + + +fapi2::ReturnCode p9_hcd_cache_dcc_skewadjust_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_cache) +{ + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = i_cache.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = i_cache.getParent<fapi2::TARGET_TYPE_PERV>(); + auto l_core_functional_vector = i_cache.getChildren<fapi2::TARGET_TYPE_CORE>(fapi2::TARGET_STATE_FUNCTIONAL); + uint8_t l_attr_chip_unit_pos = 0; + fapi2::buffer<uint64_t> l_data64; + + + FAPI_DBG("Entering ..."); + + FAPI_DBG("Release L2-0, L2-1 DC Adjust reset"); + l_data64.flush<1>(); + l_data64.clearBit<23>(); + l_data64.clearBit<24>(); + FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); + + for(auto it : l_core_functional_vector) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + it.getParent<fapi2::TARGET_TYPE_PERV>(), + l_attr_chip_unit_pos)); + + FAPI_DBG("Release CORE DC Adjust reset"); + l_data64.flush<1>(); + l_data64.clearBit<2>(); + FAPI_TRY(fapi2::putScom(l_chip, (C_NET_CTRL0_WAND + (0x1000000 * (l_attr_chip_unit_pos - 0x20))) , + l_data64)); + } + + FAPI_DBG("Scan eq_ana_bndy_bucket_0 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_0, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_0)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_1 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_1)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_2 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_2, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_2)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_3 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_3, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_3)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_4 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_4, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_4)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_5 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_5, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_5)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_6 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_6, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_6)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_7 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_7, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_7)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_8 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_8, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_8)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_9 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_9, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_9)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_10 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_10, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_10)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_11 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_11, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_11)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_12 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_12, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_12)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_13 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_13, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_13)"); + + FAPI_DBG("Release DCC bypass"); + l_data64.flush<1>(); + l_data64.clearBit<1>(); + FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_DBG("Scan eq_ana_bndy_bucket_14 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_14)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_15 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_15)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_16 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_16)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_17 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_17)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_18 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_18)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_19 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_19)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_20 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_20)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_21 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_21)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_22 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_22)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_23 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_23)"); + + FAPI_DBG("Release Progdly bypass"); + l_data64.flush<1>(); + l_data64.clearBit<2>(); + FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_DBG("Scan eq_ana_bndy_bucket_24 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_24)"); + FAPI_DBG("Scan eq_ana_bndy_bucket_25 ring"); + FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (eq_ana_bndy_bucket_25)"); + + FAPI_DBG("Exiting ..."); +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H new file mode 100644 index 00000000..c6a0c6f2 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_hcd_cache_dcc_skewadjust_setup.H +/// +/// @brief Drop DCCs reset and bypass, Drop skewadjust reset and bypass +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_HCD_CACHE_DCC_SKEWADJUST_SETUP_H_ +#define _P9_HCD_CACHE_DCC_SKEWADJUST_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_hcd_cache_dcc_skewadjust_setup_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief * Start Clocks clock region = AN only +/// * Drop DCCs reset +/// Setup 6 DCCs in parallel (commands over scan with setpulse, scan region = ANEP) +/// * Drop DCCs bypass +/// * Additional DCC setup step (commands over scan with setpulse, scan region = ANEP) +/// * Drop SkewAdjust reset +/// * Setup Skewadjust (commands over scan with setpulse, scan region = ANEP) +/// * Drop SkewAdjust bypass +/// * Additional SkewAdjust setup step (commands over scan with setpulse, scan region = ANEP) +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_EQ target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_hcd_cache_dcc_skewadjust_setup(const + fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C new file mode 100644 index 00000000..364d4013 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C @@ -0,0 +1,479 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_perv_sbe_cmn.C +/// +/// @brief Modules for scan 0 and array init +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_perv_sbe_cmn.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_quad_scom_addresses_fld.H> +#include <p9_const_common.H> + + +enum P9_PERV_SBE_CMN_Private_Constants +{ + P9_OPCG_DONE_SCAN0_POLL_COUNT = 200, // Scan0 Poll count + P9_OPCG_DONE_SCAN0_HW_NS_DELAY = 16000, // unit is nano seconds [min : 8k cycles x 4 = 8000/2 x 4 = 16000 x 10(-9) = 16 us + // max : 8k cycles = (8000/25) x 10 (-6) = 320 us] + P9_OPCG_DONE_SCAN0_SIM_CYCLE_DELAY = 800000, // unit is cycles, to match the poll count change ( 10000 * 8 ) + P9_OPCG_DONE_ARRAYINIT_HW_NS_DELAY = 200000, // unit is nano seconds [min : 400k/2 = 200k ns = 200 us + // max : 200k /25 = 8000 us = 8 ms] + P9_OPCG_DONE_ARRAYINIT_POLL_COUNT = 400, // Arrayinit Poll count + P9_OPCG_DONE_ARRAYINIT_SIM_CYCLE_DELAY = 1120000 // unit is cycles,to match the poll count change ( 280000 * 4 ) +}; + +/// @brief Seeprom array Init Module +/// --ABISTCLK_MUXSEL +/// --ABIST modes +/// --Setup BIST regions +/// --Setup all Clock Regions and Types +/// --Setup: +/// - loopcount +/// - OPCG engine start ABIST +/// - run-N mode +/// --Setup IDLE count +/// --OPCG go +/// --Poll OPCG done bit to check for completeness +/// --Clear: +/// - loopcount +/// - OPCG engine start ABIST +/// - run-N mode +/// --Clear all Clock Regions and Types +/// --Clear ABISTCLK_MUXSEL +/// --Clear BIST register +/// +/// +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target Targets all chiplets +/// @param[in] i_regions select clk regions +/// @param[in] i_loop_counter loop count value to set opcg run-N mode +/// @param[in] i_select_sram select sram abist mode +/// @param[in] i_select_edram Set edram abist mode +/// @param[in] i_start_abist_match_value match setup idle count value +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint64_t> i_loop_counter, + const bool i_select_sram, + const bool i_select_edram, + const fapi2::buffer<uint64_t> i_start_abist_match_value) +{ + fapi2::buffer<uint16_t> l_scan_count; + fapi2::buffer<uint16_t> l_misr_a_value; + fapi2::buffer<uint16_t> l_misr_b_value; + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint64_t> l_read_reg; + bool l_abist_check = false; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + fapi2::buffer<uint64_t> l_data64_clk_region; + FAPI_INF("p9_perv_sbe_cmn_array_init_module: Entering ..."); + + i_regions.extractToRight<5, 11>(l_regions); + + FAPI_DBG("Drop vital fence (moved to arrayinit from sacn0 module)"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + //CPLT_CTRL1.TC_VITL_REGION_FENCE = 0 + l_data64.setBit<C_CPLT_CTRL1_TC_VITL_REGION_FENCE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_DBG("Setup ABISTMUX_SEL"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("setup ABIST modes , BIST REGIONS:%#018lX", i_regions); + //Setting BIST register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_BIST, l_data64)); + l_data64.clearBit<0>(); //BIST.TC_BIST_START_TEST_DC = 0 + //BIST.TC_SRAM_ABIST_MODE_DC = i_select_sram + l_data64.writeBit<PERV_1_BIST_TC_SRAM_ABIST_MODE_DC>(i_select_sram); + //BIST.TC_EDRAM_ABIST_MODE_DC = i_select_edram + l_data64.writeBit<PERV_1_BIST_TC_EDRAM_ABIST_MODE_DC>(i_select_edram); + l_data64.insertFromRight<4, 11>(l_regions); //BIST.BIST_ALL_UNITS = l_regions + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_BIST, l_data64)); + FAPI_DBG("l_data64 value:%#018lX", l_data64); + + FAPI_DBG("Setup all Clock Domains and Clock Types"); + //Setting CLK_REGION register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CLK_REGION, + l_data64_clk_region)); + //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions + l_data64_clk_region.insertFromRight<4, 11>(l_regions); + l_data64_clk_region.setBit<48, 3>(); //CLK_REGION.SEL_THOLD_ALL = 0b111 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, + l_data64_clk_region)); + + FAPI_DBG("Drop Region fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_DBG("Setup: loopcount , OPCG engine start ABIST, run-N mode"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.setBit<PERV_1_OPCG_REG0_RUNN_MODE>(); //OPCG_REG0.RUNN_MODE = 1 + l_data64.setBit<14>(); //OPCG_REG0.OPCG_STARTS_BIST = 1 + l_data64.insertFromRight<PERV_1_OPCG_REG0_LOOP_COUNT, PERV_1_OPCG_REG0_LOOP_COUNT_LEN>(( + uint64_t)(i_loop_counter)); //OPCG_REG0.LOOP_COUNT = i_loop_counter + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + i_start_abist_match_value.extractToRight<0, 12>(l_scan_count); + i_start_abist_match_value.extractToRight<12, 12>(l_misr_a_value); + i_start_abist_match_value.extractToRight<24, 12>(l_misr_b_value); + + FAPI_DBG("Setup IDLE count"); + //Setting OPCG_REG1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG1, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_REG1_SCAN_COUNT, PERV_1_OPCG_REG1_SCAN_COUNT_LEN> + (l_scan_count); //OPCG_REG1.SCAN_COUNT = l_scan_count + l_data64.insertFromRight<PERV_1_OPCG_REG1_MISR_A_VAL, PERV_1_OPCG_REG1_MISR_A_VAL_LEN> + (l_misr_a_value); //OPCG_REG1.MISR_A_VAL = l_misr_a_value + l_data64.insertFromRight<PERV_1_OPCG_REG1_MISR_B_VAL, PERV_1_OPCG_REG1_MISR_B_VAL_LEN> + (l_misr_b_value); //OPCG_REG1.MISR_B_VAL = l_misr_b_value + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG1, l_data64)); + + FAPI_DBG("opcg go"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.setBit<1>(); //OPCG_REG0.OPCG_GO = 1 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); + l_timeout = P9_OPCG_DONE_ARRAYINIT_POLL_COUNT; + + //UNTIL CPLT_STAT0.CC_CTRL_OPCG_DONE_DC == 1 + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_OPCG_DONE_DC + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(P9_OPCG_DONE_ARRAYINIT_HW_NS_DELAY, + P9_OPCG_DONE_ARRAYINIT_SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::SBE_ARRAYINIT_POLL_THRESHOLD_ERR(), + "ERROR:OPCG DONE BIT NOT SET"); + + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, + l_read_reg)); //l_read_reg = CPLT_STAT0 + + if ( i_select_sram ) + { + FAPI_DBG("Checking sram abist done"); + FAPI_ASSERT(l_read_reg.getBit<0>() == 1, + fapi2::SRAM_ABIST_DONE_BIT_ERR() + .set_READ_ABIST_DONE(l_abist_check), + "ERROR:SRAM_ABIST_DONE_BIT_NOT_SET"); + } + + if ( i_select_edram ) + { + FAPI_DBG("Checking edram abist done"); + FAPI_ASSERT(l_read_reg.getBit<1>() == 1, + fapi2::EDRAM_ABIST_DONE_BIT_ERR() + .set_READ_ABIST_DONE(l_abist_check), + "ERROR:EDRAM_ABIST_DONE_BIT_NOT_SET"); + } + + //oaim_poll_done + { + FAPI_DBG("OPCG done, clear Run-N mode"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.clearBit<PERV_1_OPCG_REG0_RUNN_MODE>(); //OPCG_REG0.RUNN_MODE = 0 + l_data64.clearBit<14>(); //OPCG_REG0.OPCG_STARTS_BIST = 0 + l_data64.clearBit<PERV_1_OPCG_REG0_LOOP_COUNT, PERV_1_OPCG_REG0_LOOP_COUNT_LEN>(); //OPCG_REG0.LOOP_COUNT = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("clear all clock REGIONS and type"); + //Setting CLK_REGION register value + //CLK_REGION = 0 + l_data64_clk_region = 0; //using variable to keep register data + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, + l_data64_clk_region)); + + FAPI_DBG("clear ABISTCLK_MUXSEL"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_DBG("clear BIST REGISTER"); + //Setting BIST register value + //BIST = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_BIST, 0)); + } + + FAPI_INF("p9_perv_sbe_cmn_array_init_module: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Region value settings +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target ATTR_PG of the corresponding chiplet +/// @param[in] i_regions_value regions except vital and pll +/// @param[out] o_regions_value regions value +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_16(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint16_t>& o_regions_value) +{ + fapi2::buffer<uint32_t> l_read_attr = 0; + fapi2::buffer<uint32_t> l_read_attr_invert = 0; + fapi2::buffer<uint32_t> l_read_attr_shift1_right = 0; + FAPI_INF("p9_perv_sbe_cmn_regions_setup_16: Entering ..."); + + FAPI_DBG("Reading ATTR_PG"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chip, l_read_attr)); + FAPI_DBG("ATTR_PG Value : %#018lX", l_read_attr); + + FAPI_DBG("i_regions_value input from calling function: %#018lX", + i_regions_value); + + if ( l_read_attr == 0x0 ) + { + o_regions_value = i_regions_value; + } + else + { + l_read_attr_invert = l_read_attr.invert(); + FAPI_DBG("ATTR_PG inverted: %#018lX", l_read_attr_invert); + l_read_attr_shift1_right = (l_read_attr_invert >> 1); + FAPI_DBG("ATTR_PG inverted and shifted right by 1 %#018lX", + l_read_attr_shift1_right); + + o_regions_value = (i_regions_value & l_read_attr_shift1_right); + } + + FAPI_INF("p9_perv_sbe_cmn_regions_setup_16: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Region value settings +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_regions_value regions except vital and pll +/// @param[out] o_regions_value Regions value +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_64(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint64_t>& o_regions_value) +{ + fapi2::buffer<uint32_t> l_read_attr = 0; + fapi2::buffer<uint32_t> l_read_attr_invert = 0; + fapi2::buffer<uint32_t> l_read_attr_shift1_right = 0; + fapi2::buffer<uint64_t> l_temp = 0; + FAPI_INF("p9_perv_sbe_cmn_regions_setup_64: Entering ..."); + + FAPI_DBG("Reading ATTR_PG"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_read_attr)); + FAPI_DBG("ATTR_PG Value : %#018lX", l_read_attr); + + FAPI_DBG("i_regions_value input from calling function: %#018lX", + i_regions_value); + + if ( l_read_attr == 0x0 ) + { + o_regions_value = (i_regions_value | l_temp); + } + else + { + l_read_attr_invert = l_read_attr.invert(); + FAPI_DBG("ATTR_PG inverted: %#018lX", l_read_attr_invert); + l_read_attr_shift1_right = (l_read_attr_invert >> 1); + FAPI_DBG("ATTR_PG inverted and shifted right by 1 %#018lX", + l_read_attr_shift1_right); + + o_regions_value = (i_regions_value & l_read_attr_shift1_right); + } + + FAPI_INF("p9_perv_sbe_cmn_regions_setup_64: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Seeprom scan0 module +/// --Raise VITAL clock region fence +/// --Write Clock Region Register +/// --Write Scan Select Register +/// --set OPCG_REG0 register bit 0='0' +/// --set OPCG_REG0 register bit 2 = '1' +/// --Poll OPCG done bit to check for scan0 completeness +/// --clear clock region register +/// --clear scan select register +/// --Drop VITAL fence +/// +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target Targets for all chiplets +/// @param[in] i_regions set the clk region +/// @param[in] i_scan_types set scan types region +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint16_t> i_scan_types) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint16_t> l_scan_types; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_perv_sbe_cmn_scan0_module: Entering ..."); + + i_regions.extractToRight<5, 11>(l_regions); + i_scan_types.extractToRight<4, 12>(l_scan_types); + + FAPI_DBG("raise Vital clock region fence"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + //CPLT_CTRL1.TC_VITL_REGION_FENCE = 1 + l_data64.setBit<C_CPLT_CTRL1_TC_VITL_REGION_FENCE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64)); + + FAPI_DBG("Raise region fences for scanned regions"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + l_data64.setBit<4, 11>(); //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = 0b11111111111 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64)); + + FAPI_DBG("Setup all Clock Domains and Clock Types"); + //Setting CLK_REGION register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CLK_REGION, l_data64)); + //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + l_data64.setBit<48, 3>(); //CLK_REGION.SEL_THOLD_ALL = 0b111 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, l_data64)); + + FAPI_DBG("Write scan select register"); + //Setting SCAN_REGION_TYPE register value + l_data64.flush<0>(); //SCAN_REGION_TYPE = 0 + //SCAN_REGION_TYPE.SCAN_REGION_ALL_UNITS = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + //SCAN_REGION_TYPE.SCAN_ALL_TYPES = l_scan_types + l_data64.insertFromRight<48, 12>(l_scan_types); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SCAN_REGION_TYPE, l_data64)); + + FAPI_DBG("set OPCG_REG0 register bit 0='0'"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.clearBit<PERV_1_OPCG_REG0_RUNN_MODE>(); //OPCG_REG0.RUNN_MODE = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("trigger Scan0"); + //Setting OPCG_REG0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + l_data64.setBit<PERV_1_OPCG_REG0_RUN_SCAN0>(); //OPCG_REG0.RUN_SCAN0 = 1 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64)); + + FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); + l_timeout = P9_OPCG_DONE_SCAN0_POLL_COUNT; + + //UNTIL CPLT_STAT0.CC_CTRL_OPCG_DONE_DC == 1 + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_OPCG_DONE_DC + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(P9_OPCG_DONE_SCAN0_HW_NS_DELAY, + P9_OPCG_DONE_SCAN0_SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::SBE_SCAN0_DONE_POLL_THRESHOLD_ERR(), + "ERROR:OPCG DONE BIT NOT SET"); + + //os0m_poll_done + { + FAPI_DBG("clear all clock REGIONS and type"); + //Setting CLK_REGION register value + //CLK_REGION = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, 0)); + + FAPI_DBG("Clear Scan Select Register"); + //Setting SCAN_REGION_TYPE register value + //SCAN_REGION_TYPE = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SCAN_REGION_TYPE, 0)); + } + + FAPI_INF("p9_perv_sbe_cmn_scan0_module: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H new file mode 100644 index 00000000..b2472eb3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_perv_sbe_cmn.H +/// +/// @brief Modules for scan 0 and array init +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_PERV_SBE_CMN_H_ +#define _P9_PERV_SBE_CMN_H_ + + +#include <fapi2.H> + + +fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint64_t> i_loop_counter, + const bool i_select_sram, + const bool i_select_edram, + const fapi2::buffer<uint64_t> i_start_abist_match_value); + +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_16(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint16_t>& o_regions_value); + +fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_64(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions_value, + fapi2::buffer<uint64_t>& o_regions_value); + +fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint16_t> i_scan_types); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C new file mode 100644 index 00000000..d11fe6bf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -0,0 +1,950 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_ram_core.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_core.C +/// @brief Class that implements the base ramming capability +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <p9_ram_core.H> +#include "p9_quad_scom_addresses.H" +#include "p9_quad_scom_addresses_fld.H" + +// identifiers for special registers +const uint32_t RAM_REG_NIA = 2000; +const uint32_t RAM_REG_MSR = 2001; +const uint32_t RAM_REG_CR = 2002; +const uint32_t RAM_REG_FPSCR = 2003; + +// opcode for ramming +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD = 0x7C1543A6; +const uint32_t OPCODE_MTSPR_FROM_GPR1_TO_SPRD = 0x7C3543A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR0 = 0x7C1542A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR1 = 0x7C3542A6; +const uint32_t OPCODE_MFSPR_FROM_SPR0_TO_GPR0 = 0x7C0002A6; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPR0 = 0x7C0003A6; +const uint32_t OPCODE_MFFPRD_FROM_FPR0_TO_GPR0 = 0x7C000066; +const uint32_t OPCODE_MTFPRD_FROM_GPR0_TO_FPR0 = 0x7C000166; +const uint32_t OPCODE_MFVSRD_FROM_VSR0_TO_GPR0 = 0x7C000066; +const uint32_t OPCODE_MFVSRD_FROM_VSR32_TO_GPR0 = 0x7C000067; +const uint32_t OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0 = 0x7C000266; +const uint32_t OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0 = 0x7C000267; +const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0 = 0x7C010366; +const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32 = 0x7C010367; +const uint32_t OPCODE_MFSPR_FROM_LR_TO_GPR0 = 0x7C0802A6; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_LR = 0x7C0803A6; +const uint32_t OPCODE_MTMSR_L0 = 0x7C000124; +const uint32_t OPCODE_MTMSRD_L0 = 0x7C000164; +const uint32_t OPCODE_MTSPR_IAMR = 0x7C1D0BA6; +const uint32_t OPCODE_MTSPR_PIDR = 0x7C100BA6; +const uint32_t OPCODE_MTSPR_LPIDR = 0x7C1F4BA6; +const uint32_t OPCODE_MTSPR_LPCR = 0x7C1E4BA6; +const uint32_t OPCODE_MTSPR_MMCRA = 0x7C12C3A6; +const uint32_t OPCODE_MTSPR_MMCR1 = 0x7C1EC3A6; +const uint32_t OPCODE_MTSPR_SEIDBAR = 0x7C1F7BA6; +const uint32_t OPCODE_MTSPR_XER = 0x7C0103A6; +const uint32_t OPCODE_MFSPR_XER = 0x7C0102A6; +const uint32_t OPCODE_MFFS = 0xFC00048E; +const uint32_t OPCODE_SLBMFEE = 0x7C000726; +const uint32_t OPCODE_SLBMFEV = 0x7C0006A6; +const uint32_t OPCODE_DCBZ = 0x7C0007EC; +const uint32_t OPCODE_DCBF = 0x7C0000AC; +const uint32_t OPCODE_LD = 0xE8000000; +const uint32_t OPCODE_STD = 0xF8000000; +const uint32_t OPCODE_LFD = 0xC8000000; +const uint32_t OPCODE_STFD = 0xD8000000; +const uint32_t OPCODE_LVX = 0x7C0000CE; +const uint32_t OPCODE_STVX = 0x7C0001CE; +const uint32_t OPCODE_LXVD2X = 0x7C000698; +const uint32_t OPCODE_STXVD2X = 0x7C000798; +const uint32_t OPCODE_MFMSR_TO_GPR0 = 0x7C0000A6; +const uint32_t OPCODE_MFCR_TO_GPR0 = 0x7C000026; +const uint32_t OPCODE_MTCRF_FROM_GPR0 = 0x7C0FF120; +const uint32_t OPCODE_MTFSF_FROM_GPR0 = 0xFE00058E; + +// TODO: make sure these special PPC are final version in PC workbook table 9-2 +const uint32_t OPCODE_MFNIA_RT = 0x001ac804; +const uint32_t OPCODE_MTNIA_LR = 0x4c1e00a4; +const uint32_t OPCODE_GPR_MOVE = 0x00000010; +const uint32_t OPCODE_VSR_MOVE_HI = 0x00000110; +const uint32_t OPCODE_VSR_MOVE_LO = 0x00000210; +const uint32_t OPCODE_XER_MOVE = 0x00000310; +const uint32_t OPCODE_CR_MOVE = 0x00000410; + +// poll count for check ram status +const uint32_t RAM_CORE_STAT_POLL_CNT = 10; + +// Scom register field +// TODO: replace the const with FLD macro define when it's ready +const uint32_t C_RAM_MODEREG_ENABLE = 0; +const uint32_t C_RAS_STATUS_CORE_MAINT = 0; +const uint32_t C_THREAD_INFO_VTID0_ACTIVE = 0; +const uint32_t C_RAM_CTRL_VTID = 0; +const uint32_t C_RAM_CTRL_VTID_LEN = 2; +const uint32_t C_RAM_CTRL_PREDECODE = 2; +const uint32_t C_RAM_CTRL_PREDECODE_LEN = 4; +const uint32_t C_RAM_CTRL_INSTRUCTION = 8; +const uint32_t C_RAM_CTRL_INSTRUCTION_LEN = 32; +const uint32_t C_RAM_STATUS_ACCESS_DURING_RECOVERY = 0; +const uint32_t C_RAM_STATUS_COMPLETION = 1; +const uint32_t C_RAM_STATUS_EXCEPTION = 2; +const uint32_t C_RAM_STATUS_LSU_EMPTY = 3; + +//----------------------------------------------------------------------------------- +// Function definitions +//----------------------------------------------------------------------------------- +RamCore::RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread) +{ + iv_target = i_target; + iv_thread = i_thread; + iv_ram_enable = false; + iv_ram_scr0_save = false; + iv_ram_setup = false; + iv_ram_err = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; + iv_backup_buf0 = 0; + iv_backup_buf1 = 0; + iv_backup_buf2 = 0; +} + +RamCore::~RamCore() +{ + if(iv_ram_setup) + { + FAPI_ERR("RamCore Destructor error: Ram is still in active state!!!"); + } +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_setup() +{ + FAPI_DBG("Start ram setup"); + fapi2::buffer<uint64_t> l_data = 0; + uint32_t l_opcode = 0; + bool l_thread_active = false; + uint8_t l_thread_stop = 0; + + // set RAM_MODEREG Scom to enable RAM mode + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data)); + l_data.setBit<C_RAM_MODEREG_ENABLE>(); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); + + // read RAS_STATUS Scom to check the thread is stopped for ramming + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_RAS_STATUS, l_data)); + FAPI_DBG("RAS_STATUS:%#lx", l_data()); + FAPI_TRY(l_data.extractToRight(l_thread_stop, C_RAS_STATUS_CORE_MAINT + 8 * iv_thread, 2)); + + FAPI_ASSERT(l_thread_stop == 3, + fapi2::P9_RAM_THREAD_NOT_STOP_ERR() + .set_THREAD(iv_thread), + "Thread to perform ram is not stopped"); + + // read THREAD_INFO Scom to check the thread is active for ramming + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_THREAD_INFO, l_data)); + FAPI_DBG("THREAD_INFO:%#lx", l_data()); + FAPI_TRY(l_data.extractToRight(l_thread_active, C_THREAD_INFO_VTID0_ACTIVE + iv_thread, 1)); + + FAPI_ASSERT(l_thread_active, + fapi2::P9_RAM_THREAD_INACTIVE_ERR() + .set_THREAD(iv_thread), + "Thread to perform ram is inactive"); + + iv_ram_enable = true; + + // backup registers SCR0/GPR0/GPR1/LR + //SCR0->iv_backup_buf0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf0)); + iv_ram_scr0_save = true; + + //GPR0->iv_backup_buf1 + //1.setup SPRC to use SCRO as SPRD + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + //2.create mtsprd<gpr0> opcode, ram into thread to get GPR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR0 from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf1)); + + //GPR1->iv_backup_buf2 + //1.create mtsprd<gpr1> opcode, ram into thread to get GPR1 + l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get GPR1 from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf2)); + + iv_ram_setup = true; + +fapi_try_exit: + + // Error happened and SCR0 saved, to restore SCR0 + // Do not use "FAPI_TRY" to avoid endless loop + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && iv_ram_scr0_save) + { + fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0); + } + + FAPI_DBG("Exiting ram setup"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_cleanup() +{ + FAPI_DBG("Start ram cleanup"); + uint32_t l_opcode = 0; + fapi2::buffer<uint64_t> l_data = 0; + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to cleanup ram without setup before"); + + // setup SPRC to use SCRO as SPRD + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + // restore GPR1 + if(!iv_write_gpr1) + { + //iv_backup_buf2->GPR1 + //1.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf2)); + + //2.create mfsprd<gpr1> opcode, ram into thread to restore GPR1 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + + // restore GPR0 + if(!iv_write_gpr0) + { + //iv_backup_buf1->GPR0 + //1.put restore data into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf1)); + + //2.create mfsprd<gpr0> opcode, ram into thread to restore GPR0 + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + + //iv_backup_buf0->SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); + + // set RAM_MODEREG Scom to clear RAM mode + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data)); + l_data.clearBit<C_RAM_MODEREG_ENABLE>(); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); + + iv_ram_enable = false; + iv_ram_scr0_save = false; + iv_ram_setup = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; + +fapi_try_exit: + FAPI_DBG("Exiting ram cleanup"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::ram_opcode(const uint32_t i_opcode, const bool i_allow_mult) +{ + FAPI_DBG("Start ram opcode"); + fapi2::buffer<uint64_t> l_data = 0; + uint8_t l_predecode = 0; + uint32_t l_poll_count = RAM_CORE_STAT_POLL_CNT; + bool l_is_load_store = false; + + // check the opcode for load/store + l_is_load_store = is_load_store(i_opcode); + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_enable, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to ram opcode without enable RAM mode before"); + + // write RAM_CTRL Scom for ramming the opcode + l_data.insertFromRight<C_RAM_CTRL_VTID, C_RAM_CTRL_VTID_LEN>(iv_thread); + l_predecode = gen_predecode(i_opcode); + l_data.insertFromRight<C_RAM_CTRL_PREDECODE, C_RAM_CTRL_PREDECODE_LEN>(l_predecode); + l_data.insertFromRight<C_RAM_CTRL_INSTRUCTION, C_RAM_CTRL_INSTRUCTION_LEN>(i_opcode); + FAPI_TRY(fapi2::putScom(iv_target, C_RAM_CTRL, l_data)); + + // poll RAM_STATUS_REG Scom for the completion + l_data.flush<0>(); + + while(1) + { + FAPI_TRY(fapi2::getScom(iv_target, C_RAM_STATUS, l_data)); + + // attempting to ram during recovery + FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_ACCESS_DURING_RECOVERY>(), + fapi2::P9_RAM_STATUS_IN_RECOVERY_ERR(), + "Attempting to ram during recovery"); + + // exception or interrupt + FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_EXCEPTION>(), + fapi2::P9_RAM_STATUS_EXCEPTION_ERR(), + "Exception or interrupt happened during ramming"); + + // load/store opcode need to check LSU empty and PPC complete + if (l_is_load_store) + { + if(l_data.getBit<C_RAM_STATUS_COMPLETION>() && l_data.getBit<C_RAM_STATUS_LSU_EMPTY>()) + { + FAPI_DBG("ram_opcode:: RAM is done"); + break; + } + } + else + { + if(l_data.getBit<C_RAM_STATUS_COMPLETION>()) + { + FAPI_DBG("ram_opcode:: RAM is done"); + break; + } + } + + --l_poll_count; + + FAPI_ASSERT(l_poll_count > 0, + fapi2::P9_RAM_STATUS_POLL_THRESHOLD_ERR(), + "Timeout for ram to complete, poll count expired"); + } + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + + if(fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) + { + iv_ram_err = true; + } + + FAPI_DBG("Exiting ram opcode"); + return fapi2::current_err; +} + +//----------------------------------------------------------------------------------- +uint8_t RamCore::gen_predecode(const uint32_t i_opcode) +{ + //TODO: make sure they are final version in PC workbook table 9-1 and 9-2 + uint8_t l_predecode = 0; + uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE; + uint32_t l_opcode_pattern1 = i_opcode & 0xFC1FFFFE; + + if((i_opcode == OPCODE_MFNIA_RT) || + (i_opcode == OPCODE_GPR_MOVE) || + (i_opcode == OPCODE_VSR_MOVE_HI) || + (i_opcode == OPCODE_VSR_MOVE_LO) || + (i_opcode == OPCODE_XER_MOVE) || + (i_opcode == OPCODE_CR_MOVE)) + { + l_predecode = 2; + } + else if((i_opcode == OPCODE_MTNIA_LR) || + (l_opcode_pattern0 == OPCODE_MTMSR_L0) || + (l_opcode_pattern0 == OPCODE_MTMSRD_L0)) + { + l_predecode = 8; + } + else if((l_opcode_pattern1 == OPCODE_MTSPR_IAMR) || + (l_opcode_pattern1 == OPCODE_MTSPR_PIDR) || + (l_opcode_pattern1 == OPCODE_MTSPR_LPIDR) || + (l_opcode_pattern1 == OPCODE_MTSPR_LPCR) || + (l_opcode_pattern1 == OPCODE_MTSPR_MMCRA) || + (l_opcode_pattern1 == OPCODE_MTSPR_MMCR1) || + (l_opcode_pattern1 == OPCODE_MTSPR_SEIDBAR) || + (l_opcode_pattern1 == OPCODE_MTSPR_XER) || + (l_opcode_pattern1 == OPCODE_MFSPR_XER) || + (l_opcode_pattern0 == OPCODE_MFFS) || + (l_opcode_pattern0 == OPCODE_SLBMFEE) || + (l_opcode_pattern0 == OPCODE_SLBMFEV)) + { + l_predecode = 4; + } + + return l_predecode; +} + +//----------------------------------------------------------------------------------- +bool RamCore::is_load_store(const uint32_t i_opcode) +{ + //TODO: make sure they are final version in PC workbook table 9-1 + bool l_load_store = false; + uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE; + uint32_t l_opcode_pattern1 = i_opcode & 0xFC000000; + + if((l_opcode_pattern0 == OPCODE_DCBZ) || + (l_opcode_pattern0 == OPCODE_DCBF) || + (l_opcode_pattern1 == OPCODE_LD) || + (l_opcode_pattern1 == OPCODE_LFD) || + (l_opcode_pattern1 == OPCODE_STD) || + (l_opcode_pattern1 == OPCODE_LFD) || + (l_opcode_pattern1 == OPCODE_STFD) || + (l_opcode_pattern0 == OPCODE_LVX) || + (l_opcode_pattern0 == OPCODE_STVX) || + (l_opcode_pattern0 == OPCODE_LXVD2X) || + (l_opcode_pattern0 == OPCODE_STXVD2X)) + { + l_load_store = true; + } + + return l_load_store; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, + fapi2::buffer<uint64_t>* o_buffer, const bool i_allow_mult) +{ + FAPI_DBG("Start get register"); + uint32_t l_opcode = 0; + uint32_t l_spr_regnum_lo = 0; + uint32_t l_spr_regnum_hi = 0; + fapi2::buffer<uint64_t> l_backup_gpr0 = 0; + fapi2::buffer<uint64_t> l_backup_fpr0 = 0; + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to get register without setup before"); + + //backup GPR0 if it is written + if(iv_write_gpr0) + { + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0)); + } + + // get register value + if(i_type == REG_GPR) + { + //1.create mtsprd<i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_type == REG_SPR) + { + if(i_reg_num == RAM_REG_NIA) + { + //1.ram MFNIA_RT opcode + l_opcode = OPCODE_MFNIA_RT; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get NIA from GPR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_MSR) + { + //1.create mfmsr opcode, ram into thread + l_opcode = OPCODE_MFMSR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get MSR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_CR) + { + //1.create mfcr opcode, ram into thread + l_opcode = OPCODE_MFCR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get MSR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_FPSCR) + { + //1.backup FPR0 + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0)); + + //2.create mffs opcode, ram into thread + l_opcode = OPCODE_MFFS; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get FPSCR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + + //4.restore FPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else + { + //1.create mfspr<gpr0, i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPR0_TO_GPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 6); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + } + else if(i_type == REG_FPR) + { + //1.create mffprd<gpr0, i_reg_num>#SX=0 opcode, ram into thread + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + +#ifndef __PPE__ + else if(i_type == REG_VSR) + { + //1.create mfvsrd<gpr0, i_reg_num> opcode, ram into thread to get dw0 + if(i_reg_num < 32) + { + l_opcode = OPCODE_MFVSRD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MFVSRD_FROM_VSR32_TO_GPR0; + l_opcode += ((i_reg_num - 32) << 21); + } + + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get VSR dw0 value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + + //4.create mfvrld<gpr0, i_reg_num> opcode, ram into thread to get dw1 + if(i_reg_num < 32) + { + l_opcode = OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0; + l_opcode += ((i_reg_num - 32) << 21); + } + + FAPI_TRY(ram_opcode(l_opcode, true)); + + //5.create mtsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //6.get VSR dw1 value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[1])); + } + +#endif + else + { + FAPI_ASSERT(false, + fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR() + .set_REGTYPE(i_type), + "Type of reg is not supported"); + } + + //restore GPR0 if necessary + if(iv_write_gpr0) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + // Error happened and it's not ram error, call ram_cleanup to restore the backup registers + // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed + // Do not use "FAPI_TRY" to avoid endless loop + fapi2::ReturnCode first_err = fapi2::current_err; + + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup) + { + ram_cleanup(); + } + + FAPI_DBG("Exiting get register"); + return first_err; +} + +//----------------------------------------------------------------------------------- +fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, + const fapi2::buffer<uint64_t>* i_buffer, const bool i_allow_mult) +{ + FAPI_DBG("Start put register"); + uint32_t l_opcode = 0; + uint32_t l_spr_regnum_lo = 0; + uint32_t l_spr_regnum_hi = 0; + bool l_write_gpr0 = false; + fapi2::buffer<uint64_t> l_backup_lr = 0; + fapi2::buffer<uint64_t> l_backup_gpr0 = 0; + fapi2::buffer<uint64_t> l_backup_gpr1 = 0; + fapi2::buffer<uint64_t> l_backup_fpr0 = 0; + + // ram_setup + if(!i_allow_mult) + { + FAPI_TRY(ram_setup()); + } + + FAPI_ASSERT(iv_ram_setup, + fapi2::P9_RAM_NOT_SETUP_ERR(), + "Attempting to put register without setup before"); + + //backup GPR0 if it is written + if(iv_write_gpr0) + { + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0)); + } + +#ifndef __PPE__ + + //backup GPR1 if it is written + if(iv_write_gpr1 && (i_type == REG_VSR)) + { + l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr1)); + } + +#endif + + // put register value + if(i_type == REG_GPR) + { + //1.put GPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<i_reg_num> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + if(i_reg_num == 0) + { + iv_write_gpr0 = true; + l_write_gpr0 = true; + } + + if(i_reg_num == 1) + { + iv_write_gpr1 = true; + } + } + else if(i_type == REG_SPR) + { + if(i_reg_num == RAM_REG_NIA) + { + //1.backup LR + l_opcode = OPCODE_MFSPR_FROM_LR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_lr)); + + //2.put NIA value into LR + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.ram MTNIA_LR opcode + l_opcode = OPCODE_MTNIA_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //4.restore LR + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_lr)); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_MSR) + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtmsrd opcode, ram into thread + l_opcode = OPCODE_MTMSRD_L0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_CR) + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtcrf opcode, ram into thread + l_opcode = OPCODE_MTCRF_FROM_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_FPSCR) + { + //1.backup FPR0 + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0)); + + //2.put SPR value into GPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtfsf opcode, ram into thread + l_opcode = OPCODE_MTFSF_FROM_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //4.restore FPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtspr<i_reg_num, gpr0> opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 6); + FAPI_TRY(ram_opcode(l_opcode, true)); + } + } + else if(i_type == REG_FPR) + { + //1.put FPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtfprd<i_reg_num, gpr0>#TX=0 opcode, ram into thread + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + l_opcode += (i_reg_num << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#ifndef __PPE__ + else if(i_type == REG_VSR) + { + //1.put VSR dw1 value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[1])); + + //2.create mfsprd<gpr0> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.put VSR dw0 value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //4.create mfsprd<gpr1> opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + l_opcode += (1 << 21); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //5.create mtvsrdd<i_reg_num, gpr0, gpr1> opcode, ram into thread + if(i_reg_num < 32) + { + l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32; + l_opcode += ((i_reg_num - 32) << 21); + } + + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#endif + else + { + FAPI_ASSERT(false, + fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR() + .set_REGTYPE(i_type), + "Type of reg is not supported"); + } + + //restore GPR0 if necessary + if(iv_write_gpr0 && !l_write_gpr0) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#ifndef __PPE__ + + //restore GPR1 if necessary + if(iv_write_gpr1 && (i_type == REG_VSR)) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr1)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#endif + + // ram_cleanup + if(!i_allow_mult) + { + FAPI_TRY(ram_cleanup()); + } + +fapi_try_exit: + // Error happened and it's not ram error, call ram_cleanup to restore the backup registers + // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed + // Do not use "FAPI_TRY" to avoid endless loop + fapi2::ReturnCode first_err = fapi2::current_err; + + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup) + { + ram_cleanup(); + } + + FAPI_DBG("Exiting put register"); + return first_err; +} + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H new file mode 100644 index 00000000..46f0eaf7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H @@ -0,0 +1,153 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_ram_core.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//----------------------------------------------------------------------------------- +/// +/// @file p9_ram_core.H +/// @brief Class that implements the base ramming capability +/// +//----------------------------------------------------------------------------------- +// *HWP HWP Owner : Liu Yang Fan <shliuyf@cn.ibm.com> +// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com> +// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//----------------------------------------------------------------------------------- + +#ifndef _P9_RAM_CORE_H_ +#define _P9_RAM_CORE_H_ + +//----------------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------------- +#include <fapi2.H> + +//----------------------------------------------------------------------------------- +// Structure definitions +//----------------------------------------------------------------------------------- +// register access type +enum Enum_RegType +{ + REG_GPR, + REG_SPR, + REG_FPR, + REG_VSR +}; + + +class RamCore +{ + public: +//----------------------------------------------------------------------------------- +// Function prototype +//----------------------------------------------------------------------------------- +/// @brief Constructor of the class that implements the base ramming capability +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +// + RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread); + +//----------------------------------------------------------------------------------- +/// @brief Destructor of the class that implements the base ramming capability +// + ~RamCore(); + +//----------------------------------------------------------------------------------- +/// @brief Enable RAM mode and backup the registers(SCR0/GPR0/GPR1) that will be destroyed later during ramming +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_setup(); + +//----------------------------------------------------------------------------------- +/// @brief Perform the ram and check ram is done +/// @param[in] i_opcode => opcode to ram +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_opcode(const uint32_t i_opcode, const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Clear RAM mode and restore the backup registers +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode ram_cleanup(); + +//----------------------------------------------------------------------------------- +/// @brief Get a register value by ramming +/// @param[in] i_type => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register nubmer +/// @param[out] o_buffer => register value +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, fapi2::buffer<uint64_t>* o_buffer, + const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Put a register value by ramming +/// @param[in] i_type => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register nubmer +/// @param[in] i_buffer => register value +/// @param[in] i_allow_mult => indicate whether to setup and cleanup +/// true: only perform ram, not to call ram_setup and ram_cleanup +/// false: call ram_setup and ram_cleanup +/// @return FAPI2_RC_SUCCESS if success, else error code. +// + fapi2::ReturnCode put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, const fapi2::buffer<uint64_t>* i_buffer, + const bool i_allow_mult = false); + +//----------------------------------------------------------------------------------- +/// @brief Generate predecode for the opcode to ramming +/// @param[in] i_opcode => opcode to ram +/// @return the predecode +// + uint8_t gen_predecode(const uint32_t i_opcode); + +//----------------------------------------------------------------------------------- +/// @brief Check the opcode is load/store or not +/// @param[in] i_opcode => opcode to ram +/// @return TRUE if it is load/store +// + bool is_load_store(const uint32_t i_opcode); + + private: + fapi2::Target<fapi2::TARGET_TYPE_CORE> iv_target; // core target + uint8_t iv_thread; // thread number + bool iv_ram_enable; // ram mode is enabled + bool iv_ram_scr0_save; // SCR0 is saved when setup + bool iv_ram_setup; // ram mode is enabled and register backup is done + bool iv_ram_err; // error happened during ram + bool iv_write_gpr0; // putGPR0 operation is executed + bool iv_write_gpr1; // putGPR1 operatoin is executed + fapi2::buffer<uint64_t> iv_backup_buf0; // register backup data + fapi2::buffer<uint64_t> iv_backup_buf1; // register backup data + fapi2::buffer<uint64_t> iv_backup_buf2; // register backup data +}; + +#endif //_P9_RAM_CORE_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C new file mode 100644 index 00000000..79046f0e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C @@ -0,0 +1,185 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_arrayinit.C +/// +/// @brief array init procedure to be called with any chiplet target except TP,EP,EC +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_arrayinit.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +enum P9_SBE_ARRAYINIT_Private_Constants +{ + LOOP_COUNTER = 0x0000000000042FFF, + REGIONS_EXCEPT_VITAL_AND_PLL = 0x7FE, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCF, + SELECT_EDRAM = 0x0, + SELECT_SRAM = 0x1, + START_ABIST_MATCH_VALUE = 0x0000000F00000000 +}; + +static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions); + +static fapi2::ReturnCode p9_sbe_arrayinit_sdisn_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set); + +fapi2::ReturnCode p9_sbe_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint32_t> l_attr_pg; + fapi2::buffer<uint8_t> l_attr_read; + FAPI_INF("p9_sbe_arrayinit: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read)); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("set sdis_n"); + FAPI_TRY(p9_sbe_arrayinit_sdisn_setup(l_chplt_trgt, l_attr_read, true)); + + FAPI_DBG("Region setup"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_chplt_trgt, + REGIONS_EXCEPT_VITAL_AND_PLL, l_regions)); + FAPI_DBG("l_regions value: %#018lX ", l_regions); + + FAPI_DBG("Call proc_sbe_arryinit_scan0_and_arrayinit_module_function"); + FAPI_TRY(p9_sbe_arrayinit_scan0_and_arrayinit_module_function(l_chplt_trgt, + l_regions)); + + FAPI_DBG("clear sdis_n"); + FAPI_TRY(p9_sbe_arrayinit_sdisn_setup(l_chplt_trgt, l_attr_read, false)); + } + + FAPI_INF("p9_sbe_arrayinit: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --Run arrayinit on all enabled chiplets +/// --Scan flush 0 to all rings except GPTR, Time, Repair on all enabled chiplets +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_regions region value settings +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint16_t> i_regions) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_arrayinit_scan0_and_arrayinit_module_function: Entering ..."); + + FAPI_DBG("Check for chiplet enable"); + //Getting NET_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); + //l_read_reg = NET_CTRL0.CHIPLET_ENABLE + l_read_reg = l_data64.getBit<PERV_1_NET_CTRL0_CHIPLET_ENABLE>(); + + if ( l_read_reg ) + { + FAPI_DBG("run array_init module for all chiplet except TP, EC, EP"); + FAPI_TRY(p9_perv_sbe_cmn_array_init_module(i_target_chiplet, i_regions, + LOOP_COUNTER, SELECT_SRAM, SELECT_EDRAM, START_ABIST_MATCH_VALUE)); + + FAPI_DBG("run scan0 module for region except vital and pll, scan types except GPTR TIME REPR all chiplets except TP, EC, EP"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, i_regions, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + } + + FAPI_INF("p9_sbe_arrayinit_scan0_and_arrayinit_module_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Sdis_n setup +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr Attribute to decide the sdis setup +/// @param[in] i_set set or clear the LCBES condition +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_arrayinit_sdisn_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_arrayinit_sdisn_setup: Entering ..."); + + if ( i_attr ) + { + if ( i_set ) + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 1 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_OR, l_data64)); + } + else + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 0 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_CLEAR, l_data64)); + } + } + + FAPI_INF("p9_sbe_arrayinit_sdisn_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H new file mode 100644 index 00000000..9fc72c1b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_arrayinit.H +/// +/// @brief array init procedure to be called with any chiplet target except TP,EP,EC +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ARRAYINIT_H_ +#define _P9_SBE_ARRAYINIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_arrayinit_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Array Init function call for any chiplet Target except TP,EP,EC +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C new file mode 100644 index 00000000..ee741b8c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -0,0 +1,244 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_attr_setup.C +/// +/// @brief Read scratch Regs, update ATTR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_attr_setup.H" + +#include <p9_perv_scom_addresses.H> + +fapi2::ReturnCode p9_sbe_attr_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_scratch_reg = 0; + fapi2::buffer<uint64_t> l_read_scratch8 = 0; + fapi2::buffer<uint8_t> l_read_1 = 0; + fapi2::buffer<uint8_t> l_read_2 = 0; + fapi2::buffer<uint8_t> l_read_3 = 0; + fapi2::buffer<uint16_t> l_read_4 = 0; + fapi2::buffer<uint32_t> l_read_5 = 0; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::buffer<uint64_t> l_data64; + bool sbe_slave_chip = false; + fapi2::buffer<uint64_t> l_read_device_reg = 0; + FAPI_INF("p9_sbe_attr_setup: Entering ..."); + + FAPI_DBG("Read Scratch8 for validity of Scratch register"); + //Getting SCRATCH_REGISTER_8 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_8_SCOM, + l_read_scratch8)); //l_read_scratch8 = PIB.SCRATCH_REGISTER_8 + + //set_security_acess + { + fapi2::buffer<uint64_t> l_read_reg; + + FAPI_DBG("Reading ATTR_SECURITY_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECURITY_MODE, FAPI_SYSTEM, l_read_1)); + + if ( l_read_1.getBit<7>() == 0 ) + { + FAPI_DBG("Clear Security Access Bit"); + //Setting CBS_CS register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64)); + l_data64.clearBit<4>(); //PIB.CBS_CS.CBS_CS_SECURE_ACCESS_BIT = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64)); + } + + //Getting CBS_CS register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, + l_read_reg)); //l_read_reg = PIB.CBS_CS + + l_read_1 = 0; + l_read_1.writeBit<7>(l_read_reg.getBit<4>()); + + FAPI_DBG("Setting ATTR_SECURITY_ENABLE with the SAB state"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURITY_ENABLE, FAPI_SYSTEM, l_read_1)); + + } + //read_scratch1_reg + { + if ( l_read_scratch8.getBit<0>() ) + { + FAPI_DBG("Reading Scratch_reg1"); + //Getting SCRATCH_REGISTER_1 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_1 + + l_read_scratch_reg.extract<0, 6>(l_read_1); + l_read_scratch_reg.extract<8, 24>(l_read_5); + + FAPI_DBG("Setting up ATTR_EQ_GARD, ATTR_EC_GARD"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5)); + + l_read_1 = 0; + l_read_4 = 0; + } + } + //read_scratch2_reg + { + if ( l_read_scratch8.getBit<1>() ) + { + FAPI_DBG("Reading Scratch_reg2"); + //Getting SCRATCH_REGISTER_2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2 + + l_read_scratch_reg.extractToRight<0, 16>(l_read_4); + + FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); + } + } + + //read_scratch4_reg + { + if ( l_read_scratch8.getBit<3>() ) + { + FAPI_DBG("Reading Scratch_Reg4"); + //Getting SCRATCH_REGISTER_4 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_4 + + l_read_scratch_reg.extractToRight<0, 16>(l_read_4); + l_read_scratch_reg.extractToRight<24, 8>(l_read_1); + + FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); + + l_read_1 = 0; + l_read_4 = 0; + } + } + //read_scratch5_reg + { + if ( l_read_scratch8.getBit<4>() ) + { + FAPI_DBG("Reading Scratch_reg5"); + //Getting SCRATCH_REGISTER_5 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_5_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_5 + + if (l_read_scratch_reg.getBit<0>()) + { + l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED; + } + else + { + l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL; + } + + l_read_2.writeBit<7>(l_read_scratch_reg.getBit<1>()); + + if (l_read_scratch_reg.getBit<2>()) + { + l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE; + } + else + { + l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE; + } + + FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, + l_read_2)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_3)); + + l_read_1 = 0; + l_read_2 = 0; + l_read_3 = 0; + + if (l_read_scratch_reg.getBit<3>()) + { + l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE; + } + else + { + l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE; + } + + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, + l_read_1)); + + l_read_1 = 0; + } + } + //read_scratch6_reg + { + if ( l_read_scratch8.getBit<5>() ) + { + FAPI_DBG("Reading Scratch_reg6"); + //Getting SCRATCH_REGISTER_6 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_6 + + l_read_1 = 0; + sbe_slave_chip = l_read_scratch_reg.getBit<24>(); + + if ( !sbe_slave_chip ) // 0b0 == master + { + FAPI_DBG("Reading DEVICE_ID_REG value"); + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_DEVICE_ID_REG, l_read_device_reg)); + + if (!l_read_device_reg.getBit<40>()) + { + l_read_1.setBit<7>(); + } + } + + l_read_scratch_reg.extractToRight<26, 3>(l_read_2); + l_read_scratch_reg.extractToRight<29, 3>(l_read_3); + + FAPI_DBG("Setting up MASTER_CHIP, FABRIC_GROUP_ID and CHIP_ID"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip, + l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip, + l_read_2)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip, + l_read_3)); + + } + } + + FAPI_INF("p9_sbe_attr_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H new file mode 100644 index 00000000..0a5e2a09 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_attr_setup.H +/// +/// @brief Read scratch Regs, update ATTR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ATTR_SETUP_H_ +#define _P9_SBE_ATTR_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_attr_setup_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief HWP will read the contents of Byte 0 of scratch register 8 indicates validity of mailbox register +/// and call FAPI2 APIs to set the values into the corresponding platform ATTR +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_attr_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C new file mode 100644 index 00000000..1cd61c93 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master.C +/// +/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_check_master.H" +fapi2::ReturnCode p9_sbe_check_master(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_check_master: Entering ..."); + + FAPI_DBG("p9_sbe_check_master: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H new file mode 100644 index 00000000..88c3bf21 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master.H +/// +/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHECK_MASTER_H_ +#define _P9_SBE_CHECK_MASTER_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_check_master_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief If master continue, else enable runtime chipOps +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_check_master(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C new file mode 100644 index 00000000..4d28bdbd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C @@ -0,0 +1,134 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_check_master_stop15.H +/// @brief Check if the targeted core (master) is fully in STOP15 +/// +// *HWP HWP Owner : Greg Still <stillgsg@us.ibm.com> +// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : SBE +/// +/// High-level procedure flow: +/// @verbatim +/// - Read the STOP History Register from the target core +/// - Return SUCCESS if:: +/// - STOP_GATED is set (indicating it is stopped) +/// - STOP_TRANSITION is clear (indicating it is stable) +/// - ACT_STOP_LEVEL is at the appropriate value (either 11 (0xB) or 15 (0x15) +/// - Return PENDING if +/// - STOP_TRANSITION is set (indicating transtion is progress) +/// - Return ERROR if +/// - STOP_GATED is set, STOP_TRANSITION is clear and ACT_STOP_LEVEL is not +/// appropriate +/// - STOP_TRANSITION is clear but STOP_GATED is clear +/// - Hardware access errors +/// @endverbatim + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- +#include <p9_sbe_check_master_stop15.H> +#include <p9_pm_stop_history.H> +#include <p9_quad_scom_addresses.H> + +// ----------------------------------------------------------------------------- +// Function definitions +// ----------------------------------------------------------------------------- + +// See .H for documentation +fapi2::ReturnCode p9_sbe_check_master_stop15( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + FAPI_IMP("> p9_sbe_check_master_stop15"); + + fapi2::buffer<uint64_t> l_data64; + uint32_t l_stop_gated = 0; + uint32_t l_stop_transition = p9ssh::SSH_UNDEFINED; + uint32_t l_stop_requested_level = 0; // Running Level + uint32_t l_stop_actual_level = 0; // Running Level + + // Read the "Other" STOP History Register + FAPI_TRY(fapi2::getScom(i_target, C_PPM_SSHOTR, l_data64)); + + // Extract the field values + l_data64.extractToRight<p9ssh::STOP_GATED_START, + p9ssh::STOP_GATED_LEN>(l_stop_gated); + + l_data64.extractToRight<p9ssh::STOP_TRANSITION_START, + p9ssh::STOP_TRANSITION_LEN>(l_stop_transition); + + // Testing showed the above operation was sign extending into + // the l_stop_transition variable. + l_stop_transition &= 0x3; + + l_data64.extractToRight<p9ssh::STOP_REQUESTED_LEVEL_START, + p9ssh::STOP_REQUESTED_LEVEL_LEN>(l_stop_requested_level); + + l_data64.extractToRight<p9ssh::STOP_ACTUAL_LEVEL_START, + p9ssh::STOP_ACTUAL_LEVEL_LEN>(l_stop_actual_level); + +#ifndef __PPE__ + FAPI_DBG("GATED = %d; TRANSITION = %d (0x%X); REQUESTED_LEVEL = %d; ACTUAL_LEVEL = %d", + l_stop_gated, + l_stop_transition, l_stop_transition, + l_stop_requested_level, + l_stop_actual_level); +#endif + + // Check for valide reguest level + FAPI_ASSERT((l_stop_requested_level == 11 || l_stop_requested_level == 15), + fapi2::CHECK_MASTER_STOP15_INVALID_REQUEST_LEVEL() + .set_REQUESTED_LEVEL(l_stop_requested_level), + "Invalid requested STOP Level"); + + // Check for valid pending condition + FAPI_ASSERT(!(l_stop_transition == p9ssh::SSH_CORE_COMPLETE || + l_stop_transition == p9ssh::SSH_ENTERING ), + fapi2::CHECK_MASTER_STOP15_PENDING(), + "STOP 15 is still pending"); + + // Assert completion and the core gated condition. If not, something is off. + FAPI_ASSERT((l_stop_transition == p9ssh::SSH_COMPLETE && + l_stop_gated == p9ssh::SSH_GATED ), + fapi2::CHECK_MASTER_STOP15_INVALID_STATE() + .set_STOP_HISTORY(l_data64), + "STOP 15 error"); + + // Check for valid actual level + FAPI_ASSERT((l_stop_actual_level == 11 || l_stop_actual_level == 15), + fapi2::CHECK_MASTER_STOP15_INVALID_ACTUAL_LEVEL() + .set_ACTUAL_LEVEL(l_stop_actual_level), + "Invalid actual STOP Level"); + + FAPI_INF("SUCCESS!! Valid STOP entry state has been achieved.") + +fapi_try_exit: + FAPI_INF("< p9_sbe_check_master_stop15"); + + return fapi2::current_err; +} // END p9_sbe_check_master_stop15 + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H new file mode 100644 index 00000000..575536d9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_check_master_stop15.H +/// +///------------------------------------------------------------------------------ +// *HWP HWP Owner : Greg Still <stillgsg@us.ibm.com> +// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHECK_MASTER_STOP15_H_ +#define _P9_SBE_CHECK_MASTER_STOP15_H_ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9_sbe_check_master_stop15_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Check if the targeted core (master) is fully in STOP15 +/// +/// @param[in] i_target Reference to TARGET_TYPE_CORE target +/// +/// @return FAPI2_RC_SUCCESS if success +/// @return STOP15_PENDING STOP 15 not reached, but no error +/// HW state (still in progress) +/// @return Others indicate hardware failur +/// +extern "C" +{ + fapi2::ReturnCode + p9_sbe_check_master_stop15( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); +} + +#endif // _P9_SBE_CHECK_MASTER_STOP15_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C new file mode 100644 index 00000000..521078bd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C @@ -0,0 +1,70 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_init.C +/// +/// @brief init procedure for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_init.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_chiplet_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_init: Entering.."); + + FAPI_DBG("Check for XSTOP Bit"); + //Getting INTERRUPT_TYPE_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, l_data64)); + //l_read_reg = PIB.INTERRUPT_TYPE_REG.CHECKSTOP + l_read_reg = l_data64.getBit<2>(); + + FAPI_ASSERT(!(l_read_reg), + fapi2::CHECKSTOP_ERR() + .set_READ_CHECKSTOP(l_read_reg), + "ERROR:CHECKSTOP BIT GET SET "); + + FAPI_INF("p9_sbe_chiplet_init: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H new file mode 100644 index 00000000..72d20577 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_init.H +/// +/// @brief init procedure for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_INIT_H_ +#define _P9_SBE_CHIPLET_INIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_init_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief chiplet init function call on all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C new file mode 100644 index 00000000..a36fa629 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C @@ -0,0 +1,123 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_initf.C +/// +/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_pll_initf.H" +#include "p9_perv_scom_addresses.H" + +fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_chiplet_pll_initf: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_XBUS | + fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI), fapi2::TARGET_STATE_FUNCTIONAL)) + { + uint8_t l_unit_pos; + RingID l_ring_id = xb_pll_bndy; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_unit_pos), + "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)"); + + switch (l_unit_pos) + { + case 0x6: + FAPI_DBG("Scan xb_pll_bndy_ring"); + l_ring_id = xb_pll_bndy; + break; + + case 0x9: + FAPI_DBG("Scan ob0_pll_bndy ring"); + l_ring_id = ob0_pll_bndy; + break; + + case 0xa: + FAPI_DBG("Scan ob1_pll_bndy ring"); + l_ring_id = ob1_pll_bndy; + break; + + case 0xb: + FAPI_DBG("Scan ob2_pll_bndy ring"); + l_ring_id = ob2_pll_bndy; + break; + + case 0xc: + FAPI_DBG("Scan ob3_pll_bndy ring"); + l_ring_id = ob3_pll_bndy; + break; + + case 0xd: + FAPI_DBG("Scan pci0_pll_bndy ring"); + l_ring_id = pci0_pll_bndy; + break; + + case 0xe: + FAPI_DBG("Scan pci1_pll_bndy ring"); + l_ring_id = pci1_pll_bndy; + break; + + case 0xf: + FAPI_DBG("Scan pci2_pll_bndy ring"); + l_ring_id = pci2_pll_bndy; + break; + + default: + FAPI_ASSERT(false, + fapi2::P9_SBE_CHIPLET_PLL_INITF_INVALID_CHIPLET(). + set_TARGET(l_chplt_trgt). + set_UNIT_POS(l_unit_pos), + "Unexpected chiplet!"); + } + + FAPI_TRY(fapi2::putRing(i_target_chip, l_ring_id, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (ringID: %d)", l_ring_id); + + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Scan mc_pll_bndy_bucket_1 ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (mc_pll_bndy)"); + } + +fapi_try_exit: + FAPI_INF("p9_sbe_chiplet_pll_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H new file mode 100644 index 00000000..a45218b9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_initf.H +/// +/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_PLL_INITF_H_ +#define _P9_SBE_CHIPLET_PLL_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief If TRUE then skip MC chiplet +/// run scan0 module (scan region = PLL, scan_types = GPTR) +/// run scan0 module (scan region = PLL, scan_types = BNDY/FUNC) +/// Scan initialize PLL BNDY chain (chiplet =[CPLT], scan ring = PLL, scan type = BNDY) +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C new file mode 100644 index 00000000..a152c465 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C @@ -0,0 +1,427 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_setup.C +/// +/// @brief Setup PLL for Obus, Xbus, PCIe, DMI +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_pll_setup.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_CHIPLET_PLL_SETUP_Private_Constants +{ + NS_DELAY = 5000000, // unit is nano seconds + SIM_CYCLE_DELAY = 100000, // unit is sim cycles + CLOCK_CMD = 0x1, + CLOCK_TYPES = 0x2, + DONT_STARTMASTER = 0x0, + DONT_STARTSLAVE = 0x0, + REGIONS = 0x001 +}; + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_test_enable( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_read_attr = 0; + FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop PDLY bypass"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_bypass(l_chplt_trgt)); + } + + FAPI_DBG("Reading ATTR_mc_sync_mode"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); + + if ( l_read_attr ) + { + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("call clock start stop module and drop syncclk muxsel"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("release pll test enable for except pcie"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Release PLL reset"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Check pll lock for PCIe"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Check pll lock for Xb,Ob"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt)); + } + } + else + { + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop MCC bypass"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_dcc_bypass(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("call clock start stop module and drop syncclk_muxsel"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("release pll test enable for except pcie"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Release PLL reset"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Check pll lock for pcie"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("check pll lock for Mc,Xb,Ob"); + FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt)); + } + } + + FAPI_INF("p9_sbe_chiplet_pll_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief check pll lock for pcie chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pci_pll_lock: Entering ..."); + + FAPI_DBG("Check PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<0>() == 1 && l_read_reg.getBit<1>() == 1, + fapi2::PLL_LOCK_ERR() + .set_PLL_READ(l_read_reg), + "ERROR:PLL LOCK NOT SET"); + + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pci_pll_lock: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief check pll lock for OB,XB,MC +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pll_lock: Entering ..."); + + FAPI_DBG("Check PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<0>() == 1 , + fapi2::PLL_LOCK_ERR() + .set_PLL_READ(l_read_reg), + "ERROR:PLL LOCK NOT SET"); + + FAPI_INF("p9_sbe_chiplet_pll_setup_check_pll_lock: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setup PLL for XBus, OBus, PCIe, (MC) chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_function: Entering ..."); + + FAPI_DBG("Drop PLL Bypass"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_PLL_BYPASS>(); //NET_CTRL0.PLL_BYPASS = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_DBG("Set scan ratio to 4:1 as soon as PLL is out of bypass mode"); + //Setting OPCG_ALIGN register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (0x3); //OPCG_ALIGN.SCAN_RATIO = 0x3 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64)); + + FAPI_DBG("Reset PCB Slave error register"); + //Setting ERROR_REG register value + //ERROR_REG = 0xFFFFFFFFFFFFFFFF + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_ERROR_REG, 0xFFFFFFFFFFFFFFFF)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop Mc DCC bypass +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Entering ..."); + + FAPI_DBG("Drop DCC bypass"); + //Setting NET_CTRL1 register value + l_data64.flush<1>(); + //NET_CTRL1.CLK_DCC_BYPASS_EN = 0 + l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop Mc PDLY bypass +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_pdly_bypass: Entering ..."); + + FAPI_DBG("Drop PDLY bypass"); + //Setting NET_CTRL1 register value + l_data64.flush<1>(); + //NET_CTRL1.CLK_PDLY_BYPASS_EN = 0 + l_data64.clearBit<PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_mc_pdly_bypass: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief release pll reset and wait +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_reset: Entering ..."); + + FAPI_DBG("Drop PLL Reset"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_PLL_RESET>(); //NET_CTRL0.PLL_RESET = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Release pll test enable except for pcie +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_test_enable( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_test_enable: Entering ..."); + + FAPI_DBG("Release PLL test enable for except pcie"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_PLL_TEST_EN>(); //NET_CTRL0.PLL_TEST_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_pll_test_enable: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief start PLL clock region, NSL latches only , call module clock_start_stop +/// Drop syncclk_muxsel +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux: Entering ..."); + + FAPI_DBG("call module clock start stop"); + FAPI_TRY(p9_sbe_common_clock_start_stop(i_target_chiplet, CLOCK_CMD, + DONT_STARTSLAVE, DONT_STARTMASTER, REGIONS, CLOCK_TYPES)); + + FAPI_DBG("Drop syncclk muxsel for pcie chiplet"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H new file mode 100644 index 00000000..c2b1caad --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_pll_setup.H +/// +/// @brief Setup PLL for Obus, Xbus, PCIe, DMI +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_PLL_SETUP_H_ +#define _P9_SBE_CHIPLET_PLL_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_setup_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Checks that the PLL locked +/// Start the VAR OSCs / Config the TANK PLLs & lock +/// In certain configs these chiplets are potentially not used +/// Must run at system frequency +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C new file mode 100644 index 00000000..951b4696 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -0,0 +1,1330 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_reset.C +/// +/// @brief Steps:- +/// 1) Identify Partical good chiplet and configure Multicasting register +/// 2) Similar way, Configure hang pulse counter for Nest/MC/OBus/XBus/PCIe +/// 3) Similar way, set fence for Nest and MC chiplet +/// 4) Similar way, Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode +/// +/// Done +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_chiplet_reset.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint8_t i_reg0_val = 0xff, + const uint8_t i_reg1_val = 0xff, + const uint8_t i_reg2_val = 0xff, + const uint8_t i_reg3_val = 0xff, + const uint8_t i_reg4_val = 0xff, + const uint8_t i_reg5_val = 0xff, + const uint8_t i_reg6_val = 0xff); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_call( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_xbus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_enable_listen_to_sync( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_hsspowergate( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const bool i_drop); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint64_t i_mc_grp1_val, + const uint64_t i_mc_grp2_val = 0x0, + const uint64_t i_mc_grp3_val = 0x0); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_ob_async_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode +p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_pll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_scan0_call( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); + +fapi2::ReturnCode p9_sbe_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + // Local variable + //uint8_t l_mc_sync_mode = 0; + fapi2::buffer<uint8_t> l_attr_vitl_setup; + fapi2::buffer<uint8_t> l_attr_hang_cnt6_setup; + fapi2::TargetState l_target_state = fapi2::TARGET_STATE_FUNCTIONAL; + FAPI_INF("p9_sbe_chiplet_reset: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP, i_target_chip, + l_attr_vitl_setup)); + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring chiplet multicasting registers. + FAPI_DBG("Configuring multicasting registers for Nest,Xb,Obus,pcie chiplets" ); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Configuring multicast registers for MC01,MC23"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP2)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CACHES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring chiplet multicasting registers.. + FAPI_DBG("Configuring cache chiplet multicasting registers"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup_cache(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CORES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring chiplet multicasting registers.. + FAPI_DBG("Configuring core chiplet multicasting registers"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP1, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP3)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Configuring NET control registers into Default required value + FAPI_DBG("Restore NET_CTRL0&1 init value - for all chiplets except TP"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 0 and register 6 + FAPI_DBG("Setup hang pulse counter for Mc"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, 0xff, 0xff, 0xff, 0xff, 0xff, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 0 and register 6 + FAPI_DBG("Setup hang pulse counter for Pcie - increase in hang_pulse value"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, 0xff, 0xff, 0xff, 0xff, 0xff, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 0 and register 6 + FAPI_DBG("Setup hang pulse counter for Xbus,Obus"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X04, 0xff, + 0xff, 0xff, 0xff, p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_NEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 5 + FAPI_DBG("Setup hang pulse counter for nest chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_nest_hang_cnt_setup(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CORES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 5 + FAPI_DBG("Setup hang pulse counter for core chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X1A, 0xff, + 0xff, 0xff, p9SbeChipletReset::HANG_PULSE_0X06, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CACHES, fapi2::TARGET_STATE_FUNCTIONAL)) + { + // Setting up hang pulse counter for register 5 + FAPI_DBG("Setup hang pulse counter for cache chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt, + p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X01, + p9SbeChipletReset::HANG_PULSE_0X01, p9SbeChipletReset::HANG_PULSE_0X04, + p9SbeChipletReset::HANG_PULSE_0X00, p9SbeChipletReset::HANG_PULSE_0X06, + p9SbeChipletReset::HANG_PULSE_0X08)); + } + + FAPI_DBG("Clock mux settings"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_call(i_target_chip)); + + if ( l_attr_vitl_setup ) + { + l_target_state = fapi2::TARGET_STATE_PRESENT; + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), l_target_state)) + { + // Setting up partial good fence drop and resetting chiplet. + FAPI_DBG("PLL Setup : Enable pll"); + FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(l_target_cplt, true)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, l_target_state)) + { + FAPI_DBG("Drop clk async reset for N3 chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, l_target_state)) + { + FAPI_DBG("Drop clk async reset for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(l_target_cplt, true)); + } + + fapi2::delay(10000, (40 * 400)); + + if ( l_attr_vitl_setup ) + { + l_target_state = fapi2::TARGET_STATE_PRESENT; + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), l_target_state)) + { + // Setting up partial good fence drop and resetting chiplet. + FAPI_DBG("PLL setup : Disable pll"); + FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(l_target_cplt, false)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, l_target_state)) + { + FAPI_DBG("Raise clk async reset for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(l_target_cplt, false)); + } + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop clk async reset for N3, Mc and Obus chiplets"); + FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop clk_div_bypass for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES | + fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Enable chiplet and reset error register"); + FAPI_TRY(p9_sbe_chiplet_reset_setup(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop lvltrans fence and endpoint reset"); + FAPI_TRY(p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset( + l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Initialize OPCG registers for Nest,MC,XB,OB,PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Enable listen to sync for NEST,OB,XB,PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(l_target_cplt, true)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | + fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Disable listen_to_sync for Nest,MC,XB,OB,PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(l_target_cplt, false)); + } + + FAPI_DBG("Set Chip-wide HSSPORWREN gate"); + FAPI_TRY(p9_sbe_chiplet_reset_hsspowergate(i_target_chip)); + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Setup IOP Logic for PCIe"); + FAPI_TRY(p9_sbe_chiplet_reset_setup_iop_logic(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("set scan ratio to 1:1 "); + FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(l_target_cplt)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_chiplet_reset_scan0_call(l_target_cplt)); + } + + FAPI_INF("p9_sbe_chiplet_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setting up hang pulse counter for all parital good chiplet except for Tp,nest, core and cache +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @param[in] i_reg0_val value for HANG_PULSE_0_REG +/// @param[in] i_reg1_val value for HANG_PULSE_1_REG +/// @param[in] i_reg2_val value for HANG_PULSE_2_REG +/// @param[in] i_reg3_val value for HANG_PULSE_3_REG +/// @param[in] i_reg4_val value for HANG_PULSE_4_REG +/// @param[in] i_reg5_val value for HANG_PULSE_5_REG +/// @param[in] i_reg6_val Hang pulse reg 6 value - for heartbeat +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint8_t i_reg0_val, + const uint8_t i_reg1_val, + const uint8_t i_reg2_val, + const uint8_t i_reg3_val, + const uint8_t i_reg4_val, + const uint8_t i_reg5_val, + const uint8_t i_reg6_val) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Entering ..."); + + //Setting HANG_PULSE_0_REG register value (Setting all fields) + if (i_reg0_val != 0xff) + { + //HANG_PULSE_0_REG.HANG_PULSE_REG_0 = (i_reg0_val != 0xff) ? i_reg0_val + l_data64.insertFromRight<0, 6>(i_reg0_val); + //HANG_PULSE_0_REG.SUPPRESS_HANG_0 = (i_reg0_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_0_REG, l_data64)); + } + + //Setting HANG_PULSE_1_REG register value (Setting all fields) + if (i_reg1_val != 0xff) + { + //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = (i_reg1_val != 0xff) ? i_reg1_val + l_data64.insertFromRight<0, 6>(i_reg1_val); + //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = (i_reg1_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); + } + + //Setting HANG_PULSE_2_REG register value (Setting all fields) + if (i_reg2_val != 0xff) + { + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = (i_reg2_val != 0xff) ? i_reg2_val + l_data64.insertFromRight<0, 6>(i_reg2_val); + //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = (i_reg2_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + } + + //Setting HANG_PULSE_3_REG register value (Setting all fields) + if (i_reg3_val != 0xff) + { + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = (i_reg3_val != 0xff) ? i_reg3_val + l_data64.insertFromRight<0, 6>(i_reg3_val); + //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = (i_reg3_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + } + + //Setting HANG_PULSE_4_REG register value (Setting all fields) + if (i_reg4_val != 0xff) + { + //HANG_PULSE_4_REG.HANG_PULSE_REG_4 = (i_reg4_val != 0xff) ? i_reg4_val + l_data64.insertFromRight<0, 6>(i_reg4_val); + //HANG_PULSE_4_REG.SUPPRESS_HANG_4 = (i_reg4_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64)); + } + + //Setting HANG_PULSE_5_REG register value (Setting all fields) + if (i_reg5_val != 0xff) + { + //HANG_PULSE_5_REG.HANG_PULSE_REG_5 = (i_reg5_val != 0xff) ? i_reg5_val + l_data64.insertFromRight<0, 6>(i_reg5_val); + //HANG_PULSE_5_REG.SUPPRESS_HANG_5 = (i_reg5_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_5_REG, l_data64)); + } + + //Setting HANG_PULSE_6_REG register value (Setting all fields) + if (i_reg6_val != 0xff) + { + //HANG_PULSE_6_REG.HANG_PULSE_REG_6 = (i_reg6_val != 0xff) ? i_reg6_val + l_data64.insertFromRight<0, 6>(i_reg6_val); + //HANG_PULSE_6_REG.SUPPRESS_HANG_6 = (i_reg6_val != 0xff) ? 0 + l_data64.clearBit<6>(); + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_6_REG, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Configuring NET control registers into Default required value +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + fapi2::buffer<uint8_t> l_read_attr; + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup: Entering ..."); + + //Setting NET_CTRL0 register value + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = + i_target_cplt.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + FAPI_DBG("Disable local clock gating VITAL"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING, + l_chip, l_read_attr)); + + if (l_read_attr) + { + //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0, + p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1)); + } + else + { + //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0, + p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE)); + } + + //Setting NET_CTRL1 register value + //NET_CTRL1 = p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL1, + p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE)); + + FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup:Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for Mc chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC: Entering ..."); + + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<3>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<3>()); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief call all the related mux settings on chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_call( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet) +{ + fapi2::buffer<uint32_t> l_read_attr; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_call: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chiplet, + l_read_attr)); + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for Mc chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_MC(l_target_cplt, l_read_attr)); + } + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for OB chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_obus(l_target_cplt, l_read_attr)); + } + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for XB chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_xbus(l_target_cplt, l_read_attr)); + } + + for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Mux settings for Pcie chiplet"); + FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_pcie(l_target_cplt, l_read_attr)); + } + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_call: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for OB chiplet +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value Clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + uint8_t l_attr_unit_pos = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, + l_attr_unit_pos)); + + if ( l_attr_unit_pos == 0x09 ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<6>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<6>()); + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL> + (i_clk_mux_value.getBit<13>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<13>() + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL> + (i_clk_mux_value.getBit<15>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<15>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + if ( l_attr_unit_pos == 0x0A ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL> + (i_clk_mux_value.getBit<16>()); //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<16>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + if ( l_attr_unit_pos == 0x0B ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL> + (i_clk_mux_value.getBit<17>()); //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<17>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + if ( l_attr_unit_pos == 0x0C ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<7>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<7>()); + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL> + (i_clk_mux_value.getBit<9>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<9>() + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL> + (i_clk_mux_value.getBit<14>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<14>() + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for Pcie chiplet +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + uint8_t l_attr_unit_pos = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, + l_attr_unit_pos)); + + if ( l_attr_unit_pos != 0x0E ) + { + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>((l_attr_unit_pos == 0x0D) ? + i_clk_mux_value.getBit<5>() : + i_clk_mux_value.getBit<4>()); //NET_CTRL1.PLL_CLKIN_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<5>() : i_clk_mux_value.getBit<4>() + + if (l_attr_unit_pos == 0x0D) + { + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL> + (i_clk_mux_value.getBit<10>()); //NET_CTRL1.REFCLK_CLKMUX0_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<10>() + l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL> + (i_clk_mux_value.getBit<11>()); //NET_CTRL1.REFCLK_CLKMUX1_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<11>() + } + + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock mux settings for XB chiplet +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_clk_mux_value clock mux value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_xbus( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_clk_mux_value) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_xbus: Entering ..."); + + //Setting NET_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<8>() + l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<8>()); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_clk_mux_xbus: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop clk div bypass for Mc chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Entering ..."); + + FAPI_DBG("drop clk_div_bypass_en"); + //Setting NET_CTRL1 register value + l_data64.flush<1>(); + //NET_CTRL1.CLK_DIV_BYPASS_EN = 0 + l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Enable listen_to_sync mode for all chiplets except MC +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_enable if TRUE - enable, FALSE - disable +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_enable_listen_to_sync( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable) +{ + FAPI_INF("p9_sbe_chiplet_reset_enable_listen_to_sync: Entering ..."); + + //Setting SYNC_CONFIG register value + //SYNC_CONFIG = i_enable? p9SbeChipletReset::SYNC_CONFIG_DEFAULT : p9SbeChipletReset::SYNC_CONFIG_4TO1 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SYNC_CONFIG, + i_enable ? p9SbeChipletReset::SYNC_CONFIG_DEFAULT : + p9SbeChipletReset::SYNC_CONFIG_4TO1)); + + FAPI_INF("p9_sbe_chiplet_reset_enable_listen_to_sync: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Set Chip-wide HSSPORWREN gate +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_hsspowergate( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_chiplet_reset_hsspowergate: Entering ..."); + + //Getting ROOT_CTRL2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, + l_read_reg)); //l_read_reg = PIB.ROOT_CTRL2 + + l_read_reg.setBit<20>(); + + FAPI_DBG("Set Chip-wide HSSPORWREN gate"); + //Setting ROOT_CTRL2 register value + //PIB.ROOT_CTRL2 = l_read_reg + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_read_reg)); + + FAPI_INF("p9_sbe_chiplet_reset_hsspowergate: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop/ raise MC async reset +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_drop Raise/drop mc async reset +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const bool i_drop) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_mc_async_reset_setup: Entering ..."); + + if ( i_drop ) + { + FAPI_DBG("Drop mc async reset"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.CLK_ASYNC_RESET = 0 + l_data64.clearBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64)); + } + else + { + if ( !(i_target_chip.isFunctional()) ) + { + FAPI_DBG("Raise mc async reset"); + //Setting NET_CTRL0 register value + l_data64.flush<0>(); + //NET_CTRL0.CLK_ASYNC_RESET = 1 + l_data64.setBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WOR, l_data64)); + } + } + + FAPI_INF("p9_sbe_chiplet_reset_mc_async_reset_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Configuring multicast registers for nest, cache, core +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_mc_grp1_val value for MULTICAST_GROUP1 register +/// @param[in] i_mc_grp2_val value for MULTICAST_GROUP2 register +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint64_t i_mc_grp1_val, + const uint64_t i_mc_grp2_val, + const uint64_t i_mc_grp3_val) +{ + FAPI_INF("p9_sbe_chiplet_reset_mc_setup: Entering ..."); + + //Setting MULTICAST_GROUP_1 register value + //MULTICAST_GROUP_1 (register) = i_mc_grp1_val + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1, + i_mc_grp1_val)); + + //Setting MULTICAST_GROUP_2 register value + if (i_mc_grp2_val != 0x0) + { + //MULTICAST_GROUP_2 (register) = (i_mc_grp2_val != 0x0) ? i_mc_grp2_val + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2, + i_mc_grp2_val)); + } + + //Setting MULTICAST_GROUP_3 register value + if (i_mc_grp3_val != 0x0) + { + //MULTICAST_GROUP_REGISTER_3 = (i_mc_grp3_val != 0x0) ? i_mc_grp3_val + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3, + i_mc_grp3_val)); + } + + FAPI_INF("p9_sbe_chiplet_reset_mc_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Multicast register setup for Cache chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + uint32_t l_attr_pg = 0; + FAPI_INF("p9_sbe_chiplet_reset_mc_setup_cache: Entering ..."); + + FAPI_DBG("Reading ATTR_PG"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); + + FAPI_DBG("Setting Multicast register 1&2 for cache chiplet"); + //Setting MULTICAST_GROUP_1 register value + //MULTICAST_GROUP_1 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0)); + //Setting MULTICAST_GROUP_2 register value + //MULTICAST_GROUP_2 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4)); + + if ( ( l_attr_pg & 0x1EBA ) == 0x0 ) // Check good EP chiplet clockdomains excluding l31, l21, refr1 + { + FAPI_DBG("Setting up multicast register 3 for even cache chiplet"); + //Setting MULTICAST_GROUP_3 register value + //MULTICAST_GROUP_3 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5)); + } + + if ( ( l_attr_pg & 0x1D76 ) == 0x0 ) // Check good EP chiplet clockdomains excluding l30, l20, refr0 + { + FAPI_DBG("Setting up multicast register 4 for odd cache chiplet"); + //Setting MULTICAST_GROUP_4 register value + //MULTICAST_GROUP_4 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_4, + p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6)); + } + + FAPI_INF("p9_sbe_chiplet_reset_mc_setup_cache: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setting up hang pulse counter for partial good Nest chiplet +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_hang_cnt_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + // Local variables + // + uint8_t l_attr_chipunit_pos = 0; + const uint8_t l_n0 = 0x02; + const uint8_t l_n1 = 0x03; + const uint8_t l_n2 = 0x04; + const uint8_t l_n3 = 0x05; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_nest_hang_cnt_setup: Entering ..."); + + // Collecting partial good and chiplet unit position attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_cplt, + l_attr_chipunit_pos)); + + //Setting HANG_PULSE_0_REG register value (Setting all fields) + //HANG_PULSE_0_REG.HANG_PULSE_REG_0 = p9SbeChipletReset::HANG_PULSE_0X10 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X10); + l_data64.clearBit<6>(); //HANG_PULSE_0_REG.SUPPRESS_HANG_0 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_0_REG, l_data64)); + //Setting HANG_PULSE_5_REG register value (Setting all fields) + //HANG_PULSE_5_REG.HANG_PULSE_REG_5 = p9SbeChipletReset::HANG_PULSE_0X06 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X06); + l_data64.clearBit<6>(); //HANG_PULSE_5_REG.SUPPRESS_HANG_5 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_5_REG, l_data64)); + //Setting HANG_PULSE_6_REG register value (Setting all fields) + //HANG_PULSE_6_REG.HANG_PULSE_REG_6 = p9SbeChipletReset::HANG_PULSE_0X08 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X08); + l_data64.clearBit<6>(); //HANG_PULSE_6_REG.SUPPRESS_HANG_6 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_6_REG, l_data64)); + + if ( l_attr_chipunit_pos == l_n0 ) + { + //Setting HANG_PULSE_1_REG register value (Setting all fields) + //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X18 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X18); + l_data64.clearBit<6>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X23 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X23); + l_data64.clearBit<6>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X12); + l_data64.clearBit<6>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + } + + if ( l_attr_chipunit_pos == l_n1 ) + { + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X0F + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X0F); + l_data64.clearBit<6>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + } + + if ( l_attr_chipunit_pos == l_n2 ) + { + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X12); + l_data64.clearBit<6>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + } + + if ( l_attr_chipunit_pos == l_n3 ) + { + //Setting HANG_PULSE_1_REG register value (Setting all fields) + //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X17 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X17); + l_data64.clearBit<6>(); //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64)); + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X13 + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X13); + l_data64.clearBit<6>(); //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64)); + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X0F + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X0F); + l_data64.clearBit<6>(); //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64)); + //Setting HANG_PULSE_4_REG register value (Setting all fields) + //HANG_PULSE_4_REG.HANG_PULSE_REG_4 = p9SbeChipletReset::HANG_PULSE_0X1C + l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X1C); + l_data64.clearBit<6>(); //HANG_PULSE_4_REG.SUPPRESS_HANG_4 = 0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64)); + } + + FAPI_INF("p9_sbe_chiplet_reset_nest_hang_cnt_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Dropping the net_ctrl0 clock_async_reset +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_ob_async_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_nest_ob_async_reset: Entering ..."); + + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.CLK_ASYNC_RESET = 0 + l_data64.clearBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_nest_ob_async_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop Endpoint reset +/// Drop lvltrans fence +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode +p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset: Entering ..."); + + FAPI_DBG("Drop lvltrans fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.LVLTRANS_FENCE = 0b0 + l_data64.clearBit<PERV_1_NET_CTRL0_LVLTRANS_FENCE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_DBG("Drop endpoint reset"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + //NET_CTRL0.PCB_EP_RESET = 0b0 + l_data64.clearBit<PERV_1_NET_CTRL0_PCB_EP_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief configuring Nest chiplet OPCG registers +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg: Entering ..."); + + //Setting OPCG_ALIGN register value + l_data64 = + p9SbeChipletReset::OPCG_ALIGN_SETTING; //OPCG_ALIGN = p9SbeChipletReset::OPCG_ALIGN_SETTING + //OPCG_ALIGN.INOP_ALIGN = p9SbeChipletReset::INOP_ALIGN_SETTING_0X5 + l_data64.insertFromRight<0, 4>(p9SbeChipletReset::INOP_ALIGN_SETTING_0X5); + l_data64.clearBit<PERV_1_OPCG_ALIGN_INOP_WAIT, PERV_1_OPCG_ALIGN_INOP_WAIT_LEN>(); //OPCG_ALIGN.INOP_WAIT = 0 + //OPCG_ALIGN.OPCG_WAIT_CYCLES = p9SbeChipletReset::OPCG_WAIT_CYCLE_0X020 + l_data64.insertFromRight<52, 12>(p9SbeChipletReset::OPCG_WAIT_CYCLE_0X020); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (p9SbeChipletReset::SCAN_RATIO_0X3); //OPCG_ALIGN.SCAN_RATIO = p9SbeChipletReset::SCAN_RATIO_0X3 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief set scan ratio to 1:1 as long as PLL is in bypass mode +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio: Entering ..."); + + FAPI_DBG("Set scan ratio to 1:1 as long as PLL is in bypass mode"); + //Setting OPCG_ALIGN register value + FAPI_TRY(fapi2::getScom(i_target_cplt, PERV_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (p9SbeChipletReset::SCAN_RATIO_0X0); //OPCG_ALIGN.SCAN_RATIO = p9SbeChipletReset::SCAN_RATIO_0X0 + FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_OPCG_ALIGN, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Enable PLL +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_enable enable/disable pll +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_pll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const bool i_enable) +{ + fapi2::buffer<uint64_t> l_data;; + FAPI_INF("p9_sbe_chiplet_reset_pll_setup: Entering ..."); + + if ( i_enable ) + { + l_data.flush<0>(); + l_data.setBit<31>(); + + FAPI_DBG("Enable pll"); + //Setting NET_CTRL0 register value + //NET_CTRL0 = l_data + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data)); + } + else + { + if ( !(i_target_chiplet.isFunctional()) ) + { + l_data.flush<1>(); + l_data.clearBit<31>(); + + FAPI_DBG("Disable PLL"); + //Setting NET_CTRL0 register value + //NET_CTRL0 = l_data + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data)); + } + } + + FAPI_INF("p9_sbe_chiplet_reset_pll_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Scan0 module call +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_scan0_call( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + FAPI_INF("p9_sbe_chiplet_reset_scan0_call: Entering ..."); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(i_target_chip, + p9SbeChipletReset::REGIONS_EXCEPT_VITAL, l_regions)); + + FAPI_DBG("run scan0 module for region except vital and pll, scan types GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chip, l_regions, + p9SbeChipletReset::SCAN_TYPES_TIME_GPTR_REPR)); + + FAPI_DBG("run scan0 module for region except vital and pll, scan types except GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chip, l_regions, + p9SbeChipletReset::SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + + FAPI_INF("p9_sbe_chiplet_reset_scan0_call: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Dorping fence on Partial good chiplet and resetting it. +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + // Local variable and constant definition + const uint64_t l_error_default_value = 0xFFFFFFFFFFFFFFFFull; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_setup: Entering ..."); + + // EP Reset all chiplet with in multicasting group + //Setting NET_CTRL0 register value + l_data64.flush<0>(); + //NET_CTRL0.CHIPLET_ENABLE = 0b1 + l_data64.setBit<PERV_1_NET_CTRL0_CHIPLET_ENABLE>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64)); + + //Setting ERROR_REG register value + //ERROR_REG = l_error_default_value + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_ERROR_REG, + l_error_default_value)); + + FAPI_INF("p9_sbe_chiplet_reset_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Setup IOP Logic for PCIe +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_chiplet_reset_setup_iop_logic: Entering ..."); + + //Setting CPLT_CONF1 register value + l_data64.flush<0>(); + l_data64.setBit<30>(); //CPLT_CONF1.TC_IOP_HSSPORWREN = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF1_OR, l_data64)); + + fapi2::delay(p9SbeChipletReset::HW_NS_DELAY, + p9SbeChipletReset::SIM_CYCLE_DELAY); + + //Setting CPLT_CONF1 register value + l_data64.flush<0>(); + l_data64.setBit<28>(); //CPLT_CONF1.TC_IOP_SYS_RESET_PCS = 0b1 + l_data64.setBit<29>(); //CPLT_CONF1.TC_IOP_SYS_RESET_PMA = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF1_OR, l_data64)); + + FAPI_INF("p9_sbe_chiplet_reset_setup_iop_logic:Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H new file mode 100644 index 00000000..feeec54b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -0,0 +1,125 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_chiplet_reset.H +/// +/// @brief Steps:- +/// 1) Identify Partical good chiplet and configure Multicasting register +/// 2) Similar way, Configure hang pulse counter for Nest/MC/OBus/XBus/PCIe +/// 3) Similar way, set fence for Nest and MC chiplet +/// 4) Similar way, Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode +/// +/// Done +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CHIPLET_RESET_H_ +#define _P9_SBE_CHIPLET_RESET_H_ + + +#include <fapi2.H> + + +namespace p9SbeChipletReset +{ +enum P9_SBE_CHIPLET_RESET_Public_Constants +{ + MCGR_CNFG_SETTING_GROUP0 = 0xE0001C0000000000ull, + MCGR_CNFG_SETTING_GROUP1 = 0xE4001C0000000000ull, + MCGR_CNFG_SETTING_GROUP2 = 0xE8001C0000000000ull, + MCGR_CNFG_SETTING_GROUP3 = 0xEC001C0000000000ull, + MCGR_CNFG_SETTING_GROUP4 = 0xF0001C0000000000ull, + MCGR_CNFG_SETTING_GROUP5 = 0xF4001C0000000000ull, + MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull, + NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull, + NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull, + HANG_PULSE_0X10 = 0x10, + HANG_PULSE_0X0F = 0x0F, + HANG_PULSE_0X06 = 0x06, + HANG_PULSE_0X17 = 0x17, + HANG_PULSE_0X18 = 0x18, + HANG_PULSE_0X22 = 0x22, + HANG_PULSE_0X23 = 0x23, + HANG_PULSE_0X13 = 0x13, + HANG_PULSE_0X03 = 0x03, + OPCG_ALIGN_SETTING = 0x5000000000003020ull, + INOP_ALIGN_SETTING_0X5 = 0x5, + OPCG_WAIT_CYCLE_0X020 = 0x020, + SCAN_RATIO_0X3 = 0x3, + SYNC_PULSE_DELAY_0X0 = 0X00, + SYNC_CONFIG_DEFAULT = 0X0000000000000000, + HANG_PULSE_0X00 = 0x00, + HANG_PULSE_0X01 = 0x01, + HANG_PULSE_0X04 = 0x04, + HANG_PULSE_0X1A = 0x1A, + NET_CNTL1_HW_INIT_VALUE = 0x7200000000000000ull, + REGIONS_EXCEPT_VITAL = 0x7FF, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE, + SCAN_TYPES_TIME_GPTR_REPR = 0x230, + SCAN_RATIO_0X0 = 0x0, + SYNC_CONFIG_4TO1 = 0X0800000000000000, + HW_NS_DELAY = 200000, // unit is nano seconds + SIM_CYCLE_DELAY = 10000, // unit is cycles + HANG_PULSE_0X12 = 0x12, + HANG_PULSE_0X1C = 0x1C, + HANG_PULSE_0X08 = 0x08 +}; +} + +typedef fapi2::ReturnCode (*p9_sbe_chiplet_reset_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Identify all good chiplets excluding EQ/EC +/// -- All chiplets will be reset and PLLs started +/// -- Partial bad - All nest Chiplets must be good, MC, IO can be partial bad +/// Setup multicast groups for all chiplets +/// -- Can't use the multicast for all non-nest chiplets +/// -- This is intended to be the eventual product setting +/// -- This includes the core/cache chiplets +/// For all good chiplets excluding EQ/EC +/// -- Setup Chiplet GP3 regs +/// -- Reset to default state +/// -- Set chiplet enable on all all good chiplets excluding EQ/EC +/// For all enabled chiplets excluding EQ/EC/Buses +/// -- Start vital clocks and release endpoint reset +/// -- PCB Slave error register Reset +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C new file mode 100644 index 00000000..3a8a765c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_clock_test2.C +/// +/// @brief sbe_clock_test2 for enabling osc-check +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_clock_test2.H" + + + +fapi2::ReturnCode p9_sbe_clock_test2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet) +{ + FAPI_INF("Entering ..."); + + FAPI_INF("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H new file mode 100644 index 00000000..180d8c66 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_clock_test2.H +/// +/// @brief sbe_clock_test2 for enabling osc-check +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_CLOCK_TEST2_H_ +#define _P9_SBE_CLOCK_TEST2_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_clock_test2_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief enable osc checking +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_clock_test2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C new file mode 100644 index 00000000..c9586829 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -0,0 +1,658 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_common.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_common.C +/// +/// @brief Common Modules for SBE +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_common.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_const_common.H> + + +enum P9_SBE_COMMON_Private_Constants +{ + NS_DELAY = 100000, // unit in nano seconds + SIM_CYCLE_DELAY = 1000, // unit in cycles + CPLT_ALIGN_CHECK_POLL_COUNT = 10, // count to wait for chiplet aligned + CPLT_OPCG_DONE_DC_POLL_COUNT = 10 // count to wait for chiplet opcg done +}; + +/// @brief --For all chiplets exit flush +/// --For all chiplets enable alignment +/// --For all chiplets disable alignemnt +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_align_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets) +{ + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_sbe_common_align_chiplets: Entering ..."); + + FAPI_DBG("For all chiplets: exit flush"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("For all chiplets: enable alignement"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("Clear chiplet is aligned"); + //Setting SYNC_CONFIG register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b1 + l_data64.setBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + + FAPI_DBG("Unset Clear chiplet is aligned"); + //Setting SYNC_CONFIG register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b0 + l_data64.clearBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); + l_timeout = CPLT_ALIGN_CHECK_POLL_COUNT; + + //UNTIL CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC == 1 + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::CPLT_NOT_ALIGNED_ERR(), + "ERROR:CHIPLET NOT ALIGNED"); + + FAPI_DBG("For all chiplets: disable alignement"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_common_align_chiplets: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief To do check on Clock controller status for chiplets +/// +/// @param[in] i_target Reference to TARGET_TYPE_PERV target Reference to TARGET_TYPE_PERV target +/// @param[in] i_clock_cmd Issue clock controller command (START/STOP) +/// @param[in] i_regions Enable required REGIONS +/// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_cc_status_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types) +{ + bool l_reg_sl = false; + bool l_reg_nsl = false; + bool l_reg_ary = false; + fapi2::buffer<uint64_t> l_sl_clock_status; + fapi2::buffer<uint64_t> l_nsl_clock_status; + fapi2::buffer<uint64_t> l_ary_clock_status; + fapi2::buffer<uint16_t> l_sl_clkregion_status; + fapi2::buffer<uint16_t> l_nsl_clkregion_status; + fapi2::buffer<uint16_t> l_ary_clkregion_status; + fapi2::buffer<uint16_t> l_regions; + FAPI_INF("p9_sbe_common_check_cc_status_function: Entering ..."); + + l_reg_sl = i_clock_types.getBit<5>(); + l_reg_nsl = i_clock_types.getBit<6>(); + l_reg_ary = i_clock_types.getBit<7>(); + i_regions.extractToRight<5, 11>(l_regions); + + if ( l_reg_sl ) + { + FAPI_DBG("Check for Clocks running SL"); + //Getting CLOCK_STAT_SL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, + l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL + FAPI_DBG("SL Clock status register is %#018lX", l_sl_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_sl_clkregion_status.flush<1>(); + l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); + l_sl_clkregion_status.invert(); + l_sl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_sl_clkregion_status == l_regions, + fapi2::NEST_SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "Clock running for sl type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_sl_clkregion_status.flush<0>(); + l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status); + l_sl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_sl_clkregion_status == l_regions, + fapi2::NEST_SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "Clock running for sl type not matching with expected values"); + } + } + + if ( l_reg_nsl ) + { + FAPI_DBG("Check for clocks running NSL"); + //Getting CLOCK_STAT_NSL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, + l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL + FAPI_DBG("NSL Clock status register is %#018lX", l_nsl_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_nsl_clkregion_status.flush<1>(); + l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); + l_nsl_clkregion_status.invert(); + l_nsl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_nsl_clkregion_status == l_regions, + fapi2::NEST_NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "Clock running for nsl type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_nsl_clkregion_status.flush<0>(); + l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status); + l_nsl_clkregion_status &= l_regions; + + FAPI_ASSERT(l_nsl_clkregion_status == l_regions, + fapi2::NEST_NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "Clock running for nsl type not matching with expected values"); + } + } + + if ( l_reg_ary ) + { + FAPI_DBG("Check for clocks running ARY"); + //Getting CLOCK_STAT_ARY register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, + l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY + FAPI_DBG("ARY Clock status register is %#018lX", l_ary_clock_status); + + if ( i_clock_cmd == 0b01 ) + { + FAPI_DBG("Checking for clock start command"); + l_ary_clkregion_status.flush<1>(); + l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); + l_ary_clkregion_status.invert(); + l_ary_clkregion_status &= l_regions; + + FAPI_ASSERT(l_ary_clkregion_status == l_regions, + fapi2::NEST_ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "Clock running for ary type not matching with expected values"); + } + + if ( i_clock_cmd == 0b10 ) + { + FAPI_DBG("Checking for clock stop command"); + l_ary_clkregion_status.flush<0>(); + l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status); + l_ary_clkregion_status &= l_regions; + + FAPI_ASSERT(l_ary_clkregion_status == l_regions, + fapi2::NEST_ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "Clock running for ary type not matching with expected values"); + } + } + + FAPI_INF("p9_sbe_common_check_cc_status_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --check checkstop register +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_checkstop_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_read_reg; + FAPI_INF("p9_sbe_common_check_checkstop_function: Entering ..."); + + FAPI_DBG("Check checkstop register"); + //Getting XFIR register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_XFIR, + l_read_reg)); //l_read_reg = XFIR + + FAPI_ASSERT(l_read_reg == 0, + fapi2::READ_ALL_CHECKSTOP_ERR() + .set_READ_ALL_CHECKSTOP(l_read_reg), + "ERROR: COMBINE ALL CHECKSTOP ERROR"); + + FAPI_INF("p9_sbe_common_check_checkstop_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief check clocks status +/// +/// @param[in] i_regions regions from upper level input +/// @param[in] i_clock_status clock status +/// @param[in] i_reg bit status +/// @param[in] i_clock_cmd clock command +/// @param[out] o_exp_clock_status expected clock status +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer<uint64_t> + i_regions, + const fapi2::buffer<uint64_t> i_clock_status, + const bool i_reg, + const fapi2::buffer<uint8_t> i_clock_cmd, + fapi2::buffer<uint64_t>& o_exp_clock_status) +{ + FAPI_INF("p9_sbe_common_check_status: Entering ..."); + + if ( (i_reg) && (i_clock_cmd == 0b01) ) + { + o_exp_clock_status = i_clock_status & (~(i_regions << 49)); + } + else + { + if ( (i_reg) && (i_clock_cmd == 0b10) ) + { + o_exp_clock_status = i_clock_status | (i_regions << 49); + } + else + { + o_exp_clock_status = i_clock_status; + } + } + + FAPI_INF("p9_sbe_common_check_status: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} + +/// @brief -- Utility function that can be used to start clocks for a specific input regions +/// -- i_regions is to input regions +/// +/// +/// @param[in] i_target Reference to TARGET_TYPE_PERV target +/// @param[in] i_clock_cmd Issue clock controller command (START/STOP) +/// @param[in] i_startslave Bit to configure to start Slave +/// @param[in] i_startmaster Bit to configure to start Master +/// @param[in] i_regions Enable required REGIONS +/// @param[in] i_clock_types Clock Types to be selected (SL/NSL/ARY) +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_clock_start_stop(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const bool i_startslave, + const bool i_startmaster, + const fapi2::buffer<uint64_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types) +{ + fapi2::buffer<uint64_t> l_sl_clock_status; + fapi2::buffer<uint64_t> l_nsl_clock_status; + fapi2::buffer<uint64_t> l_ary_clock_status; + fapi2::buffer<uint64_t> l_exp_sl_clock_status; + fapi2::buffer<uint64_t> l_exp_nsl_clock_status; + fapi2::buffer<uint64_t> l_exp_ary_clock_status; + fapi2::buffer<uint8_t> l_clk_cmd; + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint8_t> l_reg_all; + bool l_reg_sl = false; + bool l_reg_nsl = false; + bool l_reg_ary = false; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_sbe_common_clock_start_stop: Entering ..."); + + i_regions.extractToRight<53, 11>(l_regions); + i_clock_types.extractToRight<5, 3>(l_reg_all); + l_reg_sl = i_clock_types.getBit<5>(); + l_reg_nsl = i_clock_types.getBit<6>(); + l_reg_ary = i_clock_types.getBit<7>(); + + FAPI_DBG("Chiplet exit flush"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + FAPI_TRY(fapi2::putScom(i_target, PERV_CPLT_CTRL0_OR, l_data64)); + + FAPI_DBG("Clear Scan region type register"); + //Setting SCAN_REGION_TYPE register value + //SCAN_REGION_TYPE = 0 + FAPI_TRY(fapi2::putScom(i_target, PERV_SCAN_REGION_TYPE, 0)); + + FAPI_DBG("Reading the initial status of clock controller"); + //Getting CLOCK_STAT_SL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, + l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL + //Getting CLOCK_STAT_NSL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, + l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL + //Getting CLOCK_STAT_ARY register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, + l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY + FAPI_DBG("Clock status of SL_Register:%#018lX NSL_Register:%#018lX ARY_Register:%#018lX", + l_sl_clock_status, l_nsl_clock_status, l_ary_clock_status); + + i_clock_cmd.extractToRight<6, 2>(l_clk_cmd); + + FAPI_DBG("Setup all Clock Domains and Clock Types"); + //Setting CLK_REGION register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLK_REGION, l_data64)); + l_data64.insertFromRight<PERV_1_CLK_REGION_CLOCK_CMD, PERV_1_CLK_REGION_CLOCK_CMD_LEN> + (l_clk_cmd); //CLK_REGION.CLOCK_CMD = l_clk_cmd + //CLK_REGION.SLAVE_MODE = i_startslave + l_data64.writeBit<PERV_1_CLK_REGION_SLAVE_MODE>(i_startslave); + //CLK_REGION.MASTER_MODE = i_startmaster + l_data64.writeBit<PERV_1_CLK_REGION_MASTER_MODE>(i_startmaster); + //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + //CLK_REGION.SEL_THOLD_ALL = l_reg_all + l_data64.insertFromRight<48, 3>(l_reg_all); + FAPI_TRY(fapi2::putScom(i_target, PERV_CLK_REGION, l_data64)); + + // To wait until OPCG Done - CPLT_STAT0.cc_cplt_opcg_done_dc = 1 + FAPI_DBG("Poll OPCG done bit to check for completeness"); + l_data64.flush<0>(); + l_timeout = CPLT_OPCG_DONE_DC_POLL_COUNT; + + while (l_timeout != 0) + { + //Getting CPLT_STAT0 register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CPLT_STAT0, l_data64)); + bool l_poll_data = + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>(); + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::CPLT_OPCG_DONE_NOT_SET_ERR(), + "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD"); + + //To do do checking only for chiplets that dont have Master-slave mode enabled + + if ( !i_startslave && !i_startmaster ) + { + // Calculating the Expected clock status + + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_sl_clock_status, l_reg_sl, + i_clock_cmd, l_exp_sl_clock_status)); + + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_nsl_clock_status, l_reg_nsl, + i_clock_cmd, l_exp_nsl_clock_status)); + + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_ary_clock_status, l_reg_ary, + i_clock_cmd, l_exp_ary_clock_status)); + + FAPI_DBG("Check for clocks running SL"); + //Getting CLOCK_STAT_SL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, + l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", + l_exp_sl_clock_status, l_sl_clock_status); + + FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, + fapi2::SL_ERR() + .set_READ_CLK_SL(l_sl_clock_status), + "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); + + FAPI_DBG("Check for clocks running NSL"); + //Getting CLOCK_STAT_NSL register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, + l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", + l_exp_nsl_clock_status, l_nsl_clock_status); + + FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, + fapi2::NSL_ERR() + .set_READ_CLK_NSL(l_nsl_clock_status), + "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); + + FAPI_DBG("Check for clocks running ARY"); + //Getting CLOCK_STAT_ARY register value + FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, + l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", + l_exp_ary_clock_status, l_ary_clock_status); + + FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, + fapi2::ARY_ERR() + .set_READ_CLK_ARY(l_ary_clock_status), + "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); + } + + FAPI_INF("p9_sbe_common_clock_start_stop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --drop vital fence +/// --reset abstclk muxsel,syncclk_muxsel +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr_pg ATTR_PG for the corresponding chiplet +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_attr_pg) +{ + // Local variable and constant definition + fapi2::buffer <uint16_t> l_cplt_ctrl_init; + fapi2::buffer<uint32_t> l_attr_pg; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_common_cplt_ctrl_action_function: Entering ..."); + + l_attr_pg = i_attr_pg; + l_attr_pg.invert(); + l_attr_pg.extractToRight<20, 11>(l_cplt_ctrl_init); + + // Not needed as have only nest chiplet (no dual clock controller) Bit 62 ->0 + // + FAPI_DBG("Drop partial good fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + l_data64.writeBit<PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE> + (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_cplt_ctrl_init + l_data64.insertFromRight<4, 11>(l_cplt_ctrl_init); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_DBG("reset abistclk_muxsel and syncclk_muxsel"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>(); + //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_common_cplt_ctrl_action_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief will force all chiplets out of flush +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_flushmode(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_common_flushmode: Entering ..."); + + FAPI_DBG("Clear flush_inhibit to go in to flush mode"); + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 0 + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_common_flushmode: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief get children for all chiplets : Perv, Nest +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[out] o_pg_vector vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_get_pg_vector(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + fapi2::buffer<uint64_t>& o_pg_vector) +{ + fapi2::buffer<uint8_t> l_read_attrunitpos; + FAPI_INF("p9_sbe_common_get_pg_vector: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chip, + l_read_attrunitpos)); + + if ( l_read_attrunitpos == 0x01 ) + { + o_pg_vector.setBit<0>(); + } + + if ( l_read_attrunitpos == 0x02 ) + { + o_pg_vector.setBit<1>(); + } + + if ( l_read_attrunitpos == 0x03 ) + { + o_pg_vector.setBit<2>(); + } + + if ( l_read_attrunitpos == 0x04 ) + { + o_pg_vector.setBit<3>(); + } + + if ( l_read_attrunitpos == 0x05 ) + { + o_pg_vector.setBit<4>(); + } + + FAPI_INF("p9_sbe_common_get_pg_vector: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --Setting Scan ratio +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_common_set_scan_ratio: Entering ..."); + + //Setting OPCG_ALIGN register value + FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> + (0xE0); //OPCG_ALIGN.SCAN_RATIO = 0xE0 + FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64)); + + FAPI_INF("p9_sbe_common_set_scan_ratio: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H new file mode 100644 index 00000000..f3876594 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H @@ -0,0 +1,90 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_common.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_common.H +/// +/// @brief Common Modules for SBE +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_COMMON_H_ +#define _P9_SBE_COMMON_H_ + + +#include <fapi2.H> + + +fapi2::ReturnCode p9_sbe_common_align_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets); + +fapi2::ReturnCode p9_sbe_common_check_cc_status_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const fapi2::buffer<uint16_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types); + +fapi2::ReturnCode p9_sbe_common_check_checkstop_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer<uint64_t> + i_regions, + const fapi2::buffer<uint64_t> i_clock_status, + const bool i_reg, + const fapi2::buffer<uint8_t> i_clock_cmd, + fapi2::buffer<uint64_t>& o_exp_clock_status); + +fapi2::ReturnCode p9_sbe_common_clock_start_allRegions(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_anychiplet); + +fapi2::ReturnCode p9_sbe_common_clock_start_stop(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target, + const fapi2::buffer<uint8_t> i_clock_cmd, + const bool i_startslave, + const bool i_startmaster, + const fapi2::buffer<uint64_t> i_regions, + const fapi2::buffer<uint8_t> i_clock_types); + +fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint32_t> i_attr_pg); + +fapi2::ReturnCode p9_sbe_common_flushmode(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_common_get_pg_vector(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + fapi2::buffer<uint64_t>& o_pg_vector); + +fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const + fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C new file mode 100644 index 00000000..d9a3f2d5 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_enable_seeprom.C +/// +/// @brief SBE enable SEEPROM (runs from OTPROM) +/// +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_enable_seeprom.H" +fapi2::ReturnCode p9_sbe_enable_seeprom(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_enable_seeprom: Entering ..."); + + FAPI_DBG("p9_sbe_enable_seeprom: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H new file mode 100644 index 00000000..00a5ebc6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_enable_seeprom.H +/// +/// @brief SBE enable SEEPROM (runs from OTPROM) +/// +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_ENABLE_SEEPROM_H_ +#define _P9_SBE_ENABLE_SEEPROM_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_enable_seeprom_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Check SBE Vital Register for selected SEEPROM image +/// -- Update SBE FI2C_E0_PARAM register +/// -- Check for valid SEEPROM image +/// -- Branch to SEEPROM +/// +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_enable_seeprom(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C new file mode 100644 index 00000000..25d61ad0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C @@ -0,0 +1,154 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gear_switcher.C +/// +/// @brief Modules for I2C Bit rate divisor setting +/// And stop sequence on I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_gear_switcher.H" + +#include "p9_misc_scom_addresses.H" +#include "p9_perv_scom_addresses.H" + + +enum P9_SBE_GEAR_SWITCHER_Private_Constants +{ + DEFAULT_MB_BIT_RATE_DIVISOR = 0x00000000, + BUS_STATUS_BUSY_POLL_COUNT = 64 +}; + +/// @brief --adjust I2C bit rate divisor setting in I2CM B mode reg +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_scratch_reg = 0; + uint16_t l_mb_bit_rate_divisor = 0; + FAPI_DBG("Entering ..."); + + FAPI_INF("Check Mailbox for Valid I2C bit rate divisor setting"); + //Getting SCRATCH_REGISTER_2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2 + + if ( !l_read_scratch_reg ) + { + FAPI_INF("Set with Default value if Mailbox empty"); + //Setting MODE_REGISTER_B register value + //PIB.MODE_REGISTER_B = DEFAULT_MB_BIT_RATE_DIVISOR + FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B, + DEFAULT_MB_BIT_RATE_DIVISOR)); + } + else + { + l_read_scratch_reg.extractToRight<0, 16>(l_mb_bit_rate_divisor); + + FAPI_INF("Adjust I2C bit rate divisor setting in I2CM B Mode Reg"); + //Setting MODE_REGISTER_B register value + //PIB.MODE_REGISTER_B = l_mb_bit_rate_divisor + FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B, + l_mb_bit_rate_divisor)); + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief --send a stop sequence on I2C +/// --poll for stop command completion +/// --check for magic number +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_read_attr = 0; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_DBG("Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BACKUP_SEEPROM_SELECT, i_target_chip, + l_read_attr)); + + // WRITE Control register + // enable enhance mode + // Point to port_0 where the Primary SEEPROM Sits + FAPI_INF("Send a STOP sequence on I2C"); + //Setting CONTROL_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64)); + l_data64.setBit<3>(); //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_BIT_WITHSTOP_0 = 1 + //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_PORT_NUMBER_0 = l_read_attr + l_data64.insertFromRight<18, 5>(l_read_attr); + l_data64.setBit<26>(); //PIB.CONTROL_REGISTER_B.ENH_MODE_0 = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64)); + + FAPI_INF("Poll for stop command completion"); + l_timeout = BUS_STATUS_BUSY_POLL_COUNT; + + //UNTIL STATUS_REGISTER_B.BUS_STATUS_BUSY_0 == 0 + while (l_timeout != 0) + { + //Getting STATUS_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64)); + //bool l_poll_data = PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0 + bool l_poll_data = l_data64.getBit<44>(); + + if (l_poll_data == 0) + { + break; + } + + --l_timeout; + } + + FAPI_INF("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::BUS_STATUS_BUSY_0(), + "ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0"); + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H new file mode 100644 index 00000000..845b68e9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gear_switcher.H +/// +/// @brief Modules for I2C Bit rate divisor setting +/// And stop sequence on I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_GEAR_SWITCHER_H_ +#define _P9_SBE_GEAR_SWITCHER_H_ + + +#include <fapi2.H> + + +fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C new file mode 100644 index 00000000..ce8302a9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C @@ -0,0 +1,288 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_initf.C +/// +/// @brief Load time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#include "p9_sbe_gptr_time_initf.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + + FAPI_INF("p9_sbe_gptr_time_initf: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST> + (fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Scan mc_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_gptr), + "Error from putRing (mc_gptr)"); + FAPI_DBG("Scan mc_iom01_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_gptr), + "Error from putRing (mc_iom01_gptr)"); + FAPI_DBG("Scan mc_iom23_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_gptr), + "Error from putRing (mc_iom23_gptr)"); + FAPI_DBG("Scan mc_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_gptr), + "Error from putRing (mc_pll_gptr)"); + FAPI_DBG("Scan mc_time ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_time), + "Error from putRing (mc_time)"); + } + + for( auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + ( fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + + if ((l_attr_chip_unit_pos == 0x9))/* OBUS0 Chiplet */ + { + FAPI_DBG("Scan ob0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_gptr), + "Error from putRing (ob0_gptr)"); + FAPI_DBG("Scan ob0_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_pll_gptr), + "Error from putRing (ob0_pll_gptr)"); + FAPI_DBG("Scan ob0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_time), + "Error from putRing (ob0_time)"); + } + + if ((l_attr_chip_unit_pos == 0xA))/* OBUS1 Chiplet */ + { + FAPI_DBG("Scan ob1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_gptr), + "Error from putRing (ob1_gptr)"); + FAPI_DBG("Scan ob1_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_pll_gptr), + "Error from putRing (ob1_pll_gptr)"); + FAPI_DBG("Scan ob1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_time), + "Error from putRing (ob1_time)"); + } + + if ((l_attr_chip_unit_pos == 0xB))/* OBUS2 Chiplet */ + { + FAPI_DBG("Scan ob2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_gptr), + "Error from putRing (ob2_gptr)"); + FAPI_DBG("Scan ob2_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_pll_gptr), + "Error from putRing (ob2_pll_gptr)"); + FAPI_DBG("Scan ob2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_time), + "Error from putRing (ob2_time)"); + } + + if ((l_attr_chip_unit_pos == 0xC))/* OBUS3 Chiplet */ + { + FAPI_DBG("Scan ob3_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_gptr), + "Error from putRing (ob3_gptr)"); + FAPI_DBG("Scan ob3_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_pll_gptr), + "Error from putRing (ob3_pll_gptr)"); + FAPI_DBG("Scan ob3_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_time), + "Error from putRing (ob3_time)"); + } + + if ((l_attr_chip_unit_pos == 0x6))/* XBUS Chiplet */ + { + FAPI_DBG("Scan xb_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_gptr), + "Error from putRing (xb_gptr)"); + FAPI_DBG("Scan xb_io1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_gptr), + "Error from putRing (xb_io1_gptr)"); + FAPI_DBG("Scan xb_io2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_gptr), + "Error from putRing (xb_io2_gptr)"); + FAPI_DBG("Scan xb_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_pll_gptr), + "Error from putRing (xb_pll_gptr)"); + FAPI_DBG("Scan xb_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_time), + "Error from putRing (xb_time)"); + FAPI_DBG("Scan xb_io1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_time), + "Error from putRing (xb_io1_time)"); + FAPI_DBG("Scan xb_io2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_time), + "Error from putRing (xb_io2_time)"); + } + + if ((l_attr_chip_unit_pos == 0xD))/* PCI0 Chiplet */ + { + FAPI_DBG("Scan pci0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_gptr), + "Error from putRing (pci0_gptr)"); + FAPI_DBG("Scan pci0_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_pll_gptr), + "Error from putRing (pci0_pll_gptr)"); + FAPI_DBG("Scan pci0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_time), + "Error from putRing (pci0_time)"); + } + + if ((l_attr_chip_unit_pos == 0xE))/* PCI1 Chiplet */ + { + FAPI_DBG("Scan pci1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_gptr), + "Error from putRing (pci1_gptr)"); + FAPI_DBG("Scan pci1_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_pll_gptr), + "Error from putRing (pci1_pll_gptr)"); + FAPI_DBG("Scan pci1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_time), + "Error from putRing (pci1_time)"); + } + + if ((l_attr_chip_unit_pos == 0xF))/* PCI2 Chiplet */ + { + FAPI_DBG("Scan pci2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_gptr), + "Error from putRing (pci2_gptr)"); + FAPI_DBG("Scan pci2_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_pll_gptr), + "Error from putRing (pci2_pll_gptr)"); + FAPI_DBG("Scan pci2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_time), + "Error from putRing (pci2_time)"); + } + + if ((l_attr_chip_unit_pos == 0x2))/* N0 Chiplet */ + { + FAPI_DBG("Scan n0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_gptr), + "Error from putRing (n0_gptr)"); + FAPI_DBG("Scan n0_nx_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_gptr), + "Error from putRing (n0_nx_gptr)"); + FAPI_DBG("Scan n0_cxa0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_gptr), + "Error from putRing (n0_cxa0_gptr)"); + FAPI_DBG("Scan n0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_time), + "Error from putRing (n0_time)"); + FAPI_DBG("Scan n0_nx_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_time), + "Error from putRing (n0_nx_time)"); + FAPI_DBG("Scan n0_cxa0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_time), + "Error from putRing (n0_cxa0_time)"); + } + + if ((l_attr_chip_unit_pos == 0x3))/* N1 Chiplet */ + { + FAPI_DBG("Scan n1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_gptr), + "Error from putRing (n1_gptr)"); + FAPI_DBG("Scan n1_ioo0_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_gptr), + "Error from putRing (n1_ioo0_gptr)"); + FAPI_DBG("Scan n1_ioo1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_gptr), + "Error from putRing (n1_ioo1_gptr)"); + FAPI_DBG("Scan n1_mcs23_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_gptr), + "Error from putRing (n1_mcs23_gptr)"); + FAPI_DBG("Scan n1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_time), + "Error from putRing (n1_time)"); + FAPI_DBG("Scan n1_ioo0_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_time), + "Error from putRing (n1_ioo0_time)"); + FAPI_DBG("Scan n1_ioo1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_time), + "Error from putRing (n1_ioo1_time)"); + FAPI_DBG("Scan n1_mcs23_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_time), + "Error from putRing (n1_mcs23_time)"); + } + + if ((l_attr_chip_unit_pos == 0x4))/* N2 Chiplet */ + { + FAPI_DBG("Scan n2_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_gptr), + "Error from putRing (n2_gptr)"); + FAPI_DBG("Scan n2_psi_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_gptr), + "Error from putRing (n2_psi_gptr)"); + FAPI_DBG("Scan n2_cxa1_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_gptr), + "Error from putRing (n2_cxa1_gptr)"); + FAPI_DBG("Scan n2_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_time), + "Error from putRing (n2_time)"); + FAPI_DBG("Scan n2_cxa1_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_time), + "Error from putRing (n2_cxa1_time)"); + } + + if ((l_attr_chip_unit_pos == 0x5))/* N3 Chiplet */ + { + FAPI_DBG("Scan n3_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_gptr), + "Error from putRing (n3_gptr)"); + FAPI_DBG("Scan n3_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_time), + "Error from putRing (n3_time)"); + FAPI_DBG("Scan n3_np_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_gptr), + "Error from putRing (n3_np_gptr)"); + FAPI_DBG("Scan n3_mcs01_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_gptr), + "Error from putRing (n3_mcs01_gptr)"); + FAPI_DBG("Scan n3_mcs01_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_time), + "Error from putRing (n3_mcs01_time)"); + FAPI_DBG("Scan n3_np_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_time), + "Error from putRing (n3_np_time)"); + } + } + +fapi_try_exit: + FAPI_INF("p9_sbe_gptr_time_initf: Exiting ..."); + return fapi2::current_err; + +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H new file mode 100644 index 00000000..5a048f1d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_initf.H +/// +/// @brief Load time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_GPTR_TIME_INITF_H_ +#define _P9_SBE_GPTR_TIME_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_gptr_time_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Scan all rings on all enabled chiplets (except for TP) +/// Load Time and GPTR rings for all enabled chiplets +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C new file mode 100644 index 00000000..ff4bde17 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_repr_initf.C +/// +/// @brief Scan0 and Load repair, time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_gptr_time_repr_initf.H" + +#include "p9_perv_scom_addresses.H" +#include "p9_perv_sbe_cmn.H" + + +enum P9_SBE_GPTR_TIME_REPR_INITF_Private_Constants +{ + REGIONS_EXCEPT_VITAL = 0x7FF, + SCAN_TYPES_TIME_GPTR_REPR = 0x230 +}; + +static fapi2::ReturnCode +p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + auto l_perv_functional_vector = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_STATE_FUNCTIONAL); + FAPI_DBG("Entering ..."); + + for (auto l_chplt_trgt : l_perv_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, + l_attr_chip_unit_pos)); + + if (!((l_attr_chip_unit_pos == 0x07 + || l_attr_chip_unit_pos == 0x08/* McChiplet */) || + (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03 + || l_attr_chip_unit_pos == 0x04 + || l_attr_chip_unit_pos == 0x05/* NestChiplet */) || + (l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A + || l_attr_chip_unit_pos == 0x0B + || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) || + (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E + || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) || + (l_attr_chip_unit_pos == 0x06/* XbusChiplet */))) + { + continue; + } + + FAPI_INF("Call sbe_gptr_time_repr_initf_scan0_and_ring_module_function"); + FAPI_TRY(p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function( + l_chplt_trgt)); + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Scan 0 on time, repair, gptr on all enabled chiplets +/// scan initialize GPTR,TIME and REPR Rings +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode +p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("Entering ..."); + + FAPI_INF("Check for chiplet enable"); + //Getting NET_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); + l_read_reg = l_data64.getBit<0>(); //l_read_reg = NET_CTRL0.CHIPLET_ENABLE + + if ( l_read_reg ) + { + FAPI_INF("run scan0 module for regions except vital scan types GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, REGIONS_EXCEPT_VITAL, + SCAN_TYPES_TIME_GPTR_REPR)); + + + //TODO:Load Ring Module : Scan initialize PLL BNDY chain + } + + FAPI_DBG("Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H new file mode 100644 index 00000000..da24195e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_gptr_time_repr_initf.H +/// +/// @brief Scan0 and Load repair, time and GPTR rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_GPTR_TIME_REPR_INITF_H_ +#define _P9_SBE_GPTR_TIME_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_gptr_time_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Scan 0 all rings on all enabled chiplets (except for TP) +/// Load Repair, Time and GPTR rings for all enabled chiplets +/// -- All chip customization data is within the repair and time rings -- array repair, DTS setting +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C new file mode 100644 index 00000000..00e00d24 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C @@ -0,0 +1,134 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_io_initf.C +/// +/// @brief Initialize necessary latches in IP chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_io_initf.H" +#include "p9_perv_scom_addresses.H" +#include "p9_perv_scom_addresses_fld.H" + +fapi2::ReturnCode p9_sbe_io_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_io_initf: Entering ..."); + uint8_t l_attr_chip_unit_pos = 0; + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + +#if 0 + { + // PCIx FURE rings require deterministic scan enable + // no current plan to scan these during mainline IPL, but recipe is below if needed + fapi2::buffer<uint64_t> l_data64; + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC>(); + + if (l_attr_chip_unit_pos == 0xD)/* PCI0 Chiplet */ + { + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI0_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan pci0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_fure), + "Error from putRing (pci0_fure)"); + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI0_CPLT_CTRL0_CLEAR, l_data64)); + } + + if (l_attr_chip_unit_pos == 0xE)/* PCI1 Chiplet */ + { + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI1_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan pci1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_fure), + "Error from putRing (pci1_fure)"); + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI1_CPLT_CTRL0_CLEAR, l_data64)); + } + + if (l_attr_chip_unit_pos == 0xF)/* PCI2 Chiplet */ + { + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI2_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan pci2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_fure), + "Error from putRing (pci2_fure)"); + FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI2_CPLT_CTRL0_CLEAR, l_data64)); + } + } +#endif + + if (l_attr_chip_unit_pos == 0x9)/* OBUS0 Chiplet */ + { + FAPI_DBG("Scan ob0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_fure), + "Error from putRing (ob0_fure)"); + } + + if (l_attr_chip_unit_pos == 0xA)/* OBUS1 Chiplet */ + { + FAPI_DBG("Scan ob1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_fure), + "Error from putRing (ob1_fure)"); + } + + if (l_attr_chip_unit_pos == 0xB)/* OBUS2 Chiplet */ + { + FAPI_DBG("Scan ob2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_fure), + "Error from putRing (ob2_fure)"); + } + + if (l_attr_chip_unit_pos == 0xC)/* OBUS3 Chiplet */ + { + FAPI_DBG("Scan ob3_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_fure), + "Error from putRing (ob3_fure)"); + } + + if (l_attr_chip_unit_pos == 0x6)/* XBUS Chiplet */ + { + FAPI_DBG("Scan xb_io1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_fure), + "Error from putRing (xb_io1_fure)"); + FAPI_DBG("Scan xb_io2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_fure), + "Error from putRing (xb_io2_fure)"); + FAPI_DBG("Scan xb_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_fure), + "Error from putRing (xb_fure)"); + } + } + +fapi_try_exit: + FAPI_INF("p9_sbe_io_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H new file mode 100644 index 00000000..c1f186bd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_io_initf.H +/// +/// @brief Initialize necessary latches in IP chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_IO_INITF_H_ +#define _P9_SBE_IO_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_io_initf_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Apply init file for IO (Xbus, Abus and Pcie) chiplets. +/// +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_io_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C new file mode 100644 index 00000000..25336c49 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_lpc_init.C +/// +/// @brief procedure to initialize LPC to enable communictation to PNOR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_lpc_init.H" + +#include "p9_perv_scom_addresses.H" +#include "p9_perv_scom_addresses_fld.H" + +fapi2::ReturnCode p9_sbe_lpc_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("p9_sbe_lpc_init: Entering ..."); + + // set LPC clock mux select to internal clock + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + l_data64.setBit<1>(); //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_OR, l_data64)); + + // set LPC clock mux select to external clock + //Setting CPLT_CTRL0 register value + l_data64.flush<0>(); + l_data64.setBit<1>(); //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_CLEAR, l_data64)); + + //Settting registers to do an LPC functional reset + l_data64.flush<0>().setBit<CPLT_CONF1_TC_LP_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_OR, l_data64)); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_CLEAR, l_data64)); + + FAPI_DBG("p9_sbe_lpc_init: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H new file mode 100644 index 00000000..eabe73f1 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_lpc_init.H +/// +/// @brief procedure to initialize LPC to enable communictation to PNOR +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_LPC_INIT_H_ +#define _P9_SBE_LPC_INIT_H_ + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_lpc_init_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief LPC init to enable connection to PNOR +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + const uint32_t CPLT_CONF1_TC_LP_RESET = 12; + fapi2::ReturnCode p9_sbe_lpc_init(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C new file mode 100644 index 00000000..63bbe75e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C @@ -0,0 +1,113 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_enable_ridi.C +/// +/// @brief Enable ridi controls for NEST logic +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_enable_ridi.H" + +#include "p9_perv_scom_addresses.H" + +static fapi2::ReturnCode p9_sbe_nest_enable_ridi_net_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_nest_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + auto l_perv_functional_vector = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_STATE_FUNCTIONAL); + FAPI_DBG("p9_sbe_nest_enable_ridi: Entering ..."); + + for (auto l_chplt_trgt : l_perv_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, + l_attr_chip_unit_pos)); + + if (!((l_attr_chip_unit_pos == 0x07 + || l_attr_chip_unit_pos == 0x08/* McChiplet */) || + (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03 + || l_attr_chip_unit_pos == 0x04 + || l_attr_chip_unit_pos == 0x05/* NestChiplet */))) + { + continue; + } + + FAPI_INF("Call p9_sbe_nest_enable_ridi_net_ctrl_action_function"); + FAPI_TRY(p9_sbe_nest_enable_ridi_net_ctrl_action_function(l_chplt_trgt)); + } + + FAPI_DBG("p9_sbe_nest_enable_ridi: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Enable Drivers/Recievers of Nest chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_enable_ridi_net_ctrl_action_function( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + bool l_read_reg = false; + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("p9_sbe_nest_enable_ridi_net_ctrl_action_function: Entering ..."); + + FAPI_INF("Check for chiplet enable"); + //Getting NET_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64)); + l_read_reg = l_data64.getBit<0>(); //l_read_reg = NET_CTRL0.CHIPLET_ENABLE + + if ( l_read_reg ) + { + FAPI_INF("Enable Recievers, Drivers DI1 & DI2"); + //Setting NET_CTRL0 register value + l_data64.flush<0>(); + l_data64.setBit<19>(); //NET_CTRL0.RI_N = 1 + l_data64.setBit<20>(); //NET_CTRL0.DI1_N = 1 + l_data64.setBit<21>(); //NET_CTRL0.DI2_N = 1 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64)); + } + + FAPI_DBG("p9_sbe_nest_enable_ridi_net_ctrl_action_function: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H new file mode 100644 index 00000000..6c7b2dfb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_enable_ridi.H +/// +/// @brief Enable ridi controls for NEST logic +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_ENABLE_RIDI_H_ +#define _P9_SBE_NEST_ENABLE_RIDI_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_nest_enable_ridi_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Enable Drivers/Receivers of Nest Chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C new file mode 100644 index 00000000..434e0137 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C @@ -0,0 +1,135 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_initf.C +/// +/// @brief Scan rings for Nest and Mc chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_initf.H" +#include "p9_perv_scom_addresses.H" +#include "p9_perv_scom_addresses_fld.H" + +fapi2::ReturnCode p9_sbe_nest_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("Entering ..."); + uint8_t l_attr_chip_unit_pos = 0; + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + + if (l_attr_chip_unit_pos == 0x2)/* N0 Chiplet */ + { + FAPI_DBG("Scan n0_cxa_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_fure), + "Error from putRing (n0_cxa0_fure)"); + FAPI_DBG("Scan n0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_fure), + "Error from putRing (n0_fure)"); + FAPI_DBG("Scan n0_nx_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_fure), + "Error from putRing (n0_nx_fure)"); + } + + if (l_attr_chip_unit_pos == 0x3)/* N1 Chiplet */ + { + FAPI_DBG("Scan n1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_fure), + "Error from putRing (n1_fure)"); + FAPI_DBG("Scan n1_ioo0_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_fure), + "Error from putRing (n1_ioo0_fure)"); + FAPI_DBG("Scan n1_ioo1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_fure), + "Error from putRing (n1_ioo1_fure)"); + FAPI_DBG("Scan n1_mcs23_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_fure), + "Error from putRing (n1_mcs23_fure)"); + } + + if (l_attr_chip_unit_pos == 0x4)/* N2 Chiplet */ + { + FAPI_DBG("Scan n2_cxa1_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_fure), + "Error from putRing (n2_cxa1_fure)"); + FAPI_DBG("Scan n2_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_fure), + "Error from putRing (n2_fure)"); + FAPI_DBG("Scan n2_psi_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_fure), + "Error from putRing (n2_psi_fure)"); + } + + if (l_attr_chip_unit_pos == 0x05)/* N3 Chiplet */ + { + FAPI_DBG("Scan n3_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_fure), + "Error from putRing (n3_fure)"); + FAPI_DBG("Scan n3_mcs01_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_fure), + "Error from putRing (n3_mcs01_fure)"); + FAPI_DBG("Scan n3_np_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_fure), + "Error from putRing (n3_np_fure)"); + } + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_fure)); +#if 0 + { + // MC IOMxx FURE rings require deterministic scan enable + // no current plan to scan these during mainline IPL, but recipe is below if needed + fapi2::buffer<uint64_t> l_data64; + l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC>(); + FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_OR, l_data64)); + FAPI_DBG("Scan mc_iom01_fure ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_fure), + "Error from putRing (mc_iom01_fure)"); + FAPI_DBG("Scan mc_iom23_fure ring"); + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_fure), + "Error from putRing (mc_iom23_fure)"); + FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_CLEAR, l_data64)); + } +#endif + + } + +fapi_try_exit: + FAPI_INF("Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H new file mode 100644 index 00000000..90a8321e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_initf.C +/// +/// @brief Scan rings for Nest and Mc chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_NEST_INITF_H_ +#define _P9_SBE_NEST_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_nest_initf_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief apply init file +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C new file mode 100644 index 00000000..d0737f78 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C @@ -0,0 +1,388 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_startclocks.C +/// +/// @brief start PB and Nest clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_nest_startclocks.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_NEST_STARTCLOCKS_Private_Constants +{ + CLOCK_CMD = 0x1, + STARTSLAVE = 0x1, + STARTMASTER = 0x1, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE, + CLOCK_TYPES = 0x7, + DONT_STARTMASTER = 0x0, + DONT_STARTSLAVE = 0x0 +}; + +static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg); + +static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_nest_startclocks_nest_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +fapi2::ReturnCode p9_sbe_nest_startclocks(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_read_attr = 0; + fapi2::buffer<uint8_t> l_read_flush_attr; + fapi2::buffer<uint32_t> l_attr_pg; + fapi2::buffer<uint64_t> l_pg_vector; + fapi2::buffer<uint64_t> l_clock_regions; + fapi2::buffer<uint64_t> l_n3_clock_regions; + fapi2::buffer<uint16_t> l_ccstatus_regions; + fapi2::buffer<uint16_t> l_n3_ccstatus_regions; + FAPI_INF("p9_sbe_nest_startclocks: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE, i_target_chip, + l_read_flush_attr)); + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_target_cplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_n3_clock_regions)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_target_cplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_n3_ccstatus_regions)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + FAPI_INF("Reading ATTR_MC_SYNC_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); + + fapi2::TargetFilter l_nest_filter, l_nest_tp_filter, l_dd1_filter_without_N3; + + if (l_read_attr) + { + l_nest_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | + fapi2::TARGET_FILTER_ALL_NEST); + l_nest_tp_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC + | fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP); + l_dd1_filter_without_N3 = static_cast<fapi2::TargetFilter> + (fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST | + fapi2::TARGET_FILTER_TP); + } + else + { + l_nest_filter = fapi2::TARGET_FILTER_ALL_NEST; + l_nest_tp_filter = static_cast<fapi2::TargetFilter> + (fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP); + l_dd1_filter_without_N3 = static_cast<fapi2::TargetFilter> + (fapi2::TARGET_FILTER_NEST_NORTH | fapi2::TARGET_FILTER_NEST_SOUTH | + fapi2::TARGET_FILTER_NEST_EAST | fapi2::TARGET_FILTER_TP); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for N3"); + FAPI_TRY(p9_sbe_nest_startclocks_N3_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for N0,N1,N2"); + FAPI_TRY(p9_sbe_nest_startclocks_nest_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + if ( l_read_attr ) + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for MC"); + FAPI_TRY(p9_sbe_nest_startclocks_mc_fence_drop(l_trgt_chplt, l_pg_vector)); + } + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_nest_filter, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_nest_startclocks_get_attr_pg(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Call common_cplt_ctrl_action_function for Nest and Mc chiplets"); + FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_nest_tp_filter, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Call module align chiplets for Nest and Mc chiplets"); + FAPI_TRY(p9_sbe_common_align_chiplets(l_trgt_chplt)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Regions value: %#018lX", l_clock_regions); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_clock_regions)); + + FAPI_DBG("Call module clock start stop for N0, N1, N2"); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, STARTSLAVE, + DONT_STARTMASTER, l_clock_regions, CLOCK_TYPES)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_common_clock_start_stop(l_target_cplt, CLOCK_CMD, + DONT_STARTSLAVE, STARTMASTER, l_n3_clock_regions, CLOCK_TYPES)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH | + fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_ccstatus_regions)); + FAPI_DBG("Regions value: %#018lX", l_ccstatus_regions); + + FAPI_DBG("Call clockstatus check function for N0,N1,N2"); + FAPI_TRY(p9_sbe_common_check_cc_status_function(l_trgt_chplt, CLOCK_CMD, + l_ccstatus_regions, CLOCK_TYPES)); + } + + for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Call clockstatus check function for N3"); + FAPI_TRY(p9_sbe_common_check_cc_status_function(l_target_cplt, CLOCK_CMD, + l_n3_ccstatus_regions, CLOCK_TYPES)); + FAPI_DBG("pg targets vector: %#018lX", l_pg_vector); + } + + if ( l_read_attr ) + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_clock_regions)); + FAPI_DBG("Regions value: %#018lX", l_clock_regions); + + FAPI_DBG("Call module clock start stop for MC01, MC23."); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, + DONT_STARTSLAVE, DONT_STARTMASTER, l_clock_regions, CLOCK_TYPES)); + } + } + + if ( l_read_flush_attr ) + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_dd1_filter_without_N3, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("clear flush_inhibit to go into flush mode"); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); + } + } + else + { + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (l_nest_tp_filter, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("clear flush_inhibit to go into flush mode"); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); + } + } + + FAPI_INF("p9_sbe_nest_startclocks: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for OB chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_nest_startclocks_N3_fence_drop: Entering ..."); + + if ( i_pg_vector.getBit<0>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_nest_startclocks_N3_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief get attr_pg for the chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[out] o_attr_pg ATTR_PG for the chiplet +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg) +{ + FAPI_INF("p9_sbe_nest_startclocks_get_attr_pg: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, o_attr_pg)); + + FAPI_INF("p9_sbe_nest_startclocks_get_attr_pg: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for MC +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + uint8_t l_read_attrunitpos = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_nest_startclocks_mc_fence_drop: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet, + l_read_attrunitpos)); + + if ( l_read_attrunitpos == 0x07 ) + { + if ( i_pg_vector.getBit<4>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + } + + if ( l_read_attrunitpos == 0x08 ) + { + if ( i_pg_vector.getBit<2>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + } + + FAPI_INF("p9_sbe_nest_startclocks_mc_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for pcie chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_nest_startclocks_nest_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_nest_startclocks_nest_fence_drop: Entering ..."); + + if ( i_pg_vector.getBit<4>() == 1 ) + { + FAPI_DBG("Drop chiplet fence"); + //Setting NET_CTRL0 register value + l_data64.flush<1>(); + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); //NET_CTRL0.FENCE_EN = 0 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_nest_startclocks_nest_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H new file mode 100644 index 00000000..efc40a97 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H @@ -0,0 +1,66 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_nest_startclocks.H +/// +/// @brief start PB and Nest clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NEST_STARTCLOCKS_H_ +#define _P9_SBE_NEST_STARTCLOCKS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_nest_startclocks_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --drop vital fence +/// --reset abstclk muxsel and syncclk muxsel +/// --Module align chiplets +/// --Module clock start stop +/// --Check clock stat SL, NSL , ARY +/// --drop chiplet fence +/// --check checkstop register +/// --clear flush inhibit to go into flush mode +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_nest_startclocks(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C new file mode 100644 index 00000000..79e0c0e3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C @@ -0,0 +1,91 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_initf.C +/// +/// @brief apply initfile for level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_npll_initf.H" + +fapi2::ReturnCode p9_sbe_npll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_npll_initf: Entering ..."); + + uint8_t l_read_attr = 0; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + RingID ringID = perv_pll_bndy_bucket_1; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM , l_read_attr), + "Error from FAPI_ATTR_GET (ATTR_NEST_PLL_BUCKET)"); + + switch(l_read_attr) + { + case 1: + ringID = perv_pll_bndy_bucket_1; + break; + + case 2: + ringID = perv_pll_bndy_bucket_2; + break; + + case 3: + ringID = perv_pll_bndy_bucket_3; + break; + + case 4: + ringID = perv_pll_bndy_bucket_4; + break; + + case 5: + ringID = perv_pll_bndy_bucket_5; + break; + + default: + FAPI_ASSERT(false, + fapi2::P9_SBE_NPLL_INITF_UNSUPPORTED_BUCKET(). + set_TARGET(i_target_chip). + set_BUCKET_INDEX(l_read_attr), + "Unsupported Nest PLL bucket value!"); + } + + FAPI_DBG("Scan perv_pll_bndy_bucket_%d ring", l_read_attr); + FAPI_TRY(fapi2::putRing(i_target_chip, ringID, fapi2::RING_MODE_SET_PULSE_NSL), + "Error from putRing (perv_pll_bndy, ringID: %d)", ringID); + +fapi_try_exit: + FAPI_INF("p9_sbe_npll_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H new file mode 100644 index 00000000..025d2377 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_initf.H +/// +/// @brief apply initfile for level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NPLL_INITF_H_ +#define _P9_SBE_NPLL_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_npll_initf_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --run scan0 module (scan region = PLL, scan_types = GPTR) +/// --run scan0 module (scan region = PLL, scan_types = BNDY/FUNC) +/// --Scan initialize PLL BNDY chain (chiplet = PERV, scan ring = PLL, scan type = BNDY) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_npll_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C new file mode 100644 index 00000000..331fa528 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C @@ -0,0 +1,242 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_setup.C +/// +/// @brief scan initialize level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_npll_setup.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> + + +enum P9_SBE_NPLL_SETUP_Private_Constants +{ + NS_DELAY = 5000000, // unit is nano seconds + SIM_CYCLE_DELAY = 1000 // unit is sim cycles +}; + +fapi2::ReturnCode p9_sbe_npll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + uint8_t l_read_attr = 0; + fapi2::buffer<uint64_t> l_data64_root_ctrl8; + fapi2::buffer<uint64_t> l_data64_perv_ctrl0; + FAPI_INF("p9_sbe_npll_setup: Entering ..."); + + FAPI_DBG("Reading ROOT_CTRL8 register value"); + //Getting ROOT_CTRL8 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); //l_data64_root_ctrl8 = PIB.ROOT_CTRL8 + + + FAPI_DBG("Reading ATTR_SS_FILTER_BYPASS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip, + l_read_attr)); + + if ( l_read_attr == 0x0 ) + { + FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_SS0_PLL_TEST_EN = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + FAPI_DBG("Release SS PLL reset"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_SS0_PLL_RESET = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check SS PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<0>(), + fapi2::SS_PLL_LOCK_ERR() + .set_SS_PLL_READ(l_read_reg), + "ERROR:SS PLL LOCK NOT SET"); + + FAPI_DBG("Release SS PLL Bypass"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_SS0_PLL_BYPASS = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Reading ATTR_CP_FILTER_BYPASS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, + l_read_attr)); + + if ( l_read_attr == 0x0 ) + { + FAPI_DBG("Drop PLL test enable for CP Filter PLL"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT1_PLL_TEST_EN = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + FAPI_DBG("Release CP Filter PLL reset"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT1_PLL_RESET = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<1>(), + fapi2::CP_FILTER_PLL_LOCK_ERR() + .set_CP_FILTER_PLL_READ(l_read_reg), + "ERROR:CP FILTER PLL LOCK NOT SET"); + + FAPI_DBG("Release CP filter PLL Bypass Signal"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT1_PLL_BYPASS = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Reading ATTR_IO_FILTER_BYPASS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, + l_read_attr)); + + if ( l_read_attr == 0x0 ) + { + FAPI_DBG("Drop PLL test enable for IO Filter PLL"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT0_PLL_TEST_EN = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + FAPI_DBG("Release IO Filter PLL reset"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT0_PLL_RESET = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<2>(), + fapi2::IO_FILTER_PLL_LOCK_ERR() + .set_IO_FILTER_PLL_READ(l_read_reg), + "ERROR:IO FILTER PLL LOCK NOT SET"); + + FAPI_DBG("Release IO filter PLL Bypass Signal"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_FILT0_PLL_BYPASS = 0 + l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Drop PLL test enable for Nest PLL"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + //PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + + FAPI_DBG("Reading ATTR_MC_SYNC_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr)); + + if ( l_read_attr == 1 ) + { + FAPI_DBG("Set MUX to Nest Clock input"); + //Setting ROOT_CTRL8 register value + //PIB.ROOT_CTRL8.TP_PLL_CLKIN_SEL4_DC = 1 + l_data64_root_ctrl8.setBit<PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM, + l_data64_root_ctrl8)); + } + + FAPI_DBG("Release Nest PLL reset"); + //Setting PERV_CTRL0 register value + //PIB.PERV_CTRL0.TP_PLLRST_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + + fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); + + FAPI_DBG("check NEST PLL lock"); + //Getting PLL_LOCK_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG, + l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG + + FAPI_ASSERT(l_read_reg.getBit<3>(), + fapi2::NEST_PLL_ERR() + .set_NEST_PLL_READ(l_read_reg), + "ERROR:NEST PLL LOCK NOT SET"); + + FAPI_DBG("Release PLL bypass2"); + //Setting PERV_CTRL0 register value + //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64_perv_ctrl0)); + + FAPI_INF("p9_sbe_npll_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H new file mode 100644 index 00000000..b05c7db1 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H @@ -0,0 +1,71 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_npll_setup.H +/// +/// @brief scan initialize level 0 & 1 PLLs +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_NPLL_SETUP_H_ +#define _P9_SBE_NPLL_SETUP_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_npll_setup_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Release PLL test enable for SS, Filt & NEST PLLs +/// --Release SS PLL reset0 +/// --check SS PLL lock +/// --Release SS PLL bypass0 +/// --Release Filter PLL reset1 +/// --check PLL lock for Filter PLLs +/// --Release Filter PLL bypass signals +/// --Switch MC meshs to Nest mesh +/// --Release test_pll_bypass2 +/// --Release Tank PLL reset2 +/// --check Nest PLL lock +/// --Release Tank PLL bypass2 +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_npll_setup(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C new file mode 100644 index 00000000..9dc91da6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C @@ -0,0 +1,177 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_repr_initf.C +/// +/// @brief Load Repair rings for all enabled chiplets +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#include "p9_sbe_repr_initf.H" +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + uint8_t l_attr_chip_unit_pos = 0; + FAPI_INF("p9_sbe_repr_initf: Entering ..."); + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_repr)); + } + + for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos)); + + if (l_attr_chip_unit_pos == 0x9)/* OBUS0 Chiplet */ + { + FAPI_DBG("Scan ob0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob0_repr), + "Error from putRing (ob0_repr)"); + } + + if (l_attr_chip_unit_pos == 0xA)/* OBUS1 Chiplet */ + { + FAPI_DBG("Scan ob1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob1_repr), + "Error from putRing (ob1_repr)"); + } + + if (l_attr_chip_unit_pos == 0xB)/* OBUS2 Chiplet */ + { + FAPI_DBG("Scan ob2_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob2_repr), + "Error from putRing (ob2_repr)"); + } + + if (l_attr_chip_unit_pos == 0xC)/* OBUS3 Chiplet */ + { + FAPI_DBG("Scan ob3_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, ob3_repr), + "Error from putRing (ob3_repr)"); + } + + if (l_attr_chip_unit_pos == 0x6)/* XBUS Chiplet */ + { + FAPI_DBG("Scan xb_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_repr), + "Error from putRing (xb_repr)"); + FAPI_DBG("Scan xb_io1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_repr), + "Error from putRing (xb_io1_repr)"); + FAPI_DBG("Scan xb_io2_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_repr), + "Error from putRing (xb_io2_repr)"); + } + + if (l_attr_chip_unit_pos == 0xD)/* PCI0 Chiplet */ + { + FAPI_DBG("Scan pci0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci0_repr), + "Error from putRing (pci0_repr)"); + } + + if (l_attr_chip_unit_pos == 0xE)/* PCI1 Chiplet */ + { + FAPI_DBG("Scan pci1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci1_repr), + "Error from putRing (pci1_repr)"); + } + + if (l_attr_chip_unit_pos == 0xF)/* PCI2 Chiplet */ + { + FAPI_DBG("Scan pci2_repr_ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, pci2_repr), + "Error from putRing (pci2_repr)"); + } + + if (l_attr_chip_unit_pos == 0x2)/* N0 Chiplet */ + { + FAPI_DBG("Scan n0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_repr), + "Error from putRing (n0_repr)"); + FAPI_DBG("Scan n0_nx_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_repr), + "Error from putRing (n0_nx_repr)"); + FAPI_DBG("Scan n0_cxa0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_repr), + "Error from putRing (n0_cxa0_repr)"); + } + + if (l_attr_chip_unit_pos == 0x3)/* N1 Chiplet */ + { + FAPI_DBG("Scan n1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_repr), + "Error from putRing (n1_repr)"); + FAPI_DBG("Scan n1_ioo0_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_repr), + "Error from putRing (n1_ioo0_repr)"); + FAPI_DBG("Scan n1_ioo1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_repr), + "Error from putRing (n1_ioo1_repr)"); + FAPI_DBG("Scan n1_mcs23_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_repr), + "Error from putRing (n1_mcs23_repr)"); + } + + if (l_attr_chip_unit_pos == 0x4)/* N2 Chiplet */ + { + FAPI_DBG("Scan n2_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_repr), + "Error from putRing (n2_repr)"); + FAPI_DBG("Scan n2_cxa1_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_repr), + "Error from putRing (n2_cxa1_repr)"); + } + + if (l_attr_chip_unit_pos == 0x5)/* N3 Chiplet */ + { + FAPI_DBG("Scan n3_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_repr), + "Error from putRing (n3_repr)"); + FAPI_DBG("Scan n3_mcs01_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_repr), + "Error from putRing (n3_mcs01_repr)"); + FAPI_DBG("Scan n3_np_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_repr), + "Error from putRing (n3_np_repr)"); + } + } + +fapi_try_exit: + FAPI_INF("p9_sbe_repr_initf: Exiting ..."); + return fapi2::current_err; + +} + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H new file mode 100644 index 00000000..b5dbbe99 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_repr_initf.C +/// +/// @brief Initialize REPR for PERV chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_REPR_INITF_H_ +#define _P9_SBE_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Scan Repair for all Perv Chiplets except TP, EC, EP +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C new file mode 100644 index 00000000..af7c2299 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C @@ -0,0 +1,494 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_select_ex.C +/// @brief Select the Hostboot core from the available cores on the chip +/// +// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: SBE +/// +/// +/// +/// High-level procedure flow: +/// @verbatim +/// Following MC groups are needed to be setup for istep 4 use: +/// - MC group 3: Core(s) (eg ECs); use EC MC group register 3 +/// - MC group 4: EQ(s); use EQ MC group register 2 +/// - MC group 5: Even EXs; use EQ MC group register 3 +/// - MC group 6: Odd Exs; use EQ MC group register 4 +/// +/// Prerequisite: istep 2 will setup the above groups with ALL the good +/// elements represented. +/// +/// This procedure will REMOVE entities from these groups in SINGLE mode; +/// in ALL mode, the groups are not changed. In either case, the OCC +/// registers are written with the valid configuration. Additionally, +/// default PFET controller delays are written into all configured +/// EC and EQ chiplets so that istep 4 power-on operations will +/// succeed. +/// +/// Parameter indicates single core or all (controlled by Cronus/SBE) +/// +/// loop over functional cores { +/// if mode == SINGLE { +/// if first one { +/// Record the master core, EX and EQ number +/// } +/// else { +/// Remove from MC Group 3 +/// } +/// } +/// Set bits in core and EX scoreboard for later updating the OCC +/// Set default PFET controller delay values into Core +/// } +/// +/// loop over functional EQs { +/// if mode == SINGLE { +/// if not master EQ { +/// Remove from MC Groups 4 +/// for the EXs in the EQ { +/// if not master EX && bit is set in EX scoreboard +/// Remove from MC Group 5 if Even (EX0) +/// Remove from MC Group 6 if Odd (EX1) +/// } +/// Set default PFET controller delay values into EQ +/// } +/// +/// Write resultant scoreboard EQ/Core mask into OCC complex +/// - This is the "master record " of the enabled cores/quad in the system +/// - This is only for during the IPL (will be updated later in step 15) +/// @endverbatim + +// ----------------------------------------------------------------------------- +// Includes +// ----------------------------------------------------------------------------- +#include "p9_sbe_select_ex.H" +#include "p9_common_poweronoff.H" + +// ----------------------------------------------------------------------------- +// Definitions +// ----------------------------------------------------------------------------- + +static const uint32_t NUM_EX_PER_EQ = 2; + +static const uint8_t CORE_CHIPLET_START = 0x20; +static const uint8_t CORE_CHIPLET_COUNT = 24; + +static const uint8_t CORE_STOP_MC_GROUP = 3; +static const uint8_t EQ_STOP_MC_GROUP = 4; +static const uint8_t EX_EVEN_STOP_MC_GROUP = 5; +static const uint8_t EX_ODD_STOP_MC_GROUP = 6; +static const uint8_t BROADCAST_GROUP = 7; + +// Use PERV addressses as the accesses to the cores and EQ use PERV targets +static const uint64_t CORE_MC_REG = PERV_MULTICAST_GROUP_3; +static const uint64_t EQ_MC_REG = PERV_MULTICAST_GROUP_2; +static const uint64_t EX_EVEN_MC_REG = PERV_MULTICAST_GROUP_3; +static const uint64_t EX_ODD_MC_REG = PERV_MULTICAST_GROUP_4; + +// Note: in the above, the EX MC groups really live in the EQ chiplet, not the +// core! + +static const uint8_t PERV_EQ_START = 0x10; +static const uint8_t PERV_EQ_COUNT = 6; +static const uint8_t PERV_CORE_START = 0x20; +static const uint8_t PERV_CORE_COUNT = 24; + +// ----------------------------------------------------------------------------- +// Function prototypes +// ----------------------------------------------------------------------------- + +fapi2::ReturnCode select_ex_remove_core_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +fapi2::ReturnCode select_ex_remove_ex_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint32_t i_ex_num); + +fapi2::ReturnCode select_ex_remove_eq_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt); + +// ----------------------------------------------------------------------------- +// Function definitions +// ----------------------------------------------------------------------------- + +// See .H for documentation +fapi2::ReturnCode p9_sbe_select_ex( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9selectex::MODE i_mode) +{ + FAPI_IMP("> p9_sbe_select_ex"); + + fapi2::buffer<uint64_t> l_core_config = 0; + fapi2::buffer<uint64_t> l_quad_config = 0; + fapi2::buffer<uint64_t> l_data64 = 0; + uint8_t attr_force_all = 0; + bool b_single = true; + bool b_host_core_found = false; + bool b_processing_host_core = false; + + uint32_t l_master_ex_num = 0xFF; // invalid EX number initialized + uint32_t l_master_eq_num = 0xFF; // invalid EQ number initialized + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + + auto l_core_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CORES, + fapi2::TARGET_STATE_FUNCTIONAL ); + + auto l_eq_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_CACHES, + fapi2::TARGET_STATE_FUNCTIONAL ); + + // Read the "FORCE_ALL" attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, + FAPI_SYSTEM, + attr_force_all)); + + // Set the flow mode and respect the force mode + if (attr_force_all || i_mode == p9selectex::ALL) + { + b_single = false; + FAPI_DBG("All cores mode"); + } + else + { + FAPI_DBG("Single core mode: Number of candidate cores = %d, Number of candidate caches = %d", + l_core_functional_vector.size(), + l_eq_functional_vector.size()); + } + + // Loop through the core functional vector. The first core in the vector + // is going to be the hostboot core as the FAPI platform code is expected + // to return the vector elements in acsending order; thus, the first vector + // entry is the lowest numbered, valid core. + // + // Two buffers track the core and EX configuration as though "ALL" is the + // mode chosen. This is done to reduce conditional processing within the + // vector loop to allow for better prefetch utilization. + + for (auto core : l_core_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + core, + l_attr_chip_unit_pos)); + + // Needed as core is a PERV target + uint32_t l_core_num = static_cast<uint32_t>(l_attr_chip_unit_pos - PERV_CORE_START); + + FAPI_DBG("Functional core l_attr_chip_unit_pos 0x%02X, l_core_num = 0x%02X", + l_attr_chip_unit_pos, l_core_num); + + uint32_t l_ex_num = l_core_num / 2; + uint32_t l_eq_num = l_core_num / 4; + + if (b_single) + { + b_processing_host_core = false; + + if (!b_host_core_found) + { + + l_master_ex_num = l_ex_num; + l_master_eq_num = l_eq_num; + + uint8_t l_short_core_num = static_cast<uint8_t>(l_core_num); + FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_MASTER_CORE, + i_target, + l_short_core_num)); + + uint8_t l_short_ex_num = static_cast<uint8_t>(l_ex_num); + FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_MASTER_EX, + i_target, + l_short_ex_num)); + + FAPI_DBG("MASTER core chiplet %d 0x%02X; EX %d 0x%02X", + l_core_num, l_core_num, + l_master_ex_num, l_master_ex_num); + + b_host_core_found = true; + b_processing_host_core = true; + + } // host_core_found + + // Remove the core from the apppropriate multicast group if not + // the host core + if (!b_processing_host_core) + { + FAPI_TRY(select_ex_remove_core_from_mc_group(core)); + } + + } // Single + + // To save code space in the SBE, the assumption is made that if the core + // is good (eg in the core functional vector), then the EX associated with + // it is also good. No checking is performed on the associated the EX + // targets to check this. + // + // Thus, set the bits in the buffers for the OCC configuration register + // update + FAPI_DBG("core num = %d, ex num = %d", + l_core_num, l_ex_num); + l_core_config.setBit(l_core_num); + l_quad_config.setBit(l_ex_num); + + FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX EX 0x%016llX", + l_core_config, l_quad_config); + + // Write the default PFET Controller Delay values for the Core + // as it will be used for istep 4 + FAPI_DBG("Setting PFET Delays in core %d", l_core_num); + + l_data64.flush<0>() + .insertFromRight<0, 4>(p9power::PFET_DELAY_POWERDOWN_CORE) + .insertFromRight<4, 4>(p9power::PFET_DELAY_POWERUP_CORE); + + FAPI_TRY(fapi2::putScom(core, + C_PPM_PFDLY - 0x20000000, // Create chip address base + l_data64), + "Error: Core PFET Delay register"); + + } // Core loop + + // Process the good EQs + for (auto eq : l_eq_functional_vector) + { + uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + eq, + l_attr_chip_unit_pos)); + + // Needed as eq is a PERV target + uint32_t l_eq_num = static_cast<uint32_t>(l_attr_chip_unit_pos - PERV_EQ_START); + + FAPI_DBG("Functional EQ l_attr_chip_unit_pos 0x%02X, l_eq_num = 0x%02X", + l_attr_chip_unit_pos, l_eq_num); + + if (b_single) + { + if (l_eq_num != l_master_eq_num) + { + FAPI_TRY(select_ex_remove_eq_from_mc_group(eq)); + } + + for (auto i = l_eq_num * NUM_EX_PER_EQ; i < (l_eq_num + 1)*NUM_EX_PER_EQ; ++i) + { + FAPI_DBG("ex = %d, master ex = %d, quad bit[%d] = %d", + i, l_master_ex_num, i, l_quad_config.getBit(i)); + + // Remove from MC group if not master EX and configured + if ((i != l_master_ex_num) && l_quad_config.getBit(i)) + { + FAPI_TRY(select_ex_remove_ex_from_mc_group(eq, i)); + } + } + + } // Single + + FAPI_DBG("Setting PFET Delays in EQ %d", l_eq_num); + + // Write the default PFET Controller Delay values for the EQs + // that will be used for istep 4 + l_data64.flush<0>() + .insertFromRight<0, 4>(p9power::PFET_DELAY_POWERDOWN_EQ) + .insertFromRight<4, 4>(p9power::PFET_DELAY_POWERUP_EQ); + + FAPI_TRY(fapi2::putScom(eq, + EQ_PPM_PFDLY - 0x10000000, // Create chip address base + l_data64), + "Error: EQ PFET Delay register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + + + } // EQ loop + + + // Write to the OCC Core Configuration Status Register + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_CCSR_SCOM2, l_core_config)); + + // Write to the OCC Quad Configuration Status Register + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QCSR_SCOM2, l_quad_config)); + + // Write default value the OCC Quad Status Status Register + l_data64.flush<0>() + .setBit<0, 12>() // L2 Stopped + .setBit<14, 6>(); // Quad Stopped + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QSSR_SCOM2, l_data64)); + +fapi_try_exit: + FAPI_INF("< p9_sbe_select_ex"); + + return fapi2::current_err; +} // END p9_sbe_select_ex + +///----------------------------------------------------------------------------- +/// @brief Remve core chiplet from Dynamic cores multicast group +/// +/// @param[in] i_target_cplt Reference to TARGET_TYPE_PERV target +/// that is a core +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode select_ex_remove_core_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + FAPI_INF("> remove_from_core_mc_group..."); + + fapi2::buffer<uint64_t> l_data64 = 0; + + // Entering group + l_data64.insertFromRight<0, 3>(0x7); + l_data64.insertFromRight<3, 3>(BROADCAST_GROUP); + // Removed group + l_data64.insertFromRight<19, 3>(CORE_STOP_MC_GROUP); + +#ifndef __PPE__ + uint8_t l_attr_chip_unit_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + i_target_cplt, + l_attr_chip_unit_pos)); + + FAPI_DBG("Removing Core %d from MC group %d", + l_attr_chip_unit_pos - PERV_CORE_START, + CORE_STOP_MC_GROUP ); +#endif + + FAPI_TRY(fapi2::putScom(i_target_cplt, + CORE_MC_REG, + l_data64), + "Error: Core MC group register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + +fapi_try_exit: + FAPI_INF("< remove_from_core_mc_group..."); + return fapi2::current_err; + +} + +///----------------------------------------------------------------------------- +/// @brief Remove EX from multicast group +/// +/// @param[in] i_ex_num EX number that needs to be removed from an MC group +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode select_ex_remove_ex_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt, + const uint32_t i_ex_num) +{ + FAPI_INF("> select_ex_remove_ex_from_mc_group..."); + + // If the Core is in a even EX, then put the EQ chiplet in the EQ MC group + // and the EX Even MC group. + + // If the Core is in a odd EX, then put the EQ chiplet in the EQ MC group + // and the EX Odd MC group. + + fapi2::buffer<uint64_t> l_data64 = 0; + + // Entering group + l_data64.insertFromRight<0, 3>(0x7); + l_data64.insertFromRight<3, 3>(BROADCAST_GROUP); + + if (i_ex_num % 2) // Odd EX + { + FAPI_DBG("Removing EX %d (Odd) from MC group %d", + i_ex_num, + EX_ODD_STOP_MC_GROUP); + + // Removed group + l_data64.insertFromRight<19, 3>(EX_ODD_STOP_MC_GROUP); + + FAPI_TRY(fapi2::putScom(i_target_cplt, + EX_ODD_MC_REG, + l_data64), + "Error: EX Odd MC group register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + + } + else // Even EX + { + FAPI_DBG("Removing EX %d (Even) from MC group %d", + i_ex_num, + EX_EVEN_STOP_MC_GROUP); + + + // Removed group + l_data64.insertFromRight<19, 3>(EX_EVEN_STOP_MC_GROUP); + + FAPI_TRY(fapi2::putScom(i_target_cplt, + EX_EVEN_MC_REG, + l_data64), + "Error: EX Even MC group register, rc 0x%.16X", + (uint32_t)fapi2::current_err); + } + +fapi_try_exit: + FAPI_INF("< select_ex_remove_ex_from_mc_group..."); + return fapi2::current_err; + +} + +///----------------------------------------------------------------------------- +/// @brief Remove EX from multicast group +/// +/// @param[in] i_ex_num EX number for which the EQ needs to be in MC group +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode select_ex_remove_eq_from_mc_group( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt) +{ + FAPI_INF("> select_ex_remove_eq_from_mc_group..."); + + fapi2::buffer<uint64_t> l_data64; + + // Entering group + l_data64.insertFromRight<0, 3>(0x7); + l_data64.insertFromRight<3, 3>(BROADCAST_GROUP); + // Removed group + l_data64.insertFromRight<19, 3>(EQ_STOP_MC_GROUP); + +#ifndef __PPE__ + uint8_t l_attr_chip_unit_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + i_target_cplt, + l_attr_chip_unit_pos)); + + FAPI_DBG("Removing EQ %d from MC group %d", + l_attr_chip_unit_pos - PERV_EQ_START, + EQ_STOP_MC_GROUP ); +#endif + + FAPI_TRY(fapi2::putScom(i_target_cplt, + EQ_MC_REG, + l_data64), + "Error: EQ MC group register, rc 0x%.8X", + (uint32_t)fapi2::current_err); + +fapi_try_exit: + FAPI_INF("< select_ex_remove_eq_from_mc_group..."); + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H new file mode 100644 index 00000000..3c40e9aa --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H @@ -0,0 +1,85 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_select_ex.H +/// @brief Select the Hostboot core from the available cores on the chip +/// +// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: SBE +/// + +#ifndef _P9_SBE_SELECT_EX_H_ +#define _P9_SBE_SELECT_EX_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi2.H> +#include <p9_misc_scom_addresses.H> +#include <p9_quad_scom_addresses.H> +#include <p9_perv_scom_addresses.H> + + +namespace p9selectex +{ +// valid domain options +enum MODE +{ + SINGLE, // Only the first core + ALL // All Core +}; + +} // namespace p9selectex + + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_select_ex_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + p9selectex::MODE); + +extern "C" { + +// ----------------------------------------------------------------------------- +// Function prototype +// ----------------------------------------------------------------------------- + +/// @brief Select the Hostboot core from the available cores on the chip +/// +/// @param [in] i_target Chip target +/// @param [in] i_mode SINGLE core (enable only the first core found); +/// ALL cores (enable all configured cores found) +/// + fapi2::ReturnCode p9_sbe_select_ex( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + p9selectex::MODE i_mode); + +} // extern "C" + +#endif // _P9_SBE_SELECT_EX_H_ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C new file mode 100644 index 00000000..420680f7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C @@ -0,0 +1,151 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_sbe_setup_boot_freq.C +/// @brief Setup Boot Frequency +/// +// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : SBE +// *Level : 2 +/// +/// @verbatim +/// +/// Procedure Summary: +/// - Read frequency ATTR and write to the Quad PPM DPLL Freq Ctrl register +/// +/// @endverbatim + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +#include "p9_sbe_setup_boot_freq.H" +#include "p9_quad_scom_addresses.H" + +enum P9_SBE_SETUP_BOOT_FREQ_CONSTANTS +{ + +// Default configuration settings + +// Default boot_frequency in terms of a multiplier of the refclk frequency/8 +// This is value used if the mailbox value is zero +// +// Value implemented is 3.0GHz, @todo, RTC 140053 - Should it be 2 GHz for P9 ? +// +// 3000MHz / 16.667MHz = ~180 => 0xB4 +// +// Note: the above is aligned, as a value, to 0:10, written as bits 17:27 of PPM DPLL freq ctrl register +// Bits 0:7 are DPLL.MULT_INTG(0:7), and Bits 8:10 are DPLL.MULT_FRAC(0:2) +// + DEFAULT_BOOT_FREQUENCY_MULTIPLIER = 0x00B4, + +}; + +//----------------------------------------------------------------------------- +// Procedure +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +BootFreqInitAttributes(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + uint16_t& i_boot_frequency_multiplier) +{ + + i_boot_frequency_multiplier = DEFAULT_BOOT_FREQUENCY_MULTIPLIER; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target, i_boot_frequency_multiplier)); + + // If attribute values are zero, use the default values (hardcoded) + + // check BOOT FREQ MULT + if (i_boot_frequency_multiplier == 0) + { + // Default voltage if mailbox value is not set + + // @todo, L3 phase Eventually, this should replaced with an error point + // to indicate that the mailbox -> attributes haven't been setup + + i_boot_frequency_multiplier = DEFAULT_BOOT_FREQUENCY_MULTIPLIER; + FAPI_INF("DPLL boot frequency not set in attributes. Setting to default of %d (%x)", + i_boot_frequency_multiplier, i_boot_frequency_multiplier); + } + else + { + FAPI_INF("DPLL boot frequency = %d (%x)", + i_boot_frequency_multiplier, i_boot_frequency_multiplier); + } + +fapi_try_exit: + return fapi2::current_err; +} // BootFreqInitAttributes + + +fapi2::ReturnCode +setDPLLFrequency(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint16_t i_DpllBootFreqMult + ) +{ + fapi2::buffer<uint64_t> l_data; + + + auto l_present_eqs = i_target.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL); + + l_data.insertFromRight<17, 11>(i_DpllBootFreqMult); + + for(auto l_tlst : l_present_eqs) + { + FAPI_TRY(fapi2::putScom(l_tlst, EQ_QPPM_DPLL_FREQ, l_data)); + //@todo,Determine ff_slew rate value RTC 140053 + FAPI_TRY(fapi2::putScom(l_tlst, EQ_QPPM_DPLL_CTRL, 0)); + + } + +fapi_try_exit: + return fapi2::current_err; +} + + +// Hardware procedure +fapi2::ReturnCode +p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + // Boot frequency variable + uint16_t l_boot_frequency_multiplier; + + // Read Boot freq mult attribute + FAPI_TRY(BootFreqInitAttributes(i_target, l_boot_frequency_multiplier)); + + // Set Boot Frequency + + FAPI_TRY(setDPLLFrequency(i_target, + l_boot_frequency_multiplier), + "Setting Boot Frequency"); + +fapi_try_exit: + return fapi2::current_err; + +} // Procedure diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H new file mode 100644 index 00000000..c41909ae --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9_sbe_setup_boot_freq.H +/// @brief Setup Boot Frequency +/// +/// *HW Owner : Sudheendra K Srivathsa <sudheendraks@in.ibm.com> +/// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *Team : PM +/// *Consumed by : SBE +/// *Level : 2 +/// + +#ifndef __P9_SBE_SETUP_BOOT_FREQ_H__ +#define __P9_SBE_SETUP_BOOT_FREQ_H__ + +/// @typedef p9_sbe_setup_boot_freq_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_sbe_setup_boot_freq_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +extern "C" +{ + +/// @brief Read an attribute containing the boot frequency and set that +/// into each configured EQ chiplet. +/// @param [in] i_target TARGET_TYPE_PROC_CHIP +/// @attr +/// @attritem ATTR_BOOT_FREQ_MULT - 11 bit frequency multiplier of refclk +/// @return FAPI2_RC_SUCCESS + fapi2::ReturnCode + p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +} // extern C + +#endif // __P9_SBE_SETUP_BOOT_FREQ_H__ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C new file mode 100644 index 00000000..e7797e75 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C @@ -0,0 +1,82 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_setup_evid.C +/// @brief Setup External Voltage IDs and Boot Frequency +/// +// *HW Owner : Greg Still <stillgs@us.ibm.com> +// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *Team : PM +// *Consumed by : SBE +// *Level : 1 +/// +/// @verbatim +/// Procedure Summary: +/// - Use Attributes to send VDD, VCS via the AVS bus to VRMs +/// - Use Attributes to adjust the VDN and send via I2C to VRM +/// - Read core frequency ATTR and write to the Quad PPM +/// @endverbatim + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +#include "p9_sbe_setup_evid.H" + +//----------------------------------------------------------------------------- +// Procedure +//----------------------------------------------------------------------------- + +fapi2::ReturnCode +p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + + //fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + + // Substep indicators + + // commented out in Level 1 to not have "unused variable" warnings + // until the SBE substep management "macro" or "call" is defined. + + // const uint32_t STEP_SBE_EVID_START = 0x1; + // const uint32_t STEP_SBE_EVID_CONFIG = 0x2; + // const uint32_t STEP_SBE_EVID_WRITE_VDN = 0x3; + // const uint32_t STEP_SBE_EVID_POLL_VDN_STATUS = 0x4; + // const uint32_t STEP_SBE_EVID_WRITE_VDD = 0x5; + // const uint32_t STEP_SBE_EVID_POLL_VDD_STATUS = 0x6; + // const uint32_t STEP_SBE_EVID_WRITE_VCS = 0x7; + // const uint32_t STEP_SBE_EVID_POLL_VCS_STATUS = 0x8; + // const uint32_t STEP_SBE_EVID_TIMEOUT = 0x9; + // const uint32_t STEP_SBE_EVID_BOOT_FREQ = 0xA; + // const uint32_t STEP_SBE_EVID_COMPLETE = 0xB; + +// The inclusion of the following will cause a "label 'fapi_try_exit' defined but not used" +// compile error in Cronus. This will be uncommented when FAPI_TRY functions are added +// during the real procedure development. However, this is NOT needed for Level 1. +//fapi_try_exit: + return fapi2::current_err; + +} // Procedure + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H new file mode 100644 index 00000000..a1ab2263 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_sbe_setup_evid.H +/// @brief Setup External Voltage IDs and Boot Frequency +/// +/// *HW Owner : Greg Still <stillgs@us.ibm.com> +/// *FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *Team : PM +/// *Consumed by : SBE +/// *Level : 1 +/// + +#ifndef __P9_SBE_SETUP_EVID_H__ +#define __P9_SBE_SETUP_EVID_H__ + +extern "C" +{ + +/// @typedef p9_sbe_setup_evid_FP_t +/// function pointer typedef definition for HWP call support + typedef fapi2::ReturnCode (*p9_sbe_setup_evid_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Read attributes containing this part's boot voltages (VDD, VCS and VDN) +/// and set these voltage using the AVSBUS interface (VDD, VCS) an I2C (VDN). +/// Also reads a differnt attribute containing the boot frequency and set that +/// into each configured EQ chiplet. +/// @param [in] i_target TARGET_TYPE_PROC_CHIP +/// @attr +/// @attritem ATTR_BOOT_FREQ uint16_t - 9 bit frequency multiplier of the refclk right justified +/// @attritem ATTR_VCS_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VCS rail +/// @attritem ATTR_VDD_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VDD rail +/// @attritem ATTR_VDN_BOOT_VOLTAGE uint16_t - 1mV grandularity setting for the VDN rail +/// +/// @retval FAPI_RC_SUCCESS + fapi2::ReturnCode + p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + + +} // extern C + +#endif // __P9_SBE_SETUP_EVID_H__ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C new file mode 100644 index 00000000..f55ae68d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C @@ -0,0 +1,327 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.C +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_startclock_chiplets.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_STARTCLOCK_CHIPLETS_Private_Constants +{ + DONT_STARTMASTER = 0x0, + DONT_STARTSLAVE = 0x0, + CLOCK_CMD = 0x1, + CLOCK_TYPES = 0x7, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE +}; + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint8_t i_attr); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_sync_config( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +static fapi2::ReturnCode p9_sbe_startclock_chiplets_xb_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector); + +fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_pg_vector; + fapi2::buffer<uint64_t> l_regions; + fapi2::buffer<uint8_t> l_attr_obus_ratio; + fapi2::buffer<uint32_t> l_attr_pg; + FAPI_INF("p9_sbe_startclock_chiplets: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, + l_attr_obus_ratio)); + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_startclock_chiplets_set_ob_ratio(l_trgt_chplt, + l_attr_obus_ratio)); + } + + for (auto l_target_cplt : + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST | + fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector)); + FAPI_DBG("partial good targets vector: %#018lX", l_pg_vector); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_TRY(p9_sbe_startclock_chiplets_get_attr_pg(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Call p9_sbe_common_cplt_ctrl_action_function for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg)); + + FAPI_DBG("Disable listen to sync for all non-master/slave chiplets"); + FAPI_TRY(p9_sbe_startclock_chiplets_sync_config(l_trgt_chplt)); + + FAPI_DBG("call module align chiplets for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_align_chiplets(l_trgt_chplt)); + + FAPI_DBG("Region setup "); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt, + REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_regions)); + FAPI_DBG("Regions value: %#018lX", l_regions); + + FAPI_DBG("Call module clock start stop for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, + DONT_STARTSLAVE, DONT_STARTMASTER, l_regions, CLOCK_TYPES)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for Xbus"); + FAPI_TRY(p9_sbe_startclock_chiplets_xb_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop Chiplet fence for Obus"); + FAPI_TRY(p9_sbe_startclock_chiplets_ob_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("Drop chiplet fence for PCIe"); + FAPI_TRY(p9_sbe_startclock_chiplets_pci_fence_drop(l_trgt_chplt, l_pg_vector)); + } + + for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | + fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), + fapi2::TARGET_STATE_FUNCTIONAL)) + { + FAPI_DBG("call sbe_common_flushmode for xbus, obus, pcie chiplets"); + FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt)); + } + + FAPI_INF("p9_sbe_startclock_chiplets: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief get attr_pg for the chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[out] o_attr_pg ATTR_PG for the chiplet +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + fapi2::buffer<uint32_t>& o_attr_pg) +{ + FAPI_INF("p9_sbe_startclock_chiplets_get_attr_pg: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, o_attr_pg)); + + FAPI_INF("p9_sbe_startclock_chiplets_get_attr_pg: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for OB chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_ob_fence_drop: Entering ..."); + + FAPI_INF("Drop chiplet fence"); + + //Setting NET_CTRL0 register value + if (i_pg_vector.getBit<2>() == 1) + { + l_data64.flush<1>(); + //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<2>() == 1) ? 0 + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_startclock_chiplets_ob_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for pcie chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector Pg vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_pci_fence_drop: Entering ..."); + + FAPI_INF("Drop chiplet fence"); + + //Setting NET_CTRL0 register value + if (i_pg_vector.getBit<3>() == 1) + { + l_data64.flush<1>(); + //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<3>() == 1) ? 0 + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_startclock_chiplets_pci_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief set obus ratio +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr Attribute that holds the OBUS ratio value +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const uint8_t i_attr) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_set_ob_ratio: Entering ..."); + + //Setting CPLT_CONF1 register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_CPLT_CONF1, l_data64)); + l_data64.insertFromRight<16, 2>(i_attr); //CPLT_CONF1.TC_OB_RATIO_DC = i_attr + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CONF1, l_data64)); + + FAPI_INF("p9_sbe_startclock_chiplets_set_ob_ratio: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Disable listen to sync for all non-master / slave chiplets +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_sync_config( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_sync_config: Entering ..."); + + //Setting SYNC_CONFIG register value + FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_SYNC_CONFIG, l_data64)); + l_data64.setBit<4>(); //SYNC_CONFIG.LISTEN_TO_SYNC_PULSE_DIS = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SYNC_CONFIG, l_data64)); + + FAPI_INF("p9_sbe_startclock_chiplets_sync_config: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Drop chiplet fence for XB chiplet +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @param[in] i_pg_vector vector of targets +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_startclock_chiplets_xb_fence_drop( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet, + const fapi2::buffer<uint64_t> i_pg_vector) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_startclock_chiplets_xb_fence_drop: Entering ..."); + + FAPI_INF("Drop chiplet fence"); + + //Setting NET_CTRL0 register value + if (i_pg_vector.getBit<1>() == 1) + { + l_data64.flush<1>(); + //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<1>() == 1) ? 0 + l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64)); + } + + FAPI_INF("p9_sbe_startclock_chiplets_xb_fence_drop: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H new file mode 100644 index 00000000..a9e777f6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_startclock_chiplets.H +/// +/// @brief Start clock procedure for XBUS, OBUS, PCIe +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_STARTCLOCK_CHIPLETS_H_ +#define _P9_SBE_STARTCLOCK_CHIPLETS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_startclock_chiplets_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Start Xbus, Obus, PCIe clocks +/// Start clocks on configured chiplets for all chips (master and slaves) +/// +/// @param[in] i_target_chiplets Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_startclock_chiplets(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplets); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C new file mode 100644 index 00000000..151aa89d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C @@ -0,0 +1,159 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_arrayinit.C +/// +/// @brief SBE PRV Array Init Procedure +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_arrayinit.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +enum P9_SBE_TP_ARRAYINIT_Private_Constants +{ + REGIONS_EXCEPT_PIB_NET_PLL = 0x4FE, + SCAN_TYPES = 0xDCF, + LOOP_COUNTER = 0x0000000000042FFF, + START_ABIST_MATCH_VALUE = 0x0000000F00000000, + SELECT_SRAM = 0x1, + SELECT_EDRAM = 0x0, + PIBMEM_EXCLUDE_ABIST = 0xC000000000000000, + PIBMEM_INCLUDE_ABIST = 0x8000000000000000 +}; + +static fapi2::ReturnCode p9_sbe_tp_arrayinit_sdisn_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set); + +fapi2::ReturnCode p9_sbe_tp_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint8_t> l_attr_read; + + FAPI_INF("p9_sbe_tp_arrayinit: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read)); + + FAPI_DBG("Exclude PIBMEM from TP array init"); + //Setting PIBMEM_REPAIR_REGISTER_0 register value + //PIB.PIBMEM_REPAIR_REGISTER_0 = 0xC000000000000000 + FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0, PIBMEM_EXCLUDE_ABIST )); + + FAPI_DBG("set sdis_n"); + FAPI_TRY(p9_sbe_tp_arrayinit_sdisn_setup( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_attr_read, true)); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_PIB_NET_PLL, l_regions)); + FAPI_DBG("l_regions value: %#018lX", l_regions); + + FAPI_DBG("Call ARRAY INIT Module for Pervasive Chiplet"); + FAPI_TRY(p9_perv_sbe_cmn_array_init_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, LOOP_COUNTER, SELECT_SRAM, + SELECT_EDRAM, START_ABIST_MATCH_VALUE)); + + FAPI_DBG("Call SCAN0 Module for Pervasive Chiplet"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES)); + + FAPI_DBG("clear sdis_n"); + FAPI_TRY(p9_sbe_tp_arrayinit_sdisn_setup( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_attr_read, false)); + + FAPI_DBG("Add PIBMEM back to TP array init"); + //Setting PIBMEM_REPAIR_REGISTER_0 register value + //PIB.PIBMEM_REPAIR_REGISTER_0 = 0x8000000000000000 + FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0, PIBMEM_INCLUDE_ABIST)); + + FAPI_INF("p9_sbe_tp_arrayinit: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief Sdis_n set or clear +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PERV target +/// @param[in] i_attr Attribute to decide to sdis_n setup +/// @param[in] i_set set or clear the LCBES condition +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_tp_arrayinit_sdisn_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip, + const fapi2::buffer<uint8_t> i_attr, + const bool i_set) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_arrayinit_sdisn_setup: Entering ..."); + + if ( i_attr ) + { + if ( i_set ) + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 1 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_OR, l_data64)); + } + else + { + //Setting CPLT_CONF0 register value + l_data64.flush<0>(); + //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 0 + l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_CLEAR, l_data64)); + } + } + + FAPI_INF("p9_sbe_tp_arrayinit_sdisn_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H new file mode 100644 index 00000000..9ab5e359 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_arrayinit.H +/// +/// @brief SBE PRV Array Init Procedure +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_ARRAYINIT_H_ +#define _P9_SBE_TP_ARRAYINIT_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_arrayinit_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Array Init for PRV Cplt +/// -- Scan0 of PRV Chiplet (except PIB/PCB) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_arrayinit(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C new file mode 100644 index 00000000..c953c3cf --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C @@ -0,0 +1,134 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init1.C +/// +/// @brief Initial steps of PIB AND PCB +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init1.H" +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> + + +enum P9_SBE_TP_CHIPLET_INIT1_Private_Constants +{ + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE, + REGIONS_EXCEPT_VITAL_PIB_NET = 0x4FF, // Regions excluding VITAL, PIB and NET + SCAN_TYPES_TIME_GPTR_REPR = 0x230 +}; + +fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint64_t> l_data64; + fapi2::buffer<uint8_t> l_read_attr; + FAPI_INF("p9_sbe_tp_chiplet_init1: Entering ..."); + + FAPI_DBG("Disable local clock gating VITAL"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING, + i_target_chip, l_read_attr)); + FAPI_DBG("l_read_attr is %d", l_read_attr); + + if (l_read_attr) + { + //Getting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64)) + //PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC = 1 + l_data64.setBit<PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, + l_data64)); + } + + FAPI_DBG("Release PCB Reset"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + //PIB.ROOT_CTRL0.PCB_RESET_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Set Chiplet Enable"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1 + l_data64.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Drop TP Chiplet Fence Enable"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0 + l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Drop Global Endpoint reset"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL0_SET_GLOBAL_EP_RESET_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + FAPI_DBG("Switching PIB trace bus to SBE tracing"); + + FAPI_DBG("Drop OOB Mux"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>(); //PIB.ROOT_CTRL0.OOB_MUX = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Region setup call"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET, l_regions)); + FAPI_DBG("l_regions value : %#018lX", l_regions); + + FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES_TIME_GPTR_REPR)); + + FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types except GPTR, TIME, REPR"); + FAPI_TRY(p9_perv_sbe_cmn_scan0_module( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, + SCAN_TYPES_EXCEPT_TIME_GPTR_REPR)); + + FAPI_INF("p9_sbe_tp_chiplet_init1: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H new file mode 100644 index 00000000..39383792 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init1.H +/// +/// @brief Initial steps of PIB AND PCB +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT1_H_ +#define _P9_SBE_TP_CHIPLET_INIT1_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Releases the Pervasive Control Bus (PCB) reset +/// Sets TP chiplet enable +/// Drops pervasive chiplet fences +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C new file mode 100644 index 00000000..69c6f6c3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init2.C +/// +/// @brief Run scan 0 module for pervasive +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init2.H" + + +fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + + FAPI_INF("p9_sbe_tp_chiplet_init2: Entering ..."); + + + FAPI_INF("p9_sbe_tp_chiplet_init2: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H new file mode 100644 index 00000000..34d94425 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init2.H +/// +/// @brief Run scan 0 module for pervasive +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT2_H_ +#define _P9_SBE_TP_CHIPLET_INIT2_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init2_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Initialize TP Hangcounter 6 +/// -- Scan Repair, Time and GPTR for PRV Chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C new file mode 100644 index 00000000..c7af39d3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C @@ -0,0 +1,371 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init3.C +/// +/// @brief TP Chiplet Start Clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_init3.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_perv_sbe_cmn.H> +#include <p9_sbe_common.H> + + +enum P9_SBE_TP_CHIPLET_INIT3_Private_Constants +{ + START_CMD = 0x1, + REGIONS_ALL_EXCEPT_PIB_NET = 0x4FF, + CLOCK_TYPES = 0x7, + HW_NS_DELAY = 100000, // unit is nano seconds + SIM_CYCLE_DELAY = 1000, // unit is sim cycles + POLL_COUNT = 300, // Observed Number of times CBS read for CBS_INTERNAL_STATE_VECTOR + OSC_ERROR_MASK = 0xF700000000000000, // Mask OSC errors + LFIR_ACTION0_VALUE = 0x0000000000000000, + LFIR_ACTION1_VALUE = 0xFFFFBC2BFC7FFFFF, + FIR_MASK_VALUE = 0x0000000000000000 +}; + +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet); + +fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + bool l_read_reg = 0; + fapi2::buffer<uint32_t> l_pfet_value; + fapi2::buffer<uint32_t> l_attr_pfet; + fapi2::buffer<uint64_t> l_regions; + fapi2::buffer<uint64_t> l_kvref_reg; + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_tpchiplet = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0]; + fapi2::buffer<uint64_t> l_data64; + int l_timeout = 0; + FAPI_INF("p9_sbe_tp_chiplet_init3: Entering ..."); + + FAPI_DBG("Reading ATTR_PFET_OFF_CONTROLS"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PFET_OFF_CONTROLS, i_target_chip, + l_pfet_value)); + + FAPI_DBG("Switch pervasive chiplet OOB mux"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>(); //PIB.ROOT_CTRL0.OOB_MUX = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + FAPI_DBG("Reset PCB Master Interrupt Register"); + //Setting INTERRUPT_TYPE_REG register value + //PIB.INTERRUPT_TYPE_REG = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, 0)); + + FAPI_DBG("Clear pervasive chiplet region fence"); + FAPI_TRY(p9_sbe_tp_chiplet_init3_region_fence_setup(l_tpchiplet)); + + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_tpchiplet, + REGIONS_ALL_EXCEPT_PIB_NET, l_regions)); + FAPI_DBG("l_regions value: %#018lX", l_regions); + + FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_regions, + CLOCK_TYPES)); + + FAPI_DBG("Calling clock_test2"); + FAPI_TRY(p9_sbe_tp_chiplet_init3_clock_test2(i_target_chip)); + + FAPI_DBG("Drop FSI fence 5"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + //PIB.ROOT_CTRL0.FENCE5_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL0_SET_FENCE5_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + l_pfet_value.extractToRight<0, 30>(l_attr_pfet); + + FAPI_DBG("Set pfet off controls"); + //Setting DISABLE_FORCE_PFET_OFF register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_DISABLE_FORCE_PFET_OFF, l_data64)); + //PIB.DISABLE_FORCE_PFET_OFF.DISABLE_FORCE_PFET_OFF_REG = l_attr_pfet + l_data64.insertFromRight<0, 30>(l_attr_pfet); + FAPI_TRY(fapi2::putScom(i_target_chip, PU_DISABLE_FORCE_PFET_OFF, l_data64)); + + FAPI_DBG("Drop EDRAM control gate and pfet_force_off"); + //Setting ROOT_CTRL2 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_data64)); + l_data64.clearBit<16>(); //PIB.ROOT_CTRL2.ROOT_CTRL2_16_FREE_USAGE = 0 + //PIB.ROOT_CTRL2.TPFSI_TP_PFET_FORCE_OFF_DC = 0 + l_data64.clearBit<PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_FORCE_OFF_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_data64)); + + //TOD error reg; + //config TOD error mask reg; + //clear TOD error reg; + + FAPI_DBG("Clear pervasive LFIR"); + //Setting LOCAL_FIR register value + //PERV.LOCAL_FIR = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_AND, 0)); + + FAPI_DBG("Configure pervasive LFIR" ); + //Setting LOCAL_FIR_ACTION0 register value + //PERV.LOCAL_FIR_ACTION0 = LFIR_ACTION0_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_ACTION0, + LFIR_ACTION0_VALUE)); + //Setting LOCAL_FIR_ACTION1 register value + //PERV.LOCAL_FIR_ACTION1 = LFIR_ACTION1_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_ACTION1, + LFIR_ACTION1_VALUE)); + //Setting LOCAL_FIR_MASK register value + //PERV.LOCAL_FIR_MASK = FIR_MASK_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_MASK, FIR_MASK_VALUE)); + + // Enables any checkstop if set, to propogate to FSP and get notified + // + FAPI_DBG("p9_sbe_tp_chiplet_init3: Unmask CFIR Mask"); + //Setting FIR_MASK register value + //PERV.FIR_MASK = FIR_MASK_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_FIR_MASK, FIR_MASK_VALUE)); + + FAPI_DBG("Setup Pervasive Hangcounter 0:Thermal, 1:OCC/SBE, 2:PBA hang, 3:Nest freq for TOD hang, 5:malefunction alert"); + //Setting HANG_PULSE_0_REG register value (Setting all fields) + //PERV.HANG_PULSE_0_REG.HANG_PULSE_REG_0 = 0b010000 + l_data64.insertFromRight<0, 6>(0b010000); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_0_REG.SUPPRESS_HANG_0 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_0_REG, l_data64)); + //Setting HANG_PULSE_1_REG register value (Setting all fields) + //PERV.HANG_PULSE_1_REG.HANG_PULSE_REG_1 = 0b000100 + l_data64.insertFromRight<0, 6>(0b000100); + l_data64.setBit<6>(); //PERV.HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_1_REG, l_data64)); + //Setting HANG_PULSE_2_REG register value (Setting all fields) + //PERV.HANG_PULSE_2_REG.HANG_PULSE_REG_2 = 0b010010 + l_data64.insertFromRight<0, 6>(0b010010); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_2_REG, l_data64)); + //Setting HANG_PULSE_3_REG register value (Setting all fields) + //PERV.HANG_PULSE_3_REG.HANG_PULSE_REG_3 = 0b000001 + l_data64.insertFromRight<0, 6>(0b000001); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_3_REG, l_data64)); + //Setting HANG_PULSE_5_REG register value (Setting all fields) + //PERV.HANG_PULSE_5_REG.HANG_PULSE_REG_5 = 0b000110 + l_data64.insertFromRight<0, 6>(0b000110); + l_data64.clearBit<6>(); //PERV.HANG_PULSE_5_REG.SUPPRESS_HANG_5 = 0b0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_5_REG, l_data64)); + + FAPI_DBG("CHECK FOR XSTOP"); + //Getting INTERRUPT_TYPE_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, l_data64)); + //l_read_reg = PIB.INTERRUPT_TYPE_REG.CHECKSTOP + l_read_reg = l_data64.getBit<PERV_INTERRUPT_TYPE_REG_CHECKSTOP>(); + + FAPI_ASSERT(l_read_reg == 0, + fapi2::XSTOP_ERR() + .set_READ_XSTOP(l_read_reg), + "XSTOP BIT GET SET"); + + FAPI_DBG("Start calibration"); + //Setting KVREF_AND_VMEAS_MODE_STATUS_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64)); + l_data64.setBit<0>(); //KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_START_CAL = 0b1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64)); + + FAPI_DBG("Check for calibration done"); + l_timeout = POLL_COUNT; + + //UNTIL KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_CAL_DONE == 1 + while (l_timeout != 0) + { + //Getting KVREF_AND_VMEAS_MODE_STATUS_REG register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64)); + //bool l_poll_data = KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_CAL_DONE + bool l_poll_data = l_data64.getBit<16>(); + + if (l_poll_data == 1) + { + break; + } + + fapi2::delay(HW_NS_DELAY, SIM_CYCLE_DELAY); + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::CALIBRATION_NOT_DONE(), + "Calibration not done, bit16 not set"); + + FAPI_INF("p9_sbe_tp_chiplet_init3: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief clock test +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read ; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_chiplet_init3_clock_test2: Entering ..."); + + FAPI_DBG("unfence 281D"); + //Setting ROOT_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + l_data64.clearBit<0>(); //PIB.ROOT_CTRL0.TPFSI_SBE_FENCE_VTLIO_DC_UNUSED = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64)); + + //Getting ROOT_CTRL3 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, + l_read)); //l_read = PIB.ROOT_CTRL3 + + l_read.setBit<27>(); + + FAPI_DBG("Set osc_ok latch active"); + //Setting ROOT_CTRL3 register value + //PIB.ROOT_CTRL3 = l_read + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read)); + + FAPI_DBG("Turn on oscilate pgood"); + //Setting ROOT_CTRL6 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL6_SCOM, l_data64)); + //PIB.ROOT_CTRL6.TPFSI_OSCSW1_PGOOD = 1 + l_data64.setBit<PERV_ROOT_CTRL6_SET_TPFSI_OSCSW1_PGOOD>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL6_SCOM, l_data64)); + + //Getting ROOT_CTRL3 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, + l_read)); //l_read = PIB.ROOT_CTRL3 + + l_read.clearBit<17>(); + + FAPI_DBG("turn off use_osc_1_0"); + //Setting ROOT_CTRL3 register value + //PIB.ROOT_CTRL3 = l_read + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read)); + + FAPI_DBG("Mask OSC err"); + //Setting OSCERR_MASK register value + //PIB.OSCERR_MASK = OSC_ERROR_MASK + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_OSCERR_MASK, OSC_ERROR_MASK)); + + FAPI_DBG("reset osc-error_reg"); + //Setting OSCERR_HOLD register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_OSCERR_HOLD, l_data64)); + l_data64.clearBit<4, 4>(); //PERV.OSCERR_HOLD.OSCERR_MEM = 0000 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_OSCERR_HOLD, l_data64)); + + FAPI_DBG("Resets FIR"); + //Setting LOCAL_FIR register value + l_data64.flush<1>(); + l_data64.clearBit<36>(); + l_data64.clearBit<37>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_AND, l_data64)); + +#ifndef SIM_ONLY_OSC_SWC_CHK + + FAPI_DBG("check for OSC ok"); + //Getting SNS1LTH register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SNS1LTH_SCOM, + l_read)); //l_read = PIB.SNS1LTH + + FAPI_ASSERT(l_read.getBit<21>() == 0 && l_read.getBit<28>() == 1, + fapi2::MF_OSC_NOT_TOGGLE() + .set_READ_SNS1LTH(l_read), + "MF oscillator not toggling"); + + FAPI_DBG("Osc error active"); + //Getting OSCERR_HOLD register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_OSCERR_HOLD, + l_read)); //l_read = PERV.OSCERR_HOLD + + FAPI_ASSERT(l_read.getBit<4>() == 0, + fapi2::MF_OSC_ERR() + .set_READ_OSCERR_HOLD(l_read), + "MF oscillator error active"); + +#endif + + FAPI_INF("p9_sbe_tp_chiplet_init3_clock_test2: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// @brief region fence setup +/// +/// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target +/// @return FAPI2_RC_SUCCESS if success, else error code. +static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet) +{ + // Local variable and constant definition + fapi2::buffer <uint32_t> l_attr_pg; + fapi2::buffer <uint16_t> l_attr_pg_data; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_chiplet_init3_region_fence_setup: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); + + l_attr_pg.invert(); + l_attr_pg.extractToRight<20, 11>(l_attr_pg_data); + + FAPI_DBG("Drop partial good fences"); + //Setting CPLT_CTRL1 register value + l_data64.flush<0>(); + l_data64.writeBit<PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE> + (l_attr_pg.getBit<19>()); //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>() + //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_attr_pg_data + l_data64.insertFromRight<4, 11>(l_attr_pg_data); + FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64)); + + FAPI_INF("p9_sbe_tp_chiplet_init3_region_fence_setup: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H new file mode 100644 index 00000000..c5367d97 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H @@ -0,0 +1,66 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_init3.H +/// +/// @brief TP Chiplet Start Clocks +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_INIT3_H_ +#define _P9_SBE_TP_CHIPLET_INIT3_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init3_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- Switches PRV Chiplet OOB mux +/// -- Reset PCB Master Interrupt Register +/// -- Drop Pervasive and OCC2PIB Fence in GP0 (bits 19 & 63) +/// --"Clock Start" command (all other clk domains) +/// -- Clear force_align in chiplet GP0 +/// -- Clear flushmode_inhibit in chiplet GP0 +/// -- Drop FSI fence 5 (checkstop, interrupt conditions) +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C new file mode 100644 index 00000000..f7960207 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C @@ -0,0 +1,61 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_reset.C +/// +/// @brief setup hangcounter 6 for TP chiplet +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_chiplet_reset.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_chiplet_reset: Entering ..."); + + FAPI_DBG("Initializing Hangcounter 6 for PRV Cplt"); + //Setting HANG_PULSE_6_REG register value + //PERV.HANG_PULSE_6_REG = HANG_PULSE_VALUE + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_6_REG, + HANG_PULSE_VALUE)); + + FAPI_DBG("p9_sbe_tp_chiplet_reset: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H new file mode 100644 index 00000000..441a7a6e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_chiplet_reset.H +/// +/// @brief setup hangcounter 6 for TP chiplet +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_CHIPLET_RESET_H_ +#define _P9_SBE_TP_CHIPLET_RESET_H_ + + +#include <fapi2.H> + + +enum P9_SBE_TP_CHIPLET_RESET_Constants +{ + HANG_PULSE_VALUE = 0x1400000000000000 +}; + +typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_reset_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Setup hang counter for PCB slaves/master +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C new file mode 100644 index 00000000..b8c22322 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_enable_ridi.C +/// +/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_enable_ridi.H" + +#include "p9_perv_scom_addresses.H" + + +fapi2::ReturnCode p9_sbe_tp_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_DBG("p9_sbe_tp_enable_ridi: Entering ..."); + + FAPI_INF("Enable Recievers, Drivers DI1 & DI2"); + //Setting ROOT_CTRL1 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + l_data64.setBit<19>(); //PIB.ROOT_CTRL1.TP_RI_DC_B = 1 + l_data64.setBit<20>(); //PIB.ROOT_CTRL1.TP_DI1_DC_B = 1 + l_data64.setBit<21>(); //PIB.ROOT_CTRL1.TP_DI2_DC_B = 1 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64)); + + FAPI_DBG("p9_sbe_tp_enable_ridi: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H new file mode 100644 index 00000000..c18e9a7f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H @@ -0,0 +1,59 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_enable_ridi.H +/// +/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_ENABLE_RIDI_H_ +#define _P9_SBE_TP_ENABLE_RIDI_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_enable_ridi_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Enable drivers/receivers for PRV chiplet +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_enable_ridi(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C new file mode 100644 index 00000000..42957145 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_initf.C +/// +/// @brief Scan initialize GPTR, TIME for PERV chiplet +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ + +#include "p9_sbe_tp_gptr_time_initf.H" + +fapi2::ReturnCode p9_sbe_tp_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_tp_gptr_time_initf: Entering ..."); + + FAPI_DBG("Scan perv_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_gptr), + "Error from putRing (perv_gptr)"); + FAPI_DBG("Scan perv_ana_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_ana_gptr), + "Error from putRing (perv_ana_gptr)"); + FAPI_DBG("Scan perv_pll_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_pll_gptr), + "Error from putRing (perv_pll_gptr)"); + FAPI_DBG("Scan occ_gptr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_gptr), + "Error from putRing (occ_gptr)"); + FAPI_DBG("Scan occ_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_time), + "Error from putRing (occ_time)"); + FAPI_DBG("Scan perv_time ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_time), + "Error from putRing (perv_time)"); + +fapi_try_exit: + FAPI_INF("p9_sbe_tp_gptr_time_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H new file mode 100644 index 00000000..2b99ade3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_initf.C +/// +/// @brief Scan initialize GPTR, TIME for PERV chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_TP_GPTR_TIME_INITF_H_ +#define _P9_SBE_TP_GPTR_TIME_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_gptr_time_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Load Scan Repair, Time and GPTR for TP Chiplet +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_gptr_time_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C new file mode 100644 index 00000000..2c351d74 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_repr_initf.C +/// +/// @brief proc sbe tp gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_gptr_time_repr_initf.H" +fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Entering ..."); + + FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H new file mode 100644 index 00000000..27ba211c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_gptr_time_repr_initf.H +/// +/// @brief proc sbe tp gptr time repr initf +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_ +#define _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_gptr_time_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Load Scan Repair, Time and GPTR for TP Chiplet +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C new file mode 100644 index 00000000..f1150966 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_initf.C +/// +/// @brief TP chiplet scaninits for the TP rings +//------------------------------------------------------------------------------ +// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_initf.H" +#include "p9_ring_id.h" + +fapi2::ReturnCode p9_sbe_tp_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_tp_initf: Entering ..."); + + FAPI_DBG("Scan perv_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_fure), + "Error from putRing (perv_fure)"); + + FAPI_DBG("Scan occ_fure ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_fure), + "Error from putRing (occ_fure)"); + + FAPI_DBG("Scan perv_ana_func ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_ana_func), + "Error from putRing (perv_ana_func)"); + +fapi_try_exit: + FAPI_INF("p9_sbe_tp_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H new file mode 100644 index 00000000..abf1f54c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_initf.H +/// +/// @brief TP chiplet scaninits for the TP rings +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_INITF_H_ +#define _P9_SBE_TP_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_initf_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief -- This doesn't include the gptr/time/repair rings, +/// -- since they are scanned in tp_chiplet_init2. +/// -- This doesn't include the net/pib/fuse rings, +/// -- since they are used by the SBE hardware itself. +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C new file mode 100644 index 00000000..7c933122 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C @@ -0,0 +1,52 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_ld_image.C +/// +/// @brief Proc SBE load Image +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_ld_image.H" +fapi2::ReturnCode p9_sbe_tp_ld_image(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_DBG("p9_sbe_tp_ld_image: Entering ..."); + + FAPI_DBG("p9_sbe_tp_ld_image: Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H new file mode 100644 index 00000000..e458d2be --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H @@ -0,0 +1,65 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_ld_image.H +/// +/// @brief Proc SBE load Image +// *! +// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com +// *! BACKUP NAME : Email: +//------------------------------------------------------------------------------ +// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP FW Owner : Brian Silver <bsilver@us.ibm.com> +// *HWP Team : Perv +// *HWP Level : 1 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_LD_IMAGE_H_ +#define _P9_SBE_TP_LD_IMAGE_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_ld_image_FP_t)(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief This procedure copies the .pibmem0 section of image from SEEPROM to the PIBMEM. +/// The pibmem0 section contains the PORE branch table (error handlers) used for the majority of the SEEPROM IPL as well as +/// performance sensitive routines such as the decompression-scan routine and the LCO loader. +/// Once the image is loaded then the error handlers are switched to +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_ld_image(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C new file mode 100644 index 00000000..53aed3bb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_repr_initf.C +/// +/// @brief Scan initialize REPR for PERV chiplet +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ + +#include "p9_sbe_tp_repr_initf.H" + +fapi2::ReturnCode p9_sbe_tp_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + FAPI_INF("p9_sbe_tp_repr_initf: Entering ..."); + + FAPI_DBG("Scan perv_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, perv_repr), + "Error from putRing (perv_repr)"); + + FAPI_DBG("Scan occ_repr ring"); + FAPI_TRY(fapi2::putRing(i_target_chip, occ_repr), + "Error from putRing (occ_repr)"); + +fapi_try_exit: + FAPI_INF("p9_sbe_tp_repr_initf: Exiting ..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H new file mode 100644 index 00000000..134fc853 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_repr_initf.C +/// +/// @brief Scan initialize REPR for PERV chiplet +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : Sunil Kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + +#ifndef _P9_SBE_TP_REPR_INITF_H_ +#define _P9_SBE_TP_REPR_INITF_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_repr_initf_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief --Scan Repair for TP Chiplet +/// +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. + +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_repr_initf(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C new file mode 100644 index 00000000..828c855c --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C @@ -0,0 +1,161 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_switch_gears.C +/// +/// @brief Switch from refclock to PLL AND adjust I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +//## auto_generated +#include "p9_sbe_tp_switch_gears.H" +//## auto_generated +#include "p9_const_common.H" + +#include <p9_misc_scom_addresses.H> +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_sbe_gear_switcher.H> + + +enum P9_SBE_TP_SWITCH_GEARS_Private_Constants +{ + BACKUP_SEEPROM_MAGIC_NUM_ADDRESS = 0xD8A9029000000000, // Magic number value from Backup SEEPROM + BUS_STATUS_BUSY_POLL_COUNT = 256, + MAGIC_NUMBER = 0x584950205345504D, + NORMAL_SEEPROM_MAGIC_NUM_ADDRESS = 0xD8A9009000000000 // Magic number value from SEEPROM +}; + +fapi2::ReturnCode p9_sbe_tp_switch_gears(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_switch_gears: Entering ..."); + +#ifdef __PPE__ + + FAPI_DBG("switch from refclock to PLL speed"); + //Setting PERV_CTRL0 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0 + l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64)); + + FAPI_TRY(p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting( + i_target_chip)); + + FAPI_TRY(p9_sbe_gear_switcher_i2c_stop_sequence(i_target_chip)); + + FAPI_DBG("Checking Magic number"); + FAPI_TRY(p9_sbe_tp_switch_gears_check_magicnumber(i_target_chip)); +fapi_try_exit: +#endif + + FAPI_INF("p9_sbe_tp_switch_gears: Exiting ..."); + + return fapi2::current_err; + +} + +/// @brief check for magic number +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) +{ + fapi2::buffer<uint64_t> l_read_reg; + fapi2::buffer<uint8_t> l_read_attr = 0; + int l_timeout = 0; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("p9_sbe_tp_switch_gears_check_magicnumber: Entering ..."); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BACKUP_SEEPROM_SELECT, i_target_chip, + l_read_attr)); + + if ( l_read_attr.getBit<7>() == 1 ) + { + FAPI_DBG("Read magic number from Backup SEEPROM"); + //Setting CONTROL_REGISTER_B register value + //PIB.CONTROL_REGISTER_B = BACKUP_SEEPROM_MAGIC_NUM_ADDRESS + FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, + BACKUP_SEEPROM_MAGIC_NUM_ADDRESS)); + } + else + { + FAPI_DBG("Read magic number from SEEPROM"); + //Setting CONTROL_REGISTER_B register value + //PIB.CONTROL_REGISTER_B = NORMAL_SEEPROM_MAGIC_NUM_ADDRESS + FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, + NORMAL_SEEPROM_MAGIC_NUM_ADDRESS)); + } + + FAPI_DBG("Poll for stop command completion"); + l_timeout = BUS_STATUS_BUSY_POLL_COUNT; + + //UNTIL STATUS_REGISTER_B.BUS_STATUS_BUSY_0 == 0 + while (l_timeout != 0) + { + //Getting STATUS_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64)); + //bool l_poll_data = PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0 + bool l_poll_data = l_data64.getBit<44>(); + + if (l_poll_data == 0) + { + break; + } + + --l_timeout; + } + + FAPI_DBG("Loop Count :%d", l_timeout); + + FAPI_ASSERT(l_timeout > 0, + fapi2::BUS_STATUS_BUSY0(), + "ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0"); + + FAPI_DBG("Reading the value of DATA0TO7_REGISTER_B"); + //Getting DATA0TO7_REGISTER_B register value + FAPI_TRY(fapi2::getScom(i_target_chip, PU_DATA0TO7_REGISTER_B, + l_read_reg)); //l_read_reg = PIB.DATA0TO7_REGISTER_B + + FAPI_ASSERT(l_read_reg == MAGIC_NUMBER, + fapi2::MAGIC_NUMBER_NOT_VALID(), + "ERROR: Magic number not matching"); + + FAPI_INF("p9_sbe_tp_switch_gears_check_magicnumber: Exiting ..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H new file mode 100644 index 00000000..a53d025f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file p9_sbe_tp_switch_gears.H +/// +/// @brief Switch from refclock to PLL AND adjust I2C +//------------------------------------------------------------------------------ +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> +// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> +// *HWP FW Owner : sunil kumar <skumarj8@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE +//------------------------------------------------------------------------------ + + +#ifndef _P9_SBE_TP_SWITCH_GEARS_H_ +#define _P9_SBE_TP_SWITCH_GEARS_H_ + + +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_sbe_tp_switch_gears_FP_t)( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// @brief Switch from refclcok to PLL speed (leave bypass) +/// Read new I2C Bit Rate Divisor setting from mailbox +/// Adjust I2C bit rate divisor setting in I2CM B mode reg +/// Send a stop sequence on I2C +/// Poll for stop command completion +/// Check for magic number +/// +/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target +/// @return FAPI2_RC_SUCCESS if success, else error code. +extern "C" +{ + fapi2::ReturnCode p9_sbe_tp_switch_gears(const + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); +} + +fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); + +#endif diff --git a/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk b/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk new file mode 100644 index 00000000..d4b77bb7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk @@ -0,0 +1,76 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/perv/pervfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file pervfiles.mk +# +# @brief mk for including perv object files +# +########################################################################## +# Object Files +########################################################################## + +PERV-CPP-SOURCES =p9_sbe_arrayinit.C +PERV-CPP-SOURCES +=p9_sbe_attr_setup.C +PERV-CPP-SOURCES +=p9_sbe_check_master.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_init.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_initf.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_setup.C +PERV-CPP-SOURCES +=p9_sbe_chiplet_reset.C +PERV-CPP-SOURCES +=p9_sbe_enable_seeprom.C +PERV-CPP-SOURCES +=p9_sbe_gptr_time_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_lpc_init.C +PERV-CPP-SOURCES +=p9_sbe_nest_enable_ridi.C +PERV-CPP-SOURCES +=p9_sbe_nest_initf.C +PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C +PERV-CPP-SOURCES +=p9_sbe_npll_initf.C +PERV-CPP-SOURCES +=p9_sbe_npll_setup.C +PERV-CPP-SOURCES +=p9_sbe_select_ex.C +PERV-CPP-SOURCES +=p9_sbe_startclock_chiplets.C +PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C +PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_reset.C +PERV-CPP-SOURCES +=p9_sbe_tp_enable_ridi.C +PERV-CPP-SOURCES +=p9_sbe_tp_initf.C +PERV-CPP-SOURCES +=p9_sbe_tp_ld_image.C +PERV-CPP-SOURCES +=p9_sbe_setup_evid.C +PERV-CPP-SOURCES +=p9_perv_sbe_cmn.C +PERV-CPP-SOURCES +=p9_sbe_common.C +PERV-CPP-SOURCES +=p9_sbe_check_master_stop15.C +PERV-CPP-SOURCES +=p9_hcd_cache_dcc_skewadjust_setup.C +PERV-CPP-SOURCES +=p9_sbe_setup_boot_freq.C +PERV-CPP-SOURCES +=p9_sbe_io_initf.C +PERV-CPP-SOURCES +=p9_sbe_gptr_time_initf.C +PERV-CPP-SOURCES +=p9_sbe_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_tp_gptr_time_initf.C +PERV-CPP-SOURCES +=p9_sbe_tp_repr_initf.C +PERV-CPP-SOURCES +=p9_sbe_clock_test2.C + +PERV-C-SOURCES = +PERV-S-SOURCES = + +PERV_OBJECTS += $(PERV-CPP-SOURCES:.C=.o) +PERV_OBJECTS += $(PERV-C-SOURCES:.c=.o) +PERV_OBJECTS += $(PERV-S-SOURCES:.S=.o) diff --git a/src/import/chips/p9/procedures/hwp/pm/Makefile b/src/import/chips/p9/procedures/hwp/pm/Makefile new file mode 100644 index 00000000..65f3170a --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/pm/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the pm hardware procedure code. See the +# "pmfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/pm +export SUB_OBJDIR = /pm + +include img_defs.mk +include pmfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(PM_OBJECTS)) + +libpm.a: pm + $(AR) crs $(OBJDIR)/libpm.a $(OBJDIR)/*.o + +.PHONY: clean pm +pm: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C new file mode 100644 index 00000000..fce9dea9 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C @@ -0,0 +1,179 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_block_wakeup_intr.C +/// @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PCBS-PM associated +/// with an EX chiplet +/// +// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> +// *HWP FW Owner: Prem Jha <premjha1@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: FSP:HS +/// +/// @verbatim +/// High-level procedure flow: +/// +/// With set/reset enum parameter, either set or clear PMGP0(53) +/// +/// Procedure Prereq: +/// - System clocks are running +/// @endverbatim +/// +//------------------------------------------------------------------------------ + + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include <p9_block_wakeup_intr.H> +#include <p9_hcd_common.H> + + + +// This must stay in sync with enum OP_TYPE enum in header file +const char* OP_TYPE_STRING[] = +{ + "SET", + "CLEAR" +}; + + +// ---------------------------------------------------------------------- +// Procedure Function +// ---------------------------------------------------------------------- + +/// @brief @brief Set/reset the BLOCK_INTR_INPUTS bit in the Core PPM +/// associated with an EX chiplet + +fapi2::ReturnCode +p9_block_wakeup_intr( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_core_target, + const p9pmblockwkup::OP_TYPE i_operation) +{ + FAPI_INF("> p9_block_wakeup_intr..."); + + fapi2::buffer<uint64_t> l_data64 = 0; + + // Get the core number + uint8_t l_attr_chip_unit_pos = 0; + + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + i_core_target.getParent<fapi2::TARGET_TYPE_PERV>(); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + l_perv, + l_attr_chip_unit_pos), + "fapiGetAttribute of ATTR_CHIP_UNIT_POS failed"); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET; + + // Read for trace + { + fapi2::buffer<uint64_t> l_cpmmr = 0; + fapi2::buffer<uint64_t> l_gpmmr = 0; + + // Read the CPMMR and GPMMR as a trace + FAPI_TRY(fapi2::getScom(i_core_target, + C_CPPM_CPMMR, + l_cpmmr), + "getScom of CPMMR failed"); + + FAPI_TRY(fapi2::getScom(i_core_target, + C_PPM_GPMMR, + l_gpmmr), + "getScom of GPMMR failed"); + + FAPI_DBG("Debug: before setting PPM_WRITE_OVERRIDE on Core %d - CPPMR: 0x%016llX GPMMR: 0x%016llX", + l_attr_chip_unit_pos, l_cpmmr, l_gpmmr); + } + + // Ensure access to the GPMMR is in place using CPMMR Write Access + // Override. This will not affect the CME functionality as only the + // Block Wake-up bit is being manipulated -- a bit that the CME does + // not control but does react upon. + + FAPI_INF("Set the CPPM PPM Write Override"); + l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_OVERRIDE>(); + FAPI_TRY(fapi2::putScom(i_core_target, + C_CPPM_CPMMR_OR, + l_data64), + "putScom of CPMMR to set PMM Write Override failed"); + + l_data64.flush<0>().setBit<BLOCK_REG_WKUP_EVENTS>(); + + switch (i_operation) + { + case p9pmblockwkup::SET: + + // @todo RTC 144905 Add Special Wakeup setting here when available + + FAPI_INF("Setting GPMMR[Block Interrupt Sources] on Core %d", + l_attr_chip_unit_pos); + + FAPI_TRY(fapi2::putScom(i_core_target, + C_PPM_GPMMR_OR, + l_data64), + "Setting GPMMR failed"); + + // @todo RTC 144905 Add Special Wakeup clearing here when available + + break; + + case p9pmblockwkup::SET_NOSPWUP: + FAPI_INF("Setting GPMMR[Block Interrupt Sources] without Special Wake-up on Core %d", + l_attr_chip_unit_pos); + + FAPI_TRY(fapi2::putScom(i_core_target, + C_PPM_GPMMR_OR, + l_data64), + "Setting GPMMR failed"); + break; + + case p9pmblockwkup::CLEAR: + FAPI_INF("Clearing GPMMR[Block Interrupt Sources] on Core %d", + l_attr_chip_unit_pos); + + FAPI_TRY(fapi2::putScom(i_core_target, + C_PPM_GPMMR_CLEAR, + l_data64), + "Clearing GPMMR failed"); + break; + + default: + ; + } + + FAPI_INF("Clear the CPPM PPM Write Override"); + l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_OVERRIDE>(); + FAPI_TRY(fapi2::putScom(i_core_target, + C_CPPM_CPMMR_CLEAR, + l_data64), + "putScom of CPMMR to clear PMM Write Override failed"); + +fapi_try_exit: + FAPI_INF("< p9_block_wakeup_intr..."); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H new file mode 100644 index 00000000..f4aaaf44 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H @@ -0,0 +1,106 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file p9_block_wakeup_intr.H +/// @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PPM +/// associated with an EX chiplet +/// +// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner: Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 1 +// *HWP Consumed by: FSP:HS +/// +///----------------------------------------------------------------------------- + +#ifndef _P9_BLKWKUP_H_ +#define _P9_BLKWKUP_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi2.H> +#include <p9_quad_scom_addresses.H> +#include <p9_quad_scom_addresses_fld.H> + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +namespace p9pmblockwkup +{ + +enum OP_TYPE +{ + SET = 0, + SET_NOSPWUP = 1, + CLEAR = 2 +}; + +// Used by checking infrasture checking code +static const uint32_t END_OP = CLEAR; + +} // namespace p9pmblockwkup + + +// +// CPMMR Bit definitions +const uint32_t BLOCK_REG_WKUP_EVENTS = 6; + +// GPMMR Address mappings (for clarity) +static const uint64_t C_PPM_GPMMR = C_PPM_GPMMR_SCOM; +static const uint64_t C_PPM_GPMMR_CLEAR = C_PPM_GPMMR_SCOM1; +static const uint64_t C_PPM_GPMMR_OR = C_PPM_GPMMR_SCOM2; + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_block_wakeup_intr_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&, + const p9pmblockwkup::OP_TYPE); + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ + +/// @brief @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PPM +/// associated with an EX chiplet +/// +/// @param[in] i_core_target Core target +/// @param[in] i_operation SET, CLEAR +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. + + fapi2::ReturnCode + p9_block_wakeup_intr( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_core_target, + const p9pmblockwkup::OP_TYPE i_operation); + +} // extern "C" + +#endif // _P9_BLKWKUP_H_ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm.H new file mode 100644 index 00000000..d14c021a --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm.H @@ -0,0 +1,102 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_pm.H +/// @brief Common header for Power Manangement procedures +/// + +// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HS + +#ifndef _P9_PM_H_ +#define _P9_PM_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Macro Defintions +//------------------------------------------------------------------------------ + +// Create a multi-bit mask of @a n bits starting at bit @a b +#ifndef BITS + #define BITS(b, n) ((0xffffffffffffffffull << (64 - (n))) >> (b)) +#endif + +// Create a single bit mask at bit @a b +#ifndef BIT + #define BIT(b) BITS((b), 1) +#endif + +extern const char* p9_PM_FLOW_MODE_NAME[]; + +#define PM_FLOW_MODE_NAME \ + { \ + "PM_RESET", \ + "PM_INIT", \ + "PM_SETUP", \ + "PM_SETUP_PIB", \ + "PM_SETUP_ALL", \ + "PM_RESET_SOFT", \ + "PM_INIT_SOFT", \ + "PM_INIT_SPECIAL" \ + } + +#define PM_MODE_NAME_VAR p9_PM_FLOW_MODE_NAME[] = PM_FLOW_MODE_NAME + +#define PM_MODE_NAME(_mi_mode)( \ + p9_PM_FLOW_MODE_NAME[_mi_mode-1] \ + ) + + + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ +namespace p9pm +{ + +enum PM_FLOW_MODE +{ + PM_RESET = 0x1, + PM_INIT = 0x2, + PM_SETUP = 0x3, + PM_SETUP_PIB = 0x4, + PM_SETUP_ALL = 0x5, + PM_RESET_SOFT = 0x6, + PM_INIT_SOFT = 0x7, + PM_INIT_SPECIAL = 0x8, +}; + +} // end of namespace p9pm + + +#endif // _P9_PM_H_ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C new file mode 100644 index 00000000..c88407cd --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C @@ -0,0 +1,237 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pm_ocb_indir_access.C +/// @brief Performs the data transfer to/from an OCB indirect channel + +// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> +// *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : FSP:HS + +/// +/// High-level procedure flow: +/// @verbatim +/// 1) Check if the channel for access is valid. +/// 2) For the PUT operation, the data from the buffer will be written +/// into the OCB Data register in blocks of 64bits; +/// from where eventually the data will be written to SRAM. +/// 3) For GET operation, the data read from the SRAM will be retrieved from +/// the DATA register and written into the buffer in blocks of 64bits. +/// @endverbatim +/// + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <p9_pm_ocb_indir_access.H> + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + +enum +{ + OCB_FULL_POLL_MAX = 4, + OCB_FULL_POLL_DELAY_HDW = 0, + OCB_FULL_POLL_DELAY_SIM = 0 +}; + +fapi2::ReturnCode p9_pm_ocb_indir_access( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_ACCESS_OP i_ocb_op, + const uint32_t i_ocb_req_length, + const bool i_oci_address_valid, + const uint32_t i_oci_address, + uint32_t& o_ocb_act_length, + uint64_t* io_ocb_buffer) +{ + FAPI_IMP("Enter p9_pm_ocb_indir_access..."); + FAPI_DBG("Channel : %d, Operation : %d, No.of 8B Blocks of Data: %d", + i_ocb_chan, i_ocb_op, i_ocb_req_length); + + uint64_t l_OCBAR_address = 0; + uint64_t l_OCBDR_address = 0; + uint64_t l_OCBCSR_address = 0; + uint64_t l_OCBSHCS_address = 0; + o_ocb_act_length = 0; + + FAPI_DBG("Checking channel validity"); + + switch ( i_ocb_chan ) + { + case p9ocb::OCB_CHAN0: + l_OCBAR_address = PU_OCB_PIB_OCBAR0; + l_OCBDR_address = PU_OCB_PIB_OCBDR0; + l_OCBCSR_address = PU_OCB_PIB_OCBCSR0_RO; + l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS0_SCOM; + break; + + case p9ocb::OCB_CHAN1: + l_OCBAR_address = PU_OCB_PIB_OCBAR1; + l_OCBDR_address = PU_OCB_PIB_OCBDR1; + l_OCBCSR_address = PU_OCB_PIB_OCBCSR1_RO; + l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS1_SCOM; + break; + + case p9ocb::OCB_CHAN2: + l_OCBAR_address = PU_OCB_PIB_OCBAR2; + l_OCBDR_address = PU_OCB_PIB_OCBDR2; + l_OCBCSR_address = PU_OCB_PIB_OCBCSR2_RO; + l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS2_SCOM; + break; + + case p9ocb::OCB_CHAN3: + l_OCBAR_address = PU_OCB_PIB_OCBAR3; + l_OCBDR_address = PU_OCB_PIB_OCBDR3; + l_OCBCSR_address = PU_OCB_PIB_OCBCSR3_RO; + l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS3_SCOM; + break; + } + + // Verify if a valid valid address provided + // If the address is provided + // Use it for the Get / Put operation + // The following cases apply: + // Circular : OCBAR is irrelevant; write it anyway + // Linear : OCBAR will set the accessed location + // Linear Stream : OCBAR will establish the address from which + // auto-increment will commence after the first access + // Else + // Circular : OCBAR is irrelevant + // Linear : OCBAR will continue to access the same location + // Linear Stream : OCBAR will auto-increment + if ( i_oci_address_valid ) + { + FAPI_DBG(" OCI Address : 0x%08X", i_oci_address); + fapi2::buffer<uint64_t> l_data64; + l_data64.insert<0, 32>(i_oci_address); + + FAPI_TRY(fapi2::putScom(i_target, l_OCBAR_address, l_data64)); + } + + // PUT Operation + if ( i_ocb_op == p9ocb::OCB_PUT ) + { + FAPI_INF("OCB access for data write operation"); + FAPI_ASSERT(io_ocb_buffer != NULL, + fapi2::PM_OCB_PUT_NO_DATA_ERROR(), + "No data provided for PUT operation"); + + fapi2::buffer<uint64_t> l_data64; + FAPI_TRY(fapi2::getScom(i_target, l_OCBCSR_address, l_data64)); + + // The following check for circular mode is an additional check + // performed to ensure a valid data access. + if (l_data64.getBit<4>() && l_data64.getBit<5>()) + { + FAPI_DBG("Circular mode detected."); + // Check if push queue is enabled. If not, let the store occur + // anyway to let the PIB error response return occur. (that is + // what will happen if this checking code were not here) + FAPI_TRY(fapi2::getScom(i_target, l_OCBSHCS_address, l_data64)); + + if (l_data64.getBit<31>()) + { + FAPI_DBG("Poll for a non-full condition to a push queue to " + "avoid data corruption problem"); + bool l_push_ok_flag = false; + uint8_t l_counter = 0; + + do + { + // If the OCB_OCI_OCBSHCS0_PUSH_FULL bit (bit 0) is clear, + // proceed. Otherwise, poll + if (!l_data64.getBit<0>()) + { + l_push_ok_flag = true; + FAPI_DBG("Push queue not full. Proceeding"); + break; + } + + // Delay, before next polling. + fapi2::delay(OCB_FULL_POLL_DELAY_HDW, + OCB_FULL_POLL_DELAY_SIM); + + FAPI_TRY(fapi2::getScom(i_target, + l_OCBSHCS_address, + l_data64)); + l_counter++; + } + while (l_counter < OCB_FULL_POLL_MAX); + + FAPI_ASSERT((true == l_push_ok_flag), + fapi2::PM_OCB_PUT_DATA_POLL_NOT_FULL_ERROR(). + set_PUSHQ_STATE(l_data64), + "Polling timeout waiting on push non-full"); + } + } + + // Walk the input buffer (io_ocb_buffer) 8B (64bits) at a time to write + // the channel data register + for(uint32_t l_index = 0; l_index < i_ocb_req_length; l_index++) + { + l_data64.insertFromRight(io_ocb_buffer[l_index], 0, 64); + FAPI_TRY(fapi2::putScom(i_target, l_OCBDR_address, l_data64), + "ERROR:Failed to complete write to channel data register"); + o_ocb_act_length++; + FAPI_DBG("data(64 bits): 0x%016lX written to channel data register", + io_ocb_buffer[l_index]); + } + + FAPI_DBG("%d blocks(64bits each) of data put", o_ocb_act_length); + } + // GET Operation + else if( i_ocb_op == p9ocb::OCB_GET ) + { + FAPI_INF("OCB access for data read operation"); + + fapi2::buffer<uint64_t> l_data64; + uint64_t l_data = 0; + + for (uint32_t l_loopCount = 0; l_loopCount < i_ocb_req_length; + l_loopCount++) + { + FAPI_TRY(fapi2::getScom(i_target, l_OCBDR_address, l_data64), + "ERROR: Failed to read data from channel %d", i_ocb_chan); + l_data64.extract(l_data, 0, 64); + io_ocb_buffer[l_loopCount] = l_data; + o_ocb_act_length++; + FAPI_DBG("data(64 bits): 0x%016lX read from channel data register", + io_ocb_buffer[l_loopCount]); + } + + FAPI_DBG("%d blocks(64bits each) of data retrieved", + o_ocb_act_length); + } + + FAPI_IMP("Exit p9_pm_ocb_indir_access..."); + +fapi_try_exit: + return fapi2::current_err; + +} diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H new file mode 100644 index 00000000..e5b548fb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H @@ -0,0 +1,114 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_pm_ocb_indir_access.H +/// @brief Access procedure to the OCC OCB indirect channels +/// + +// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> +// *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : FSP:HS + +#ifndef _P9_PM_OCB_INDIR_ACCESS_H_ +#define _P9_PM_OCB_INDIR_ACCESS_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <fapi2.H> +#include <p9_pm.H> +#include <p9_pm_ocb_init.H> + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ +namespace p9ocb +{ +enum PM_OCB_ACCESS_OP +{ + OCB_GET = 0x1, + OCB_PUT = 0x2 +}; +} + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_pm_ocb_indir_access_FP_t) +(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const p9ocb::PM_OCB_CHAN_NUM, + const p9ocb::PM_OCB_ACCESS_OP, + const uint32_t, + const bool, + const uint32_t, + uint32_t&, + uint64_t*); + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ + +extern "C" +{ + +/// @brief Provides for the abstract access to an OCB indirect channel that has +/// been configured previously via p9_pm_ocb_indir_setup_[linear/circular] +/// procedures +/// +/// @param[in] &i_target Chip target +/// @param[in] i_ocb_chan OCB channel number (0, 1, 2, 3) +/// @param[in] i_ocb_op Operation (Get, Put) +/// @param[in] i_ocb_req_length Requested length in the number of 8B +/// elements to be accessed (unit origin) +/// Number of bytes = (i_ocb_req_length) * +/// 8B +/// @param[in] i_oci_address_valid Indicator that oci_address is to be used +/// @param[in] i_oci_address OCI Address to be used for the operation +/// @param[out] &o_ocb_act_length Address containing the actual length +/// in the number of 8B elements to be +/// accessed (zero origin) +/// Number of bytes = (o_ocb_act_length+1) * +/// 8B +/// @param[in/out] io_ocb_buffer Pointer to a container of type uint64_t +/// to store the data to be written into or +/// obtained from OCC SRAM +/// +/// @return FAPI2_RC_SUCCESS on success, else error. + + fapi2::ReturnCode p9_pm_ocb_indir_access( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_ACCESS_OP i_ocb_op, + const uint32_t i_ocb_req_length, + const bool i_oci_address_valid, + const uint32_t i_oci_address, + uint32_t& o_ocb_act_length, + uint64_t* io_ocb_buffer); + +} // extern "C" + +#endif // _P9_PM_OCB_INDIR_ACCESS_H_ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C new file mode 100644 index 00000000..ef7f0138 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C @@ -0,0 +1,90 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pm_ocb_indir_setup_circular.C +/// @brief Configure OCB Channels for Circular Push or Pull Mode +/// +// *HWP HWP Owner : Amit Kumar <akumar@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HS + +/// High-level procedure flow: +/// @verbatim +/// Setup specified channel to push or pull circular mode by calling +/// p9_pm_ocb_init +/// +/// Procedure Prereq: +/// - System clocks are running +/// @endverbatim +/// + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include <p9_pm_ocb_indir_setup_circular.H> + +fapi2::ReturnCode p9_pm_ocb_indir_setup_circular( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_q_len, + const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_flow, + const p9ocb::PM_OCB_ITPTYPE i_ocb_itp) +{ + FAPI_IMP("p9_pm_ocb_indir_setup_circular Enter"); + FAPI_DBG("Channel: %d; Mode: %d; OCB BAR: 0x%08X; Queue length: %d;", + i_ocb_chan, i_ocb_type, i_ocb_bar, i_ocb_q_len); + FAPI_DBG("Flow Notification Mode: %d; Interrupt Behaviour: %d", i_ocb_flow, + i_ocb_itp); + + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + FAPI_EXEC_HWP(l_rc, + p9_pm_ocb_init, + i_target, + p9pm::PM_SETUP_ALL, + i_ocb_chan, + i_ocb_type, + i_ocb_bar, + i_ocb_q_len, + i_ocb_flow, + i_ocb_itp); + + if (l_rc == fapi2::FAPI2_RC_SUCCESS) + { + FAPI_INF("Circular setup of channel %d successful.", i_ocb_chan); + } + else + { + FAPI_ERR("ERROR: Failed to setup channel %d to circular mode.", + i_ocb_chan); + } + + FAPI_IMP("p9_pm_ocb_indir_setup_circular Exit"); + return l_rc; +} diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H new file mode 100644 index 00000000..a366bbd8 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pm_ocb_indir_setup_circular.H +/// @brief Configure OCB Channels for Circular Push or Pull Mode +// *HWP HWP Owner : Amit Kumar <akumar@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HS + +#ifndef _P9_PM_OCB_INDIR_SETUP_CIRCULAR_H_ +#define _P9_PM_OCB_INDIR_SETUP_CIRCULAR_H_ + +#include <fapi2.H> +#include <p9_pm_ocb_init.H> + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_pm_ocb_indir_setup_circular_FP_t) +(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const p9ocb::PM_OCB_CHAN_NUM, + const p9ocb::PM_OCB_CHAN_TYPE, + const uint32_t, + const uint8_t, + const p9ocb::PM_OCB_CHAN_OUFLOW, + const p9ocb::PM_OCB_ITPTYPE); + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// @brief Configure OCB Channels for Circular Push or Pull Mode +/// @param[in] i_target Chip Target +/// @param[in] i_ocb_chan Select channel 0-3 to set up +/// @param[in] i_ocb_type Circular push; circular pull +/// @return FAPI2_RC_SUCCESS on success, error otherwise + + fapi2::ReturnCode p9_pm_ocb_indir_setup_circular( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_q_len, + const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_flow, + const p9ocb::PM_OCB_ITPTYPE i_ocb_itp); + +} // extern "C" + +#endif diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C new file mode 100644 index 00000000..292659cb --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C @@ -0,0 +1,91 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p8_ocb_indir_setup_linear.C +/// @brief Configure OCB Channel for Linear Streaming or Non-streaming mode + +// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HS + +/// High-level procedure flow: +/// @verbatim +/// Setup specified channel to linear streaming or non-streaming mode by +/// calling proc proc_ocb_init +/// +/// Procedure Prereq: +/// - System clocks are running +/// @endverbatim +/// +//------------------------------------------------------------------------------ + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + +#include <p9_pm.H> +#include <p9_pm_ocb_indir_setup_linear.H> + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- +fapi2::ReturnCode p9_pm_ocb_indir_setup_linear( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar) +{ + FAPI_IMP("p9_pm_ocb_indir_setup_linear Enter"); + FAPI_DBG("For channel %d as type %d, OCB Bar 0x%x", + i_ocb_chan, i_ocb_type, i_ocb_bar); + + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + FAPI_EXEC_HWP(l_rc, + p9_pm_ocb_init, + i_target, + p9pm::PM_SETUP_PIB, + i_ocb_chan, + i_ocb_type, + i_ocb_bar, + 0, // ocb_q_len + p9ocb::OCB_Q_OUFLOW_NULL, + p9ocb::OCB_Q_ITPTYPE_NULL); + + if (l_rc == fapi2::FAPI2_RC_SUCCESS) + { + FAPI_INF("Linear setup of channel %d successful.", i_ocb_chan); + } + else + { + FAPI_ERR("ERROR: Failed to setup channel %d to linear mode.", + i_ocb_chan); + } + + FAPI_IMP("p9_pm_ocb_indir_setup_linear Exit"); + return l_rc; +} + diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H new file mode 100644 index 00000000..27adcc48 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H @@ -0,0 +1,68 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9_pm_ocb_indir_setup_linear.C +/// @brief Configure OCB Channel for Linear Streaming or Non-streaming mode + +// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 2 +// *HWP Consumed by : HS + +#ifndef _P9_PM_OCB_INDIR_SETUP_LINEAR_H_ +#define _P9_PM_OCB_INDIR_SETUP_LINEAR_H_ + +#include <fapi2.H> +#include <p9_pm_ocb_init.H> + +typedef fapi2::ReturnCode (*p9_pm_ocb_indir_setup_linear_FP_t) +(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const p9ocb::PM_OCB_CHAN_NUM, + const p9ocb::PM_OCB_CHAN_TYPE, + const uint32_t); + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// @brief Configure OCB Channel for Linear Streaming or Non-streaming mode +/// @param[in] i_target Chip Target +/// @param[in] i_ocb_chan select channel 0-3 to set up (see p8_ocb_init.H) +/// @param[in] i_ocb_type linear streaming or non-streaming (see p8_ocb_init.H) +/// @param[in] i_ocb_bar 32-bit channel base address (29 bits + "000") +/// @return FAPI2_RC_SUCCESS on success, else error. + + fapi2::ReturnCode p9_pm_ocb_indir_setup_linear( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar); + +} // extern "C" + +#endif diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C new file mode 100644 index 00000000..2ac813d6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C @@ -0,0 +1,674 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_pm_ocb_init.C +/// @brief Setup and configure OCB channels +/// +// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> +// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: FSP:HS + +/// Add support for linear window mode +/// +/// High-level procedure flow: +/// +/// - if mode = PM_INIT +/// - placeholder - currently do nothing +/// - if mode = PM_RESET +/// - reset each register in each OCB channel to its scan0-flush state +/// - if mode = PM_SETUP_PIB or PM_SETUP_ALL +/// - process parameters passed to procedure +/// - Set up channel control/status register based on passed parameters +/// (OCBCSRn) +/// - Set Base Address Register +/// - linear streaming & non-streaming => OCBARn +/// - push queue => OCBSHBRn (only if PM_SETUP_ALL) +/// - pull queue => OCBSLBRn (only if PM_SETUP_ALL) +/// - Set up queue control and status register (only if PM_SETUP_ALL) +/// - push queue => OCBSHCSn +/// - pull queue => OCBSLCSn +/// +/// Procedure Prerequisite: +/// - System clocks are running +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_pm_ocb_init.H> + +//------------------------------------------------------------------------------ +// CONSTANTS +//------------------------------------------------------------------------------ +enum PM_OCB_CONST +{ + MAX_OCB_QUE_LEN = 31, // Max length of PULL/PUSH queue + INTERRUPT_SRC_MASK_REG = 0xFFFFFFFF, // Mask for interrupt source register + MAX_OCB_CHANNELS = 3 // Max no. of OCB channels +}; + +// channel register arrrays +const uint64_t OCBARn[4] = {PU_OCB_PIB_OCBAR0, + PU_OCB_PIB_OCBAR1, + PU_OCB_PIB_OCBAR2, + PU_OCB_PIB_OCBAR3 + }; + +const uint64_t OCBCSRn_CLEAR[4] = {PU_OCB_PIB_OCBCSR0_CLEAR, + PU_OCB_PIB_OCBCSR1_CLEAR, + PU_OCB_PIB_OCBCSR2_CLEAR, + PU_OCB_PIB_OCBCSR3_CLEAR + }; + +const uint64_t OCBCSRn_OR[4] = {PU_OCB_PIB_OCBCSR0_OR, + PU_OCB_PIB_OCBCSR1_OR, + PU_OCB_PIB_OCBCSR2_OR, + PU_OCB_PIB_OCBCSR3_OR + }; + +const uint64_t OCBESRn[4] = {PU_OCB_PIB_OCBESR0, + PU_OCB_PIB_OCBESR1, + PU_OCB_PIB_OCBESR2, + PU_OCB_PIB_OCBESR3 + }; + +const uint64_t OCBSLBRn[4] = {PU_OCB_OCI_OCBSLBR0_SCOM, + PU_OCB_OCI_OCBSLBR1_SCOM, + PU_OCB_OCI_OCBSLBR2_SCOM, + PU_OCB_OCI_OCBSLBR3_SCOM + }; + +const uint64_t OCBSHBRn[4] = {PU_OCB_OCI_OCBSHBR0_SCOM, + PU_OCB_OCI_OCBSHBR1_SCOM, + PU_OCB_OCI_OCBSHBR2_SCOM, + PU_OCB_OCI_OCBSHBR3_SCOM + }; + +const uint64_t OCBSLCSn[4] = {PU_OCB_OCI_OCBSLCS0_SCOM, + PU_OCB_OCI_OCBSLCS1_SCOM, + PU_OCB_OCI_OCBSLCS2_SCOM, + PU_OCB_OCI_OCBSLCS3_SCOM + }; + +const uint64_t OCBSHCSn[4] = {PU_OCB_OCI_OCBSHCS0_SCOM, + PU_OCB_OCI_OCBSHCS1_SCOM, + PU_OCB_OCI_OCBSHCS2_SCOM, + PU_OCB_OCI_OCBSHCS3_SCOM + }; + +const uint64_t OCBSESn[4] = {PU_OCB_OCI_OCBSES0_SCOM, + PU_OCB_OCI_OCBSES1_SCOM, + PU_OCB_OCI_OCBSES2_SCOM, + PU_OCB_OCI_OCBSES3_SCOM + }; + +const uint64_t OCBLWCRn[4] = {PU_OCB_OCI_OCBLWCR0_SCOM, + PU_OCB_OCI_OCBLWCR1_SCOM, + PU_OCB_OCI_OCBLWCR2_SCOM, + PU_OCB_OCI_OCBLWCR3_SCOM + }; + +const uint64_t OCBLWSBRn[4] = {PU_OCB_OCI_OCBLWSBR0_SCOM, + PU_OCB_OCI_OCBLWSBR1_SCOM, + PU_OCB_OCI_OCBLWSBR2_SCOM, + PU_OCB_OCI_OCBLWSBR3_SCOM + }; + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// +/// @brief Reset OCB Channels to default state (ie. scan-0 flush state) +/// +/// @param [in] i_target Chip Target +/// +/// @return FAPI2_RC_SUCCESS on success, else error. +/// +fapi2::ReturnCode pm_ocb_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +//------------------------------------------------------------------------------ +/// +/// @brief Init specified channel to type specified +/// +/// @param [in] i_target Chip Target +/// +/// @param [in] i_ocb_chan Channel to setup from enum PM_OCB_CHAN_NUM. +/// OCB_CHAN0 : OCB Channel 0 +/// OCB_CHAN1 : OCB Channel 1 +/// OCB_CHAN2 : OCB Channel 2 +/// OCB_CHAN3 : OCB Channel 3 +/// +/// @param [in] i_ocb_type Type of channel from PM_OCB_CHAN_TYPE. +/// OCB_TYPE_LIN:Linear w/o address increment +/// OCB_TYPE_LINSTR:Linear with address increment +/// OCB_TYPE_CIRC:Circular mode +/// OCB_TYPE_PUSHQ:Circular Push Queue +/// OCB_TYPE_PULLQ:Circular Pull Queue +/// +/// @param [in] i_ocb_bar 32-bit channel base address(29 bits + "000") +/// +/// @param [in] i_ocb_upd_reg Type of register to init 'PM_OCB_CHAN_REG' +/// OCB_UPD_PIB_REG:Update PIB Register +/// OCB_UPD_PIB_OCI_REG:Update OCI+PIB Registers +/// +/// @param [in] i_ocb_q_len 0-31 length of push or pull queue in +/// (queue_length + 1) * 8B +/// +/// @param [in] i_ocb_ouflow_en Channel flow control from PM_OCB_CHAN_OUFLOW +/// OCB_Q_OUFLOW_EN:Overflow/Underflow Enable +/// OCB_Q_OUFLOW_DIS:Overflow/Underflow Disable +/// +/// @param [in] i_ocb_itp_type Channel interrupt control from PM_OCB_ITPTYPE +/// OCB_Q_ITPTYPE_FULL:Interrupt on Full +/// OCB_Q_ITPTYPE_NOTFULL:Interrupt on Not Full +/// OCB_Q_ITPTYPE_EMPTY:Interrupt on Empty +/// OCB_Q_ITPTYPE_NOTEMPTY:Interrupt on Not Empty +/// @return FAPI2_RC_SUCCESS on success, else error. +/// +fapi2::ReturnCode pm_ocb_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar, + const p9ocb::PM_OCB_CHAN_REG i_ocb_upd_reg, + const uint8_t i_ocb_q_len, + const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_ouflow_en, + const p9ocb::PM_OCB_ITPTYPE i_ocb_itp_type); + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + +fapi2::ReturnCode p9_pm_ocb_init( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9pm::PM_FLOW_MODE i_mode, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_q_len, + const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_ouflow_en, + const p9ocb::PM_OCB_ITPTYPE i_ocb_itp_type) +{ + FAPI_IMP("p9_pm_ocb_init Enter"); + + // ------------------------------------------------------------------------- + // INIT mode: Placeholder; NOOP at present + // ------------------------------------------------------------------------- + if (i_mode == p9pm::PM_INIT) + { + FAPI_DBG(" Channel initialization is a no-op."); + } + // ------------------------------------------------------------------------- + // RESET mode: Change the OCB channel registers to scan-0 flush state + // ------------------------------------------------------------------------- + else if (i_mode == p9pm::PM_RESET) + { + FAPI_INF(" *** Resetting OCB Indirect Channels 0-3"); + FAPI_TRY(pm_ocb_reset(i_target), "ERROR: OCB Reset failed."); + } + // ------------------------------------------------------------------------- + // SETUP mode: Perform user setup of an indirect channel + // ------------------------------------------------------------------------- + else if (i_mode == p9pm::PM_SETUP_ALL || i_mode == p9pm::PM_SETUP_PIB) + { + FAPI_INF("*** Setup OCB Indirect Channel %d ", i_ocb_chan); + p9ocb::PM_OCB_CHAN_REG l_upd_reg = p9ocb::OCB_UPD_PIB_REG; + + if (i_mode == p9pm::PM_SETUP_ALL) + { + l_upd_reg = p9ocb::OCB_UPD_PIB_OCI_REG; + } + + FAPI_TRY(pm_ocb_setup(i_target, i_ocb_chan, i_ocb_type, i_ocb_bar, + l_upd_reg, i_ocb_q_len, i_ocb_ouflow_en, + i_ocb_itp_type), + "ERROR: OCB Setup failed."); + } + // Invalid Mode + else + { + FAPI_ASSERT(false, fapi2::PM_OCBINIT_BAD_MODE().set_BADMODE(i_mode), + "ERROR; Unknown mode passed to proc_ocb_init. Mode %x", + i_mode); + } + +fapi_try_exit: + FAPI_IMP("p9_pm_ocb_init EXIT"); + return fapi2::current_err; +} + + +fapi2::ReturnCode pm_ocb_setup( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar, + const p9ocb::PM_OCB_CHAN_REG i_ocb_upd_reg, + const uint8_t i_ocb_q_len, + const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_ouflow_en, + const p9ocb::PM_OCB_ITPTYPE i_ocb_itp_type) +{ + FAPI_IMP("pm_ocb_setup Enter"); + + uint32_t l_ocbase = 0x0; + fapi2::buffer<uint64_t> l_mask_or(0); + fapi2::buffer<uint64_t> l_mask_clear(0); + fapi2::buffer<uint64_t> l_data64; + + // Verify input queue length is valid + if ((i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) || + (i_ocb_type == p9ocb::OCB_TYPE_PULLQ)) + { + // check queue_len + if (i_ocb_q_len > MAX_OCB_QUE_LEN) + { + FAPI_ASSERT( + false, + fapi2::PM_OCBINIT_BAD_Q_LENGTH_PARM(). + set_BADQLENGTH(i_ocb_q_len), + "ERROR: Bad Queue Length Passed to Procedure => %d", + i_ocb_q_len); + } + } + + // ------------------------------------------------------------------------- + // Init Status and Control Register (OCBCSRn, OCBCSRn_CLEAR, OCBCSRn_OR) + // bit 2 => pull_read_underflow_en (0=disabled 1=enabled) + // bit 3 => push_write_overflow_en (0=disabled 1=enabled) + // bit 4 => ocb_stream_mode (0=disabled 1=enabled) + // bit 5 => ocb_stream_type (0=linear 1=circular) + // ------------------------------------------------------------------------- + + if (i_ocb_type == p9ocb::OCB_TYPE_LIN) // linear non-streaming + { + l_mask_clear.setBit<4, 2>(); + } + else if (i_ocb_type == p9ocb::OCB_TYPE_LINSTR) // linear streaming + { + l_mask_or.setBit<4>(); + l_mask_clear.setBit<5>(); + } + else if (i_ocb_type == p9ocb::OCB_TYPE_CIRC) // circular + { + l_mask_or.setBit<4, 2>(); + } + else if (i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) // push queue + { + l_mask_or.setBit<4, 2>(); + + if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_EN) + { + l_mask_or.setBit<3>(); + } + else if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_DIS) + { + l_mask_clear.setBit<3>(); + } + } + else if (i_ocb_type == p9ocb::OCB_TYPE_PULLQ) // pull queue + { + l_mask_or.setBit<4, 2>(); + + if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_EN) + { + l_mask_or.setBit<2>(); + } + else if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_DIS) + { + l_mask_clear.setBit<2>(); + } + } + + FAPI_DBG("Writing to Channel %d Register : OCB Channel Status & Control", + i_ocb_chan); + + // write using OR mask + FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_OR[i_ocb_chan], l_mask_or), + "ERROR: Unexpected error encountered in write to OCB Channel " + "Status & Control using OR mask"); + // write using AND mask + FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_CLEAR[i_ocb_chan], l_mask_clear), + "ERROR: Unexpected error encountered in write to OCB Channel " + "Status & Control using and mask"); + + //-------------------------------------------------------------------------- + // set address base register for linear, pull queue or push queue + //-------------------------------------------------------------------------- + //don't update bar if type null or circular + if (!(i_ocb_type == p9ocb::OCB_TYPE_NULL || + i_ocb_type == p9ocb::OCB_TYPE_CIRC)) + { + // BAR for linear (streaming / non-streaming) + if ((i_ocb_type == p9ocb::OCB_TYPE_LIN) || + (i_ocb_type == p9ocb::OCB_TYPE_LINSTR)) + { + l_ocbase = OCBARn[i_ocb_chan]; + } + // BAR for push queue + else if (i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) + { + l_ocbase = OCBSHBRn[i_ocb_chan]; + } + // BAR for pull queue + else + { + l_ocbase = OCBSLBRn[i_ocb_chan]; + } + + l_data64.flush<0>().insertFromRight<0, 32>(i_ocb_bar); + + FAPI_DBG("Writing to Channel %d Register : OCB Channel Base Address", + i_ocb_chan); + + FAPI_TRY(fapi2::putScom(i_target, l_ocbase, l_data64), + "ERROR: Unexpected encountered in write to OCB Channel " + "Base Address"); + + } + + // ------------------------------------------------------------------------- + // set up push queue control register + // bits 4:5 => push interrupt action + // 00=full + // 01=not full + // 10=empty + // 11=not empty + // bits 6:10 => push queue length + // bit 31 => push queue enable + // ------------------------------------------------------------------------- + if ((i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) && + (i_ocb_upd_reg == p9ocb::OCB_UPD_PIB_OCI_REG)) + { + l_data64.flush<0>().insertFromRight<6, 5>(i_ocb_q_len); + l_data64.insertFromRight<4, 2>(i_ocb_itp_type); + l_data64.setBit<31>(); + + FAPI_DBG("Writing to Channel %d Register : OCB Channel Push " + "Control/Status Address", i_ocb_chan); + FAPI_TRY(fapi2::putScom(i_target, OCBSHCSn[i_ocb_chan], l_data64), + "ERROR : Unexpected error encountered in write to OCB " + "Channel Push Address"); + } + + // ------------------------------------------------------------------------- + // set up pull queue control register + // bits 4:5 => pull interrupt action + // 00=full + // 01=not full + // 10=empty + // 11=not empty + // bits 6:10 => pull queue length + // bit 31 => pull queue enable + // ------------------------------------------------------------------------- + if ((i_ocb_type == p9ocb::OCB_TYPE_PULLQ) && + (i_ocb_upd_reg == p9ocb::OCB_UPD_PIB_OCI_REG)) + { + l_data64.flush<0>().insertFromRight<6, 5>(i_ocb_q_len); + l_data64.insertFromRight<4, 2>(i_ocb_itp_type); + l_data64.setBit<31>(); + + FAPI_DBG("Writing to Channel %d ," + "Register : OCB Channel Pull Control/Status Address", + i_ocb_chan); + FAPI_TRY(fapi2::putScom(i_target, OCBSLCSn[i_ocb_chan], l_data64), + "ERROR : Unexpected error encountered in write to OCB " + "Channel Pull Address"); + } + + // ------------------------------------------------------------------------- + // Print Channel Configuration Info + // ------------------------------------------------------------------------- + FAPI_IMP("-----------------------------------------------------"); + FAPI_IMP("OCB Channel Configuration "); + FAPI_IMP("-----------------------------------------------------"); + FAPI_IMP(" channel number => %d ", i_ocb_chan); + FAPI_IMP(" channel type => %d ", i_ocb_type); + + if ((i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) || + (i_ocb_type == p9ocb::OCB_TYPE_PULLQ)) + { + FAPI_IMP(" queue length => %d ", i_ocb_q_len); + FAPI_IMP(" interrupt type => %d ", i_ocb_itp_type); + + if (i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) + { + FAPI_IMP(" push write overflow enable => %d ", i_ocb_ouflow_en); + } + else + { + FAPI_IMP(" pull write underflow enable => %d ", i_ocb_ouflow_en); + } + } + + FAPI_IMP(" channel base address => 0x%08X ", i_ocb_bar); + FAPI_IMP("-----------------------------------------------------"); + +fapi_try_exit: + return fapi2::current_err; +} + + +fapi2::ReturnCode pm_ocb_reset( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + FAPI_IMP("p9_pm_ocb_reset Enter"); + fapi2::buffer<uint64_t> l_buf64; + + // vector of reset channels + std::vector<uint8_t> v_reset_chan; + v_reset_chan.push_back(1); + + // ------------------------------------------------------------------------- + // Loop over PIB Registers + // ------------------------------------------------------------------------- + for (auto chan : v_reset_chan) + { + fapi2::buffer<uint64_t> l_data64; + // Clear out OCB Channel BAR registers + FAPI_TRY(fapi2::putScom(i_target, OCBARn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d BAR Register", chan); + + // Clear out OCB Channel control and status registers + l_data64.flush<1>(); + FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_CLEAR[chan], l_data64), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Control & Status Register Clear", chan); + + // Put channels in Circular mode + // - set bits 4,5 (circular mode) using OR + l_data64.flush<0>().setBit<4>().setBit<5>(); + FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_OR[chan], l_data64), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Control & Status OR Register Set", chan); + + // Clear out OCB Channel Error Status registers + FAPI_TRY(fapi2::putScom(i_target, OCBESRn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Error Status Register", chan); + } + + // ------------------------------------------------------------------------- + // Loop over OCI Registers + // ------------------------------------------------------------------------- + for (auto chan : v_reset_chan) + { + fapi2::buffer<uint64_t> l_data64; + // Clear out Pull Base + FAPI_TRY(fapi2::putScom(i_target, OCBSLBRn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Pull Base Register", chan); + + // Clear out Push Base + FAPI_TRY(fapi2::putScom(i_target, OCBSHBRn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Push Base Register", chan); + + // Clear out Pull Control & Status + FAPI_TRY(fapi2::putScom(i_target, OCBSLCSn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Pull Control & Status Register", chan); + + // Clear out Push Control & Status + FAPI_TRY(fapi2::putScom(i_target, OCBSHCSn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Push Control & Status Register", chan); + + // Clear out Stream Error Status + FAPI_TRY(fapi2::putScom(i_target, OCBSESn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Stream Error Status Register", chan); + + // Clear out Linear Window Control + FAPI_TRY(fapi2::putScom(i_target, OCBLWCRn[chan], 0), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Linear Window Control Register", chan); + + // Clear out Linear Window Base + // - set bits 3:9 + l_data64.setBit<3, 7>(); + FAPI_TRY(fapi2::putScom(i_target, OCBLWSBRn[chan], l_data64), + "**** ERROR : Unexpected error encountered in write to OCB " + "Channel %d Linear Window Base Register", chan); + } + + // Set Interrupt Source Mask Registers 0 & 1 + // - keep word1 0's for simics + l_buf64.flush<0>().insertFromRight<0, 32>(INTERRUPT_SRC_MASK_REG); + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OIMR0_SCOM2, + l_buf64), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Source Mask Register0 (OIMR0)"); + + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OIMR1_SCOM2, + l_buf64), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Source Mask Register1 (OIMR1)"); + + // Clear OCC Interrupt Type Registers 0 & 1 + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OITR0_SCOM2, + 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Type Register0 (OITR0)"); + + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OITR1_SCOM2, + 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Type Register1 (OITR1)"); + + // Clear OCC Interupt Edge/Polarity Registers 0 & 1 + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OIEPR0_SCOM2, + 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Edge Polarity Register0 (OIEPR0)"); + + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OIEPR1_SCOM2, + 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Edge Polarity Register1 (OIEPR1)"); + + // Clear OCC Interrupt Source Registers 0 & 1 + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OISR0_SCOM2, + 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Source Register0 (OISR0)"); + + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OISR1_SCOM2, + 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Source Register1 (OISR1)"); + + // Clear Interrupt Route (A, B, C) Registers 0 & 1 + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR0A_SCOM, 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt 0 Route A Register (OIRR0A)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR0B_SCOM, 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt 0 Route B Register (OIRR0A)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR0C_SCOM, 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt 0 Route C Register (OIRR0A)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR1A_SCOM, 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt 1 Route A Register (OIRR1A)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR1B_SCOM, 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt 1 Route B Register (OIRR1B)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR1C_SCOM, 0), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt 1 Route C Register (OIRR1C)"); + + // Clear OCC Interrupt Timer Registers 0 & 1 + // - need bits 0&1 set to clear register + l_buf64.flush<0>().setBit<0, 2>(); + + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OTR0_SCOM, + l_buf64), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Timer0 Register (OTR0)"); + + FAPI_TRY(fapi2::putScom(i_target, + PU_OCB_OCI_OTR1_SCOM, + l_buf64), + "**** ERROR : Unexpected error encountered in write to OCC " + "Interrupt Timer1 Register (OTR1)"); + + // Clear PBA Enable Marker Acknowledgement mode to remove collisions + // with any accesses to the OCB DCR registers (eg OSTOESR). + // This function is only enabled by OCC firmware and is not via + // hardware procedures. + FAPI_TRY(fapi2::getScom(i_target, PU_PBAMODE_SCOM, l_buf64), + "**** ERROR : Failed to fetch PBA mode control status"); + l_buf64.clearBit<8>(); + FAPI_TRY(fapi2::putScom(i_target, PU_PBAMODE_SCOM, l_buf64), + "**** ERROR : Failed to write PBA mode control"); + + // Clear OCC special timeout error status register + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OSTOESR, 0), + "**** ERROR : Failed to write OSTESR"); + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H new file mode 100644 index 00000000..1130fcaa --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H @@ -0,0 +1,164 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_pm_ocb_init.H +/// @brief Setup and configure OCB channels +/// +// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com> +// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team: PM +// *HWP Level: 2 +// *HWP Consumed by: FSP:HS + +#ifndef _P9_PM_OCB_INIT_H_ +#define _P9_PM_OCB_INIT_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <p9_pm.H> +#include <fapi2.H> +#include <p9_misc_scom_addresses.H> + +//------------------------------------------------------------------------------ +// Constants definitions +//------------------------------------------------------------------------------ +namespace p9ocb +{ +/// @enum PM_OCB_CHAN_NUM +enum PM_OCB_CHAN_NUM +{ + OCB_CHAN0 = 0x00, ///< OCB Channel 0 + OCB_CHAN1 = 0x01, ///< OCB Channel 1 + OCB_CHAN2 = 0x02, ///< OCB Channel 2 + OCB_CHAN3 = 0x03 ///< OCB Channel 3 +}; + +/// @enum PM_OCB_CHAN_TYPE +enum PM_OCB_CHAN_TYPE +{ + OCB_TYPE_NULL, ///< Do nothing + OCB_TYPE_LIN, ///< Linear w/o address incrementation + OCB_TYPE_LINSTR, ///< Linear with address incrementation + OCB_TYPE_LINWIN, ///< Linear window mode + OCB_TYPE_CIRC, ///< Circular mode + OCB_TYPE_PUSHQ, ///< Circular Push Queue + OCB_TYPE_PULLQ ///< Circular Pull Queue +}; + +/// @enum PM_OCB_CHAN_REG +enum PM_OCB_CHAN_REG +{ + OCB_UPD_PIB_REG, ///< Update PIB Register + OCB_UPD_PIB_OCI_REG ///< Update OCI Register +}; + +/// @enum PM_OCB_CHAN_OUFLOW +enum PM_OCB_CHAN_OUFLOW +{ + OCB_Q_OUFLOW_NULL, ///< Do nothing + OCB_Q_OUFLOW_EN, ///< Overflow/Underflow Enable + OCB_Q_OUFLOW_DIS ///< Overflow/Underflow Disable +}; + +/// @enum PM_OCB_ITPTYPE +enum PM_OCB_ITPTYPE +{ + OCB_Q_ITPTYPE_NULL, ///< Overflow/Underflow Disable + OCB_Q_ITPTYPE_FULL, ///< Interrupt on Full + OCB_Q_ITPTYPE_NOTFULL, ///< Interrupt on Not Full + OCB_Q_ITPTYPE_EMPTY, ///< Interrupt on Empty + OCB_Q_ITPTYPE_NOTEMPTY ///< Interrupt on Not Empty +}; +} // END OF NAMESPACE p9ocb + +typedef fapi2::ReturnCode (*p9_pm_ocb_init_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const p9pm::PM_FLOW_MODE, + const p9ocb::PM_OCB_CHAN_NUM, + const p9ocb::PM_OCB_CHAN_TYPE, + const uint32_t, + const uint8_t, + const p9ocb::PM_OCB_CHAN_OUFLOW, + const p9ocb::PM_OCB_ITPTYPE); + +extern "C" +{ +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +/// +/// @brief Configure OCB Channels based on mode and parameters passed +/// +/// @param [in] i_target Chip Target +/// +/// @param [in] i_mode Mode of operation from enum PM_FLOW_MODE. +/// PM_RESET/PM_INIT/PM_SETUP_ALL +/// +/// @param [in] i_ocb_chan Channel to setup from enum PM_OCB_CHAN_NUM. +/// OCB_CHAN0 : OCB Channel 0 +/// OCB_CHAN1 : OCB Channel 1 +/// OCB_CHAN2 : OCB Channel 2 +/// OCB_CHAN3 : OCB Channel 3 +/// +/// @param [in] i_ocb_type Type of channel from PM_OCB_CHAN_TYPE. +/// OCB_TYPE_LIN:Linear w/o address increment +/// OCB_TYPE_LINSTR:Linear with address increment +/// OCB_TYPE_CIRC:Circular mode +/// OCB_TYPE_PUSHQ:Circular Push Queue +/// OCB_TYPE_PULLQ:Circular Pull Queue +/// +/// @param [in] i_ocb_bar 32-bit channel base address(29 bits + "000") +/// +/// @param [in] i_ocb_q_len 0-31 length of push or pull queue in +/// (queue_length + 1) * 8B +/// +/// @param [in] i_ocb_ouflow_en Channel flow control from PM_OCB_CHAN_OUFLOW +/// OCB_Q_OUFLOW_EN:Overflow/Underflow Enable +/// OCB_Q_OUFLOW_DIS:Overflow/Underflow Disable +/// +/// @param [in] i_ocb_itp_type Channel interrupt control from PM_OCB_ITPTYPE +/// OCB_Q_ITPTYPE_FULL:Interrupt on Full +/// OCB_Q_ITPTYPE_NOTFULL:Interrupt on Not Full +/// OCB_Q_ITPTYPE_EMPTY:Interrupt on Empty +/// OCB_Q_ITPTYPE_NOTEMPTY:Interrupt on Not Empty +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. +/// + fapi2::ReturnCode p9_pm_ocb_init( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9pm::PM_FLOW_MODE i_mode, + const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan, + const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type, + const uint32_t i_ocb_bar, + const uint8_t i_ocb_q_len, + const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_ouflow_en, + const p9ocb::PM_OCB_ITPTYPE i_ocb_itp_type); +} // extern "C" + +#endif // _P9_PM_OCB_INIT_H_ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C new file mode 100644 index 00000000..4809d65e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C @@ -0,0 +1,148 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_utils.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_pm_utils.C +/// @brief Utility functions for PM FAPIs +/// + +// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : HS + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include <p9_pm.H> +#include <p9_pm_utils.H> +#include <p9_const_common.H> + +fapi2::ReturnCode p9_pm_glob_fir_trace( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const char* i_msg) +{ + FAPI_INF("p9_pm_glob_fir_trace Enter"); + +#if 0 // The CONST_UINT64_T definition in P9 const_common.H takes 4 arguments - + // CONST_UINT64_T(name, expr, unit, meth). Need to figure out the values + // for "unit" and "meth" for the below declarations. + CONST_UINT64_T( GLOB_XSTOP_FIR_0x01040000, ULL(0x01040000) ); + CONST_UINT64_T( GLOB_RECOV_FIR_0x01040001, ULL(0x01040001) ); + CONST_UINT64_T( TP_LFIR_0x0104000A, ULL(0x0104000A) ); +#endif + + // Note: i_msg is put on on each record to allow for trace "greps" + // so as to see the "big picture" across when + + uint8_t l_traceEnFlag = false; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::buffer<uint64_t> l_data64; + +#if 0 // Uncomment when attribute ATTR_PM_GLOBAL_FIR_TRACE_EN is ready + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_GLOBAL_FIR_TRACE_EN, + FAPI_SYSTEM, + l_traceEnFlag), + "FAPI_ATTR_GET for attribute ATTR_PM_GLOBAL_FIR_TRACE_EN"); +#endif + + // Continue if trace is enabled. + if (false == l_traceEnFlag) + { + goto fapi_try_exit; + } + + // ****************************************************************** + // Check for xstops and recoverables and put in the trace + // ****************************************************************** + { +#if 0 // Uncomment when the scom address is defined + FAPI_TRY(fapi2::getScom(i_target, + READ_GLOBAL_XSTOP_FIR_0x570F001B, + l_data64)); +#endif + + if(l_data64) + { + FAPI_INF("Xstop is **ACTIVE** %s", i_msg); + } + } + + { +#if 0 // Uncomment when the scom address is defined + FAPI_TRY(fapi2::getScom(i_target, + READ_GLOBAL_RECOV_FIR_0x570F001C, + l_data64)); +#endif + + if(l_data64) + { + FAPI_INF("Recoverable attention is **ACTIVE** %s", i_msg); + } + } + + { +#if 0 // Uncomment when the scom address is defined + FAPI_TRY(fapi2::getScom(i_target, + GLOB_XSTOP_FIR_0x01040000, + l_data64)); +#endif + + if(l_data64) + { + FAPI_INF("Glob Xstop FIR is **ACTIVE** %s", i_msg); + } + } + + { +#if 0 // Uncomment when the scom address is defined + FAPI_TRY(fapi2::getScom(i_target, + GLOB_RECOV_FIR_0x01040001, + l_data64)); +#endif + + if(l_data64) + { + FAPI_INF("Glob Recov FIR is **ACTIVE** %s", i_msg); + } + } + + { +#if 0 // Uncomment when the scom address is defined + FAPI_TRY(fapi2::getScom(i_target, + TP_LFIR_0x0104000A, + l_data64)); +#endif + + if(l_data64) + { + FAPI_INF("TP LFIR is **ACTIVE** %s", i_msg); + } + } + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H new file mode 100644 index 00000000..3524991e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H @@ -0,0 +1,105 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_utils.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_pm_utils.H +/// @brief Utility functions for PM FAPIs +/// + +// *HWP HWP Owner : Amit Kumar <akumar3@us.ibm.com> +// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Bilicon Patil <bilpatil@in.ibm.com> +// *HWP Team : PM +// *HWP Level : 1 +// *HWP Consumed by : HS + +#ifndef _P9_PM_UTILS_H_ +#define _P9_PM_UTILS_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> + +//------------------------------------------------------------------------------ +// Common macros +//------------------------------------------------------------------------------ + +#define SET_FIR_ACTION(b, x, y) \ + action_0.writeBit<b>(x); \ + action_1.writeBit<b>(y); + +#define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);} +#define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);} +#define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);} +#define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);} +#define SET_FIR_MASKED(b){mask.setBit<b>();} +#define CLEAR_FIR_MASK(b){mask.clearBit<b>()} + + +/** + * @brief helper function to swizzle given input data + * @note swizles bytes to handle endianess issue. + */ +#if( __BYTE_ORDER == __BIG_ENDIAN ) + +// NOP if it is a big endian system +#define RevLe16(WORD) WORD +#define RevLe32(WORD) WORD +#define RevLe64(WORD) WORD + +#else +#define RevLe16(WORD) \ + ( (((WORD) >> 8) & 0x00FF) | (((WORD) << 8) & 0xFF00) ) + +#define RevLe32(WORD) \ + ( (((WORD) >> 24) & 0x000000FF) | (((WORD) >> 8) & 0x0000FF00) | \ + (((WORD) << 8) & 0x00FF0000) | (((WORD) << 24) & 0xFF000000) ) + +#define RevLe64(WORD) \ + ( (((WORD) >> 56) & 0x00000000000000FF) | \ + (((WORD) >> 40) & 0x000000000000FF00)| \ + (((WORD) >> 24) & 0x0000000000FF0000) | \ + (((WORD) >> 8) & 0x00000000FF000000) | \ + (((WORD) << 8) & 0x000000FF00000000) | \ + (((WORD) << 24) & 0x0000FF0000000000) | \ + (((WORD) << 40) & 0x00FF000000000000) | \ + (((WORD) << 56) & 0xFF00000000000000) ) +#endif + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ + +/// +/// @brief Trace a set of FIRs (Globals and select Locals) +/// @param[in] i_target Chip target +/// @param[in] i_msg String to put out in the trace +/// @return FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9_pm_glob_fir_trace( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const char* i_msg); + +#endif // _P9_PM_UTILS_H_ diff --git a/src/import/chips/p9/procedures/hwp/pm/pmfiles.mk b/src/import/chips/p9/procedures/hwp/pm/pmfiles.mk new file mode 100644 index 00000000..e34a62c4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/pm/pmfiles.mk @@ -0,0 +1,44 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: import/chips/p9/procedures/hwp/pm/pmfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file pmfiles.mk +# +# @brief mk for including pm object files +# +########################################################################## +# Object Files +########################################################################## + +PM-CPP-SOURCES +=p9_pm_ocb_indir_access.C +PM-CPP-SOURCES +=p9_pm_ocb_indir_setup_circular.C +PM-CPP-SOURCES +=p9_pm_ocb_indir_setup_linear.C +PM-CPP-SOURCES +=p9_pm_ocb_init.C +PM-CPP-SOURCES +=p9_pm_utils.C +PM-CPP-SOURCES +=p9_block_wakeup_intr.C +PM-C-SOURCES = +PM-S-SOURCES = + +PM_OBJECTS += $(PM-CPP-SOURCES:.C=.o) +PM_OBJECTS += $(PM-C-SOURCES:.c=.o) +PM_OBJECTS += $(PM-S-SOURCES:.S=.o) |
