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path: root/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
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Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C')
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index e04d078e..938be1bd 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -363,6 +363,11 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
{
FAPI_DBG("Drop clk_div_bypass for Mc chiplet");
FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(targ));
+
+ //Setting VITL_AL config bit to disable listening to cross-chiplet DDR sync signal
+ FAPI_DBG("Set VITL_AL for MC chiplet");
+ FAPI_TRY(fapi2::putScom(targ, PERV_NET_CTRL0_WOR,
+ p9SbeChipletReset::NET_CNTL0_SET_VITL_AL));
}
}
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