diff options
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 5 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index e04d078e..938be1bd 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -363,6 +363,11 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const { FAPI_DBG("Drop clk_div_bypass for Mc chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(targ)); + + //Setting VITL_AL config bit to disable listening to cross-chiplet DDR sync signal + FAPI_DBG("Set VITL_AL for MC chiplet"); + FAPI_TRY(fapi2::putScom(targ, PERV_NET_CTRL0_WOR, + p9SbeChipletReset::NET_CNTL0_SET_VITL_AL)); } } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index 1c4ffd0a..74b105f0 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -63,6 +63,7 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull, NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull, NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull, + NET_CNTL0_SET_VITL_AL = 0x0020000000000000ull, HANG_PULSE_0X10 = 0x10, HANG_PULSE_0X0F = 0x0F, HANG_PULSE_0X06 = 0x06, |
