diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest')
6 files changed, 261 insertions, 23 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C index 55767769..aa69a0b8 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -145,7 +145,7 @@ fapi_try_exit: // NOTE: see comments above function prototype in header -fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const p9_fbc_utils_addr_mode_t i_addr_mode, uint64_t& o_base_address_nm0, @@ -198,7 +198,6 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( } // else, leave chip ID=0 for the purposes of establishing drawer base address - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy), "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)"); @@ -245,3 +244,128 @@ fapi_try_exit: FAPI_DBG("End"); return fapi2::current_err; } + + +// NOTE: see comments above function prototype in header +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9_fbc_utils_addr_mode_t i_addr_mode, + std::vector<uint64_t>& o_base_address_nm0, + std::vector<uint64_t>& o_base_address_nm1, + std::vector<uint64_t>& o_base_address_m, + uint64_t& o_base_address_mmio) +{ + uint64_t l_base_address_nm0 = 0; + uint64_t l_base_address_nm1 = 0; + uint64_t l_base_address_m = 0; + uint8_t l_addr_extension_group_id; + uint8_t l_addr_extension_chip_id; + fapi2::buffer<uint64_t> l_addr_extension_enable = 0; + uint8_t l_regions_per_msel = 1; + std::vector<uint8_t> l_alias_bit_positions; + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + + fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode; + fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2_Type l_hw423589_option2; + + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target, + i_addr_mode, + l_base_address_nm0, + l_base_address_nm1, + l_base_address_m, + o_base_address_mmio), + "Error from p9_fbc_utils_get_chip_base_address_no_aliases"); + + // read attributes defining address extension enable configuration + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, i_target, l_extended_addressing_mode), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, i_target, l_hw423589_option2), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)"); + + if (l_extended_addressing_mode) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, + FAPI_SYSTEM, + l_addr_extension_group_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, + FAPI_SYSTEM, + l_addr_extension_chip_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID"); + + // align to RA + l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_GROUP_ID_START_BIT, + FABRIC_ADDR_LS_GROUP_ID_END_BIT - FABRIC_ADDR_LS_GROUP_ID_START_BIT + 1 > + (l_addr_extension_group_id); + l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_CHIP_ID_START_BIT, + FABRIC_ADDR_LS_CHIP_ID_END_BIT - FABRIC_ADDR_LS_CHIP_ID_START_BIT + 1 > + (l_addr_extension_chip_id); + } + + // walk across bits set in enable bit field, count number of bits set + // to determine permutations + FAPI_DBG("Address extension enable mask: 0x%016lX", l_addr_extension_enable()); + + if (l_addr_extension_enable != 0) + { + for (uint8_t ii = FABRIC_ADDR_LS_GROUP_ID_START_BIT; + ii <= FABRIC_ADDR_LS_CHIP_ID_END_BIT; + ii++) + { + if (l_addr_extension_enable.getBit(ii)) + { + l_regions_per_msel *= 2; + l_alias_bit_positions.push_back(ii); + } + } + } + + FAPI_DBG("Valid regions per msel: %d", l_regions_per_msel); + + for (uint8_t l_region = 0; + l_region < l_regions_per_msel; + l_region++) + { + fapi2::buffer<uint64_t> l_alias_mask = 0; + FAPI_DBG("Generating region: %d", l_region); + + if (l_region) + { + uint8_t l_value = l_region; + + for (int jj = l_alias_bit_positions.size() - 1; + jj >= 0; + jj--) + { + l_alias_mask.writeBit(l_value & 1, + l_alias_bit_positions[jj]); + l_value = l_value >> 1; + } + } + + FAPI_DBG("Mask: 0x%016lX", l_alias_mask()); + + // hide region reserved for GPU LPC + if (!l_hw423589_option2 || (l_region != 1)) + { + o_base_address_nm0.push_back(l_base_address_nm0 | + l_alias_mask()); + o_base_address_m.push_back(l_base_address_m | + l_alias_mask()); + } + + // second non-mirrored msel region unusable with HW423589_OPTION2 + // (no MCD resources available to map) + if (!l_hw423589_option2) + { + o_base_address_nm1.push_back(l_base_address_nm1 | + l_alias_mask()); + } + } + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index 4b3a90a4..a160ad18 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -69,6 +69,13 @@ const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL; // cacheline size = 128B const uint64_t FABRIC_CACHELINE_SIZE = 0x80; +// chip address extension mask, for HW423589_OPTION2 +// repurposes chip ID(0:2) as address bits +const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0; +const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7; + +const uint64_t MAX_INTERLEAVE_GROUP_SIZE = 0x40000000000ULL; // 4_TB +const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL; // 512_GB //------------------------------------------------------------------------------ // Function prototypes @@ -99,17 +106,22 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); /// -/// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip +/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip, +/// accounting for fixed msel assignments, but not aliasing +/// enabled by chip address extension facility /// /// @param[in] i_target Reference to processor chip target /// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations -/// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip -/// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip -/// @param[out] o_base_address_m Mirrored base address for this chip -/// @param[out] o_base_address_mmio MMIO base address for this chip +/// @param[out] o_base_address_nm0 Non-mirrored base address for +/// this chip (covering msel=0b00) +/// @param[out] o_base_address_nm1 Non-mirrored base address for +/// this chip (covering msel=0b01) +/// @param[out] o_base_address_m Mirrored base address for +/// this chip (covering msel=0b10) +/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11) /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. /// -fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const p9_fbc_utils_addr_mode_t i_addr_mode, uint64_t& o_base_address_nm0, @@ -117,4 +129,29 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( uint64_t& o_base_address_m, uint64_t& o_base_address_mmio); +/// +/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip, +/// accounting for fixed msel assignments as well as variable aliasing +/// enabled by chip address extension facility +/// +/// @param[in] i_target Reference to processor chip target +/// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations +/// @param[out] o_base_address_nm0 List of non-mirrored base addresses for +/// this chip (covering msel=0b00), ordered from smallest->largest +/// @param[out] o_base_address_nm1 List of non-mirrored base addresses for +/// this chip (covering msel=0b01), ordered from smallest->largest +/// @param[out] o_base_address_m List of mirrored base addresses for +/// this chip (covering msel=0b10), ordered from +/// smallest->largest +/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11) +/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const p9_fbc_utils_addr_mode_t i_addr_mode, + std::vector<uint64_t>& o_base_address_nm0, + std::vector<uint64_t>& o_base_address_nm1, + std::vector<uint64_t>& o_base_address_m, + uint64_t& o_base_address_mmio); + #endif // _P9_FBC_UTILS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C index 3235616f..7f488ef5 100755 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C @@ -44,6 +44,8 @@ #include <p9_fbc_utils.H> #include <p9_misc_scom_addresses.H> #include <p9_misc_scom_addresses_fld.H> +#include <p9n2_misc_scom_addresses.H> +#include <p9n2_misc_scom_addresses_fld.H> //------------------------------------------------------------------------------ // Constant definitions @@ -75,14 +77,19 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) fapi2::buffer<uint64_t> l_cmd_data; fapi2::buffer<uint64_t> l_status_data_act; fapi2::buffer<uint64_t> l_status_data_exp; + fapi2::buffer<uint64_t> l_mode_data; fapi2::buffer<uint64_t> l_hp_mode_data; + fapi2::buffer<uint64_t> l_nmmu_cqmode_data; bool l_fbc_is_initialized, l_fbc_is_running; fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_pump_mode; fapi2::ATTR_PROC_FABRIC_GROUP_ID_Type l_fbc_group_id_abs; fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID_Type l_fbc_group_id_eff; fapi2::ATTR_PROC_FABRIC_CHIP_ID_Type l_fbc_chip_id_abs; fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID_Type l_fbc_chip_id_eff; + fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode; uint8_t l_fbc_xlate_addr_to_id = 0; + uint8_t l_addr_extension_group_id = 0; + uint8_t l_addr_extension_chip_id = 0; // before fabric is initialized, configure resources which live in hotplug registers // but which themselves are not hotpluggable @@ -96,14 +103,60 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_CHIP_ID)"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target, l_fbc_chip_id_eff), "Error from FAPI_ATTR_GET (ATTR_PROC_EFF_FABRIC_CHIP_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, i_target, l_extended_addressing_mode), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)"); + + // sample center mode and hotplug mode registers + FAPI_TRY(fapi2::getScom(i_target, PU_PB_CENT_SM0_PB_CENT_MODE, l_mode_data), + "Error from getScom (PU_PB_CENT_SM0_PB_CENT_MODE)"); FAPI_TRY(fapi2::getScom(i_target, PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR, l_hp_mode_data), "Error from getScom (PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR)"); + // update mode register content + if (l_extended_addressing_mode) + { + fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2_Type l_hw423589_option2; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, i_target, l_hw423589_option2), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)"); + + if (l_hw423589_option2) + { + l_addr_extension_group_id = CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2; + l_addr_extension_chip_id = CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2; + } + + // enable extended addressing mode, seed attributes from defaults + // and use attribute values to configure fabric -- should allow for testing + // alternate configurations via Cronus with const attribute overrides + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_addr_extension_group_id), + "Error from FAPI_ATTR_SET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_addr_extension_chip_id), + "Error from FAPI_ATTR_SET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_addr_extension_group_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_addr_extension_chip_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)"); + + l_mode_data.insertFromRight<P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK, + P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN> + ((l_addr_extension_group_id << 3) | l_addr_extension_chip_id); + } + // determine HW XOR mask based on fabric ID attributes l_fbc_xlate_addr_to_id = ((l_fbc_group_id_abs << 3) | l_fbc_chip_id_abs); l_fbc_xlate_addr_to_id ^= ((l_fbc_group_id_eff << 3) | l_fbc_chip_id_eff); + // update hotplug mode register content l_hp_mode_data.insertFromRight<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID, // XOR mask PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN>(l_fbc_xlate_addr_to_id); @@ -120,7 +173,17 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) l_hp_mode_data.setBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP>(); } - // write back to all hotplug registers (EAST/CENTER/WEST, NEXT & CURR) + // write back to all mode registers (EAST/CENTER/WEST) + FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_MODE, l_mode_data), + "Error from putScom (PU_PB_CENT_SM0_PB_CENT_MODE)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_MODE, l_mode_data), + "Error from putScom (PU_PB_EAST_MODE)"); + + FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_MODE, l_mode_data), + "Error from putScom (PU_PB_WEST_SM0_PB_WEST_MODE)"); + + // write back to all hotplug mode registers (EAST/CENTER/WEST, NEXT & CURR) FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR, l_hp_mode_data), "Error from putScom (PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR)"); FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT, l_hp_mode_data), @@ -136,6 +199,18 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT, l_hp_mode_data), "Error from putScom (PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT)"); + // set NMMU extended addressing configuration prior to fabric init + if (l_extended_addressing_mode) + { + FAPI_TRY(fapi2::getScom(i_target, P9N2_PU_NMMU_MMCQ_PB_MODE_REG, l_nmmu_cqmode_data), + "Error from getScom (P9N2_PU_NMMU_MMCQ_PB_MODE_REG)"); + l_nmmu_cqmode_data.insertFromRight<P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK, + P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK_LEN> + ((l_addr_extension_group_id << 3) | l_addr_extension_chip_id); + FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_NMMU_MMCQ_PB_MODE_REG, l_nmmu_cqmode_data), + "Error from getScom (P9N2_PU_NMMU_MMCQ_PB_MODE_REG)"); + } + // check state of fabric pervasive stop control signal // if set, this would prohibit all fabric commands from being broadcast FAPI_DBG("Checking status of FBC stop ..."); diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index 8bffe723..fed5330f 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -310,12 +310,13 @@ calc_image_footprint( // target base address = (drawer non-mirrored base address) + // (hostboot HRMOR offset) + // (bootloader offset) - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target, - ABS_FBC_GRP_ID_ONLY, - l_drawer_base_address_nm0, - l_drawer_base_address_nm1, - l_drawer_base_address_m, - l_drawer_base_address_mmio), + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases( + i_master_chip_target, + ABS_FBC_GRP_ID_ONLY, + l_drawer_base_address_nm0, + l_drawer_base_address_nm1, + l_drawer_base_address_m, + l_drawer_base_address_mmio), "Error from p9_fbc_utils_get_chip_base_address (drawer)"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, @@ -404,7 +405,7 @@ get_bootloader_config_data( FAPI_DBG("Start"); // read platform initialized attributes to determine struct content - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target, + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_master_chip_target, EFF_FBC_GRP_CHIP_IDS, l_chip_base_address_nm0, l_chip_base_address_nm1, diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C index d65b37c3..3bd71971 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C @@ -226,7 +226,7 @@ p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) // determine base address // = (drawer non-mirrored base address) + (hostboot HRMOR offset) // min MCS base size is 4GB, local HB will always be below - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target, ABS_FBC_GRP_ID_ONLY, l_chip_base_address_nm0, l_chip_base_address_nm1, diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index e8fc9904..49a12b75 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -153,12 +153,13 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) } // determine base address of chip nm/m/mmmio regions in real address space - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, - EFF_FBC_GRP_CHIP_IDS, - l_base_addr_nm0, - l_base_addr_nm1, - l_base_addr_m, - l_base_addr_mmio), + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases( + i_target, + EFF_FBC_GRP_CHIP_IDS, + l_base_addr_nm0, + l_base_addr_nm1, + l_base_addr_m, + l_base_addr_mmio), "Error from p9_fbc_utils_get_chip_base_address"); // set XSCOM BAR |
