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-rwxr-xr-xsbe/test/test.xml5
-rwxr-xr-xsbe/test/testScom.xml5
2 files changed, 5 insertions, 5 deletions
diff --git a/sbe/test/test.xml b/sbe/test/test.xml
index 1b23623a..505a875e 100755
--- a/sbe/test/test.xml
+++ b/sbe/test/test.xml
@@ -18,6 +18,11 @@
<simcmd>sim->frontend_current_processor = p9Proc0.sbe.ppe</simcmd>
<exitonerror>yes</exitonerror>
</testcase>
+ <!-- Workaround to set clock regs. Once simics have fix, we can remove it -->
+ <testcase>
+ <simcmd>p9Proc0.proc_chip.invoke parallel_store LOGIC 0xffc50000 \"00000000_00000001\" 64</simcmd>
+ </testcase>
+ <!-- Write value to a register and than read it back -->
<!-- Register SBE tools -->
<testcase>
<simcmd>run-python-file targets/p9_nimbus/sbeTest/simics-debug-framework.py</simcmd>
diff --git a/sbe/test/testScom.xml b/sbe/test/testScom.xml
index 01228e2a..2e4bf051 100755
--- a/sbe/test/testScom.xml
+++ b/sbe/test/testScom.xml
@@ -1,10 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
- <!-- Workaround to set clock regs. Once simics have fix, we can remove it -->
- <testcase>
- <simcmd>p9Proc0.proc_chip.invoke parallel_store LOGIC 0xffc50000 \"00000000_00000001\" 64</simcmd>
- </testcase>
- <!-- Write value to a register and than read it back -->
<testcase>
<simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd>
<exitonerror>yes</exitonerror>
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