sbe/test/test.xml


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<?xml version="1.0" encoding="UTF-8"?>

<integrationtest>
	<platform startsimargs="--notar --norun --sim_parms -nre">
		<machine>%%machine%%</machine>

        <test>
           <!-- Set IVPR to point to sbe start address ( currently PIBMEM) -->
          <testcase>
              <simcmd>p9Proc0.sbe.mibo_space.write 0xc0000160 0xFFFE800000000000 8 -b</simcmd>
              <exitonerror>yes</exitonerror>
          </testcase>
          <testcase>
              <simcmd>p9Proc0.sbe.mibo_space.write 0xc00e0000 0x5000000000000000 8 -b</simcmd>
              <exitonerror>yes</exitonerror>
          </testcase>
          <testcase>
              <simcmd>sim->frontend_current_processor = p9Proc0.sbe.ppe</simcmd>
              <exitonerror>yes</exitonerror>
          </testcase>
          <!-- Workaround to set clock regs. Once simics have fix, we can remove it -->
          <testcase>
            <simcmd>p9Proc0.proc_chip.invoke parallel_store LOGIC 0xffc50000 \"00000000_00000001\" 64</simcmd>
          </testcase>
      <!-- Write value to a register and than read it back -->
           <!-- Register SBE tools -->
          <testcase>
              <simcmd>run-python-file targets/p9_nimbus/sbeTest/simics-debug-framework.py</simcmd>
              <exitonerror>yes</exitonerror>
          </testcase>
            <include>../simics/targets/p9_nimbus/sbeTest/testIstep.xml</include>
            <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include>
            <include>../simics/targets/p9_nimbus/sbeTest/testGeneric.xml</include>
        </test>
	</platform>
</integrationtest>