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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-11-10 12:49:00 +0100 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-11-21 20:47:58 -0500 |
| commit | f078f464c0fd772d8e3a1bad3201ddf98f6b66db (patch) | |
| tree | 94360225de43363dfd4e2cf45a600c317f08922c /src | |
| parent | 04747ee5bdf29a9550b7c7561da72971baef8ca1 (diff) | |
| download | talos-sbe-f078f464c0fd772d8e3a1bad3201ddf98f6b66db.tar.gz talos-sbe-f078f464c0fd772d8e3a1bad3201ddf98f6b66db.zip | |
p9_sbe_attr_setup updates
set the ATTR_IS_SP_MODE attribute
from MBX scratch reg 3
CQ : HW393961
Change-Id: Id1eb51173451680367de614c114bd0732a678e5b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32468
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32469
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src')
3 files changed, 11 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index 4904dcc8..827fa60b 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -207,6 +207,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const //read_scratch3_reg { uint8_t l_is_mpipl = 0; + uint8_t l_is_sp_mode = 0; if ( l_read_scratch8.getBit<2>() ) { @@ -219,6 +220,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const FAPI_DBG("Setting up ATTR_IS_MPIPL"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl)); + + l_read_scratch_reg.extractToRight<3, 1>(l_is_sp_mode); + + FAPI_DBG("Setting up ATTR_IS_SP_MODE"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IS_SP_MODE, i_target_chip, l_is_sp_mode)); } else { diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 7d51583f..e93681ce 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -564,5 +564,9 @@ attribute tank <name>ATTR_PULSE_MODE_VALUE</name> <value>0x0</value> </entry> + <entry> + <name>ATTR_IS_SP_MODE</name> + <value>0x0</value> + </entry> </entries> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index f58006a3..ebbc87b1 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -106,6 +106,7 @@ <enum>FSP_LESS = 0x0,FSP = 0x1</enum> <persistRuntime/> <platInit/> + <writeable/> </attribute> <attribute> |
