future proof EC feature attributes, add missing P9N DD2 inits

  redefine EC feature attributes, using inverse logic where required, to qualify
  inits specific to P9N DD1 where possible, to eliminate need for updates for
  future chips in plan

  attempt to remove usage of generic P9N_DD1_SPY_NAMES and P9N_DD2_SPY_NAMES
  attributes added to support initial P9NDD2 engineering data -- several spies
  were not being set as a result

  -----------------
  initfile updates:
  -----------------

  p9.cme.scan.initfile
    add HW391162, SCAN_SICR_TLBIE_QUIESCE feature attributes

  p9.core.common.scan.initfile
    remove fused core init, it was applying scan default for P9N DD1 and is
    not needed for P9N DD2+ given fuse controls

  p9.core.scan.initfile
    add CORE_P9NDD1 to qualify P9N DD1 specific register hierarchy and
    dial programming

    replace usage of P9N_DD1_SPY_NAMES, P9N_DD2_SPY_NAMES using CORE_P9NDD1
    and inverse, to pick up initial pass at P9C DD1 inits

  p9.cxa.scom.initfile
    add CXA_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy

  p9.ddrphy.scom.initfile
    add DDRPHY_P9NDD1_SPY_NAMES to qualify P9N DD1 specific register hierarchy

  p9.dpll.scan.initfile
    remove POSTDD1N_DPLL_SETTINGS feature attribute, use DD1_DPLL_SETTINGS
    attribute and inverse to drive inits

  p9.l2.scan.initfile
    invert definition of OPTIMAL_LARX_STCX_PERF, HW409069 feature attributes

  p9.l3.scan.initfile
  p9.l3.scom.initifle
    remove OPTIMAL_LCO_SCOM, HW396230_SCOM feature attributes
    use HW386657, HW396230 attributes to drive inits

  p9.mca.scom.initfile
    add MCA_P9NDD1_ASYNC to differentiate asynchronous boundary crossing
    programming and dial name differences between P9N DD1, P9N DD2

  p9.mmu.scan.initfile
  p9.mmu.scom.initfile
    invert definition of NMMU_DMT_DD2, NMMU_ISS734_DD2_1 feature attributes

  p9.ncu.scan.initfile
  p9.ncu.scom.initifle
    remove HW396230_SCOM, use HW396230 attribute to drive inits

  p9.npu.scom.initfile
    remove usage of P9N_DD1_SPY_NAMES, refactor CONFIG_ENABLE_PBUS specification
    to work for both P9NDD1, P9NDD2 ENGD

  p9.obus.scan.initfile
    remove EC qualification of OBUS FIR mask for simulation

  sample.ec.scan.initfile
    remove testcase requiring use of P9N_DD1_SPY_NAMES, properties of
    testcase are covered by other tests

  -----------------
  HWP updates:
  -----------------

  p9_xip_customize
    add customization of epsilon attributes for NMMU application

  p9_chiplet_scominit
    invert definition of P9_NDL_IOVALID feature attribute
    remove usage of P9N_DD1_SPY_NAMES

  p9_npu_scominit
    replace usage of P9N_DD1_SPY_NAMES with SETUP_BARS_NPU_DD1_ADDR

  p9_sbe_tracearray
    invert definition of CORE_TRACE_SCOMABLE feature attribute

  p9_sim_get_nia
    remove usage of P9N_DD1_SPY_NAMES, directly process CT/EC attributes
    (ok as this HWP is used for VBU sim only and not consumed by FW)

Change-Id: I63bfe8a4bfb8824b94e35a3688a6c69eecc1cf01
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40911
Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40915
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

4 files changed, 151 insertions, 174 deletions

diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
index 8acd3c72..f1308e10 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mmu_scom.C
@@ -55,8 +55,8 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         fapi2::ATTR_NAME_Type l_chip_id;
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id));
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec));
-        fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2;
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2));
+        fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1_Type l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_NMMU_NDD1, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
         fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1;
@@ -67,11 +67,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c03ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04047C0000000000 );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x04247C0000000000 );
             }
@@ -87,11 +87,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c07ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x409B000000000000 );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 22, 0, uint64_t>(literal_0x40FB000000000000 );
             }
@@ -134,11 +134,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c43ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAF800FF );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x0000FAFC00FB );
             }
@@ -154,11 +154,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x5012c47ull, l_scom_buffer ));
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x910000040F00 );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 48, 16, uint64_t>(literal_0x9D1100000F04 );
             }
@@ -171,11 +171,11 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
             l_scom_buffer.insert<30, 1, 59, uint64_t>(literal_0b11111 );
             l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b11111 );
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x00E );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 l_scom_buffer.insert<0, 12, 52, uint64_t>(literal_0x000 );
             }
@@ -227,12 +227,12 @@ fapi2::ReturnCode p9_mmu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
                 l_scom_buffer.insert<44, 8, 56, uint64_t>(l_NMMU_MM_MPSS_MODE_MPSS_ENA_PREF_PGSZ_ENA_G_64KB_H_64KB );
             }
 
-            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 == literal_0))
+            if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 != literal_0))
             {
                 constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON = 0x1;
                 l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_ON );
             }
-            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 != literal_0))
+            else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_NMMU_NDD1 == literal_0))
             {
                 constexpr auto l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF = 0x0;
                 l_scom_buffer.insert<21, 1, 63, uint64_t>(l_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS_OFF );
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C
index 4f1e4ca6..8502501c 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C
@@ -249,16 +249,16 @@ fapi2::ReturnCode p9_sbe_tracearray(
      * Check an EC feature to see if that's fixed. */
     if (ta_type == fapi2::TARGET_TYPE_CORE)
     {
-        uint8_t l_core_trace_scomable = 0;
+        uint8_t l_core_trace_not_scomable = 0;
 
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> proc_target =
             i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE,
-                               proc_target, l_core_trace_scomable),
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE,
+                               proc_target, l_core_trace_not_scomable),
                  "Failed to query chip EC feature "
-                 "ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE");
+                 "ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE");
 
-        if (!l_core_trace_scomable)
+        if (l_core_trace_not_scomable)
         {
             FAPI_ERR("Core arrays cannot be dumped in this chip EC; "
                      "please use fastarray instead.");
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 0913557b..e6d991be 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -31,11 +31,10 @@
 <attributes>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES</id>
+    <id>ATTR_CHIP_EC_FEATURE_P9_NO_NDL_IOVALID</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Returns true if spy name has changed from dd1 to dd2.
-      Less than Nimbus ec 0x20
+      Returns true if the chip has no NDL IOValid bits
     </description>
     <chipEcFeature>
       <chip>
@@ -49,42 +48,6 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Returns true if spy name has changed from dd1 to dd2.
-      Greater than or equal to 0x20
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_P9_NDL_IOVALID</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Returns true if the chip has NDL IOValid bits
-      P9N dd2
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -102,18 +65,18 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE</id>
+    <id>ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Returns true if the core trace arrays are dumpable via SCOM.
-      Nimbus EC 0x20 or greater
+      Returns true if the core trace arrays are not dumpable via SCOM.
+      Nimbus EC 0x10
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -1690,24 +1653,17 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2</id>
+    <id>ATTR_CHIP_EC_FEATURE_NMMU_NDD1</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Sets inits for DD2, also DMT mode
+      Configure NMMU for Nimbus DD1
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -1748,24 +1704,18 @@
   </attribute>
   <!-- ******************************************************************** -->
     <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_NMMU_ISS734_DD2_1</id>
+    <id>ATTR_CHIP_EC_FEATURE_NMMU_NOT_ISS734</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      issue734 dial, exists dd2.1+
+      NMMU does not require application of issue734 fixes
+      Issue734 exists on Nimbus dd2.1+
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x21</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -2001,7 +1951,7 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW396230_SCAN_ONLY</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW396230</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
       Nimbus DD1 only: set L3/NCU skip group scope via scan only
@@ -2018,30 +1968,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW396230_SCOM</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Nimbus DD2+: able to set L3/NCU skip group scope via SCOM
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW405880_LCO_IN_RETENTION</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2060,10 +1986,10 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCAN_ONLY</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW386657</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Nimbus DD1 only: set the optimal dial setups for LCO's
+      Nimbus DD1 only: set the optimal dial setups for LCO's via scan
     </description>
     <chipEcFeature>
       <chip>
@@ -2077,30 +2003,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCOM</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Nimbus DD2+: set the optimal dial setups for LCO's
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_DISABLE_CP_ME</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -2118,31 +2020,24 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LARX_STCX_PERF</id>
+    <id>ATTR_CHIP_EC_FEATURE_UNTUNED_LARX_STCX_PERF</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Nimbus DD2+: set the optimal dial setups for larx/stcx
+      Nimbus DD1: Larx/stcx dials are non performance tuned
     </description>
     <chipEcFeature>
       <chip>
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW409069</id>
+    <id>ATTR_CHIP_EC_FEATURE_NOT_HW409069</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
       Nimbus DD2+: HW409069 load_larx protection not activated because of dtag_data_resp
@@ -2153,14 +2048,7 @@
         <name>ENUM_ATTR_NAME_NIMBUS</name>
         <ec>
           <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-      <chip>
-        <name>ENUM_ATTR_NAME_CUMULUS</name>
-        <ec>
-          <value>0x10</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
+          <test>LESS_THAN</test>
         </ec>
       </chip>
     </chipEcFeature>
@@ -2839,6 +2727,113 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW391162</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 only: spoof pb_init in cache contained mode
+      Enables L2 checkers to monitor for transactions arbitrating
+      to broadcast onto the fabric
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_SCAN_SICR_TLBIE_QUIESCE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 only: scan ON NCU_TLBIE_QUISCE fence
+      for non-cache contained modes.  Flush state corrected in HW
+      for future revisions
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_CXA_P9NDD1_SPY_NAMES</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Use Nimbus DD1 CXA spy register definition names
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_DDRPHY_P9NDD1_SPY_NAMES</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Use Nimbus DD1 DDR PHY spy register definition names
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Program MCA ECC logic to support Nimbus DD1
+      asynchronus boundary crossing requirements
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_CORE_P9NDD1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 core spy behavior qualifier
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->
   <!-- ******************************************************************** -->
@@ -3215,7 +3210,7 @@
     <id>ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Only MC in Cumulus need to generate scan clock in even cycle instead of odd
+      Cumulus only: MC chiplet requires scan clock in even cycle instead of odd
     </description>
     <chipEcFeature>
       <chip>
@@ -3232,7 +3227,7 @@
     <id>ATTR_CHIP_EC_FEATURE_HW406337</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Cumulus only dropping MC chiplet fence during arrayinit
+      Cumulus only: dropping MC chiplet fence during arrayinit
     </description>
     <chipEcFeature>
       <chip>
@@ -3337,24 +3332,6 @@
   </attribute>
   <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_POSTDD1N_DPLL_SETTINGS</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Post DD1 update : Used for new DD2 settings such as ..._EXTERNAL_JUMP_VALUES latch is new for DD2. True if:
-      Nimbus EC greater than or equal to 20
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>GREATER_THAN_OR_EQUAL</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
-  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_INT_DD1</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index cac558af..e00c1e77 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -326,7 +326,7 @@ attribute tank
 
 <!-- Pervasive EC attributes -->
   <entry>
-           <name>ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE</name>
+           <name>ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE</name>
            <virtual/>
   </entry>
   <entry>
@@ -401,7 +401,7 @@ attribute tank
   </entry>
 
   <entry>
-        <name>ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2</name>
+        <name>ATTR_CHIP_EC_FEATURE_NMMU_NDD1</name>
         <virtual/>
   </entry>
   <entry>