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| author | Raja Das <rajadas2@in.ibm.com> | 2018-03-21 23:29:02 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-08-30 00:29:53 -0500 |
| commit | bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43 (patch) | |
| tree | 42eeda324b9144a80dac924e0dc5977acc5e43bd /src/test/framework/etc/patches | |
| parent | d78d955fd26062f52df6d967a01b6119c10c29d3 (diff) | |
| download | talos-sbe-bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43.tar.gz talos-sbe-bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43.zip | |
[SBE-ARCH1]HRMOR relocated to 4Gb for SPLess Opal system
-removed s0s1 compile time flag
-64MBytes * 64 = 4096MBytes Address
-Updated simics patch to hack the Fspbit to be set, so that for SBE
Jenkins testing, SBE picks up the default 128MB HRMOR.
Change-Id: I77eb5cb018b1f684b4322f23c2b64307bfe1e230
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/56151
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/test/framework/etc/patches')
| -rw-r--r-- | src/test/framework/etc/patches/standalone.simics.patch | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/test/framework/etc/patches/standalone.simics.patch b/src/test/framework/etc/patches/standalone.simics.patch index 99e47749..ccd5be17 100644 --- a/src/test/framework/etc/patches/standalone.simics.patch +++ b/src/test/framework/etc/patches/standalone.simics.patch @@ -1,8 +1,13 @@ -63c63,65 +70c70,77 < ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64 --- -> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "80000000_00000000" 64 +> # Set the Fsp bit in MBOX3 reg (bit 3), This is to make SBE pick default HRMOR +> # i.e. 128MB instead of FspLess HRMOR address. Action files in simics are +> # hardcoded to support 128MB presently. we need to update Simic Action file to +> # be flexible and pick HRMOR basis this Fsp bit. +> # TODO - RTC 196986 +> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "90000000_00000000" 64 > # Set security enabled bit > ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x00050001 "0C000002_00000000" 64 -67a70 +74a82 > ($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x08 "00080000" 32 |
