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authorRaja Das <rajadas2@in.ibm.com>2018-03-21 23:29:02 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2018-08-30 00:29:53 -0500
commitbd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43 (patch)
tree42eeda324b9144a80dac924e0dc5977acc5e43bd
parentd78d955fd26062f52df6d967a01b6119c10c29d3 (diff)
downloadtalos-sbe-bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43.tar.gz
talos-sbe-bd5c4de63cdd033e0c6b2ec55e4ff65c17b8dc43.zip
[SBE-ARCH1]HRMOR relocated to 4Gb for SPLess Opal system
-removed s0s1 compile time flag -64MBytes * 64 = 4096MBytes Address -Updated simics patch to hack the Fspbit to be set, so that for SBE Jenkins testing, SBE picks up the default 128MB HRMOR. Change-Id: I77eb5cb018b1f684b4322f23c2b64307bfe1e230 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/56151 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
-rw-r--r--src/hwpf/target.C28
-rw-r--r--src/test/framework/etc/patches/standalone.simics.patch11
2 files changed, 27 insertions, 12 deletions
diff --git a/src/hwpf/target.C b/src/hwpf/target.C
index 5cfad0dd..fc4a6437 100644
--- a/src/hwpf/target.C
+++ b/src/hwpf/target.C
@@ -60,6 +60,12 @@ extern fapi2attr::CoreAttributes_t* G_core_attributes_ptr;
extern fapi2attr::EQAttributes_t* G_eq_attributes_ptr;
extern fapi2attr::EXAttributes_t* G_ex_attributes_ptr;
+// For PhyP system, HRMOR is set to 128MB, which is multiple of 64MB Granule * 2
+// For OPAL system, it needs the HRMOR in the range of 4GB, so that HB reloading
+// doesn't stamp on the OPAL/HostLinux Data. 64MB Granule * 64 = 4096MB, 64 is
+// the multipler.
+#define HRMOR_FOR_SPLESS_MODE 0x100000000ull //4096 * 1024 * 1024
+
#endif // else __SBEFW_SEEPROM__
namespace fapi2
@@ -105,7 +111,6 @@ extern fapi2::ReturnCode
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chipTarget =
plat_getChipTarget();
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
-
const size_t SCRATCH_PROC_CHIP_MEM_TO_USE_VALID_BIT = 0;
const size_t SCRATCH_PROC_CHIP_MEM_TO_USE_GROUP_ID_STARTBIT = 1;
const size_t SCRATCH_PROC_CHIP_MEM_TO_USE_CHIP_ID_STARTBIT = 4;
@@ -215,22 +220,27 @@ extern fapi2::ReturnCode
if ( l_scratch8Reg.getBit<2>() )
{
- uint8_t l_isMpIpl = 0;
- uint8_t l_isSpMode = 0;
+ uint8_t isMpIpl = 0;
+ uint8_t isSpMode = 0;
FAPI_DBG("Reading Scratch_reg3");
//Getting SCRATCH_REGISTER_3 register value
FAPI_TRY(fapi2::getScom(l_chipTarget, PERV_SCRATCH_REGISTER_3_SCOM,
l_tempReg));
- l_tempReg.extractToRight<2, 1>(l_isMpIpl);
+ l_tempReg.extractToRight<2, 1>(isMpIpl);
FAPI_DBG("Setting up ATTR_IS_MPIPL");
- FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_isMpIpl));
-
- l_tempReg.extractToRight<3, 1>(l_isSpMode);
+ FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, isMpIpl));
- FAPI_DBG("Setting up ATTR_IS_SP_MODE");
- FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_SP_MODE, l_chipTarget, l_isSpMode));
+ l_tempReg.extractToRight<3, 1>(isSpMode);
+ if(!isSpMode)
+ {
+ FAPI_DBG("Set up ATTR_HOSTBOOT_HRMOR_OFFSET in SPless mode");
+ uint64_t hrmor = HRMOR_FOR_SPLESS_MODE;
+ FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET,
+ FAPI_SYSTEM, hrmor));
+ }
+ FAPI_TRY(PLAT_ATTR_INIT(fapi2::ATTR_IS_SP_MODE, l_chipTarget, isSpMode));
l_tempReg.extractToRight<28, 4>(l_riskLvl);
}
diff --git a/src/test/framework/etc/patches/standalone.simics.patch b/src/test/framework/etc/patches/standalone.simics.patch
index 99e47749..ccd5be17 100644
--- a/src/test/framework/etc/patches/standalone.simics.patch
+++ b/src/test/framework/etc/patches/standalone.simics.patch
@@ -1,8 +1,13 @@
-63c63,65
+70c70,77
< ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64
---
-> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "80000000_00000000" 64
+> # Set the Fsp bit in MBOX3 reg (bit 3), This is to make SBE pick default HRMOR
+> # i.e. 128MB instead of FspLess HRMOR address. Action files in simics are
+> # hardcoded to support 128MB presently. we need to update Simic Action file to
+> # be flexible and pick HRMOR basis this Fsp bit.
+> # TODO - RTC 196986
+> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "90000000_00000000" 64
> # Set security enabled bit
> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x00050001 "0C000002_00000000" 64
-67a70
+74a82
> ($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x08 "00080000" 32
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