SBE Quiesce Implementation for FIFO/PSU

Change-Id: I25807d8114ed359347e842e2ca15d64f912865fb
RTC: 149642
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29365
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

7 files changed, 193 insertions, 39 deletions

diff --git a/src/sbefw/sbe_host_intf.H b/src/sbefw/sbe_host_intf.H
index dc9a83ea..a197a432 100644
--- a/src/sbefw/sbe_host_intf.H
+++ b/src/sbefw/sbe_host_intf.H
@@ -51,6 +51,7 @@ enum sbePsuCommandClass
     SBE_PSU_CMD_CLASS_UNKNOWN       = 0,
     SBE_PSU_CMD_CLASS_CORE_STATE    = 0xD1,
     SBE_PSU_CMD_CLASS_RING_ACCESS   = 0xD3,
+    SBE_PSU_CMD_CLASS_GENERIC       = 0xD7,
  };
 
 /**
@@ -72,6 +73,15 @@ enum sbePsuRingAccessMessages
 };
 
 /**
+ * @brief enums for SBE-Host interface for generic commands
+ */
+enum sbePsuGenericMessages
+{
+    SBE_PSU_GENERIC_MSG_QUIESCE     = 0x05,
+    SBE_PSU_GENERIC_MSG_UNKNOWN     = 0xFF,
+};
+
+/**
   * @brief enums denoting control flags
   *
   */
diff --git a/src/sbefw/sbe_sp_intf.H b/src/sbefw/sbe_sp_intf.H
index 93a05148..b983b307 100644
--- a/src/sbefw/sbe_sp_intf.H
+++ b/src/sbefw/sbe_sp_intf.H
@@ -161,6 +161,7 @@ enum sbeGenericMessageCommands
     SBE_CMD_GET_SBE_CAPABILITIES  = 0x02, /* GET SBE capabilities */
     SBE_CMD_GET_FREQ_SUPPORTED    = 0x03, /* Get Supported frequencies */
     SBE_CMD_ABORT                 = 0x05, /* Sbe Abort */
+    SBE_CMD_QUIESCE               = 0x06, /* Sbe Quiesce */
 };
 
 enum sbeMpIplCommands
@@ -263,7 +264,7 @@ enum
     GET_SRAM_OCC_SUPPPORTED             = 0xA4000004,
     PUT_SRAM_OCC_SUPPPORTED             = 0xA4000008,
     GET_SRAM_CME_SUPPPORTED             = 0xA4000010,
-    PUT_SRAM_CME_SUPPPORTED             = 0xA4000011,
+    PUT_SRAM_CME_SUPPPORTED             = 0xA4000020,
     GET_REGISTER_SUPPPORTED             = 0xA5000001,
     PUT_REGISTER_SUPPPORTED             = 0xA5000002,
     READ_FAST_ARRAY_SUPPPORTED          = 0xA6000001,
@@ -274,6 +275,7 @@ enum
     GET_SBE_CAPABILITIES_SUPPPORTED     = 0xA8000002,
     GET_SBE_FREQUENCIES_SUPPPORTED      = 0xA8000004,
     GET_SBE_STATE_SUPPPORTED            = 0xA8000008,
+    SBE_QUIESCE                         = 0xA8000010,
 };
 
 /**
diff --git a/src/sbefw/sbecmdgeneric.C b/src/sbefw/sbecmdgeneric.C
index c45a70a6..7ec6d2db 100644
--- a/src/sbefw/sbecmdgeneric.C
+++ b/src/sbefw/sbecmdgeneric.C
@@ -36,6 +36,11 @@
 #include "sbe_build_info.H"
 #include "sbeFifoMsgUtils.H"
 #include "sbeFFDC.H"
+#include "sberegaccess.H"
+#include "sbestates.H"
+#include "sbeHostMsg.H"
+#include "sbeHostUtils.H"
+
 
 // Forward declaration
 sbeCapabilityRespMsg::sbeCapabilityRespMsg()
@@ -62,7 +67,8 @@ sbeCapabilityRespMsg::sbeCapabilityRespMsg()
 
     capability[GENERIC_CHIPOP_CAPABILITY_START_IDX] =
                                 GET_SBE_FFDC_SUPPPORTED |
-                                GET_SBE_CAPABILITIES_SUPPPORTED;
+                                GET_SBE_CAPABILITIES_SUPPPORTED|
+                                SBE_QUIESCE;
 
     capability[MEMORY_CAPABILITY_START_IDX] =
                                 GET_MEMORY_SUPPPORTED |
@@ -72,6 +78,7 @@ sbeCapabilityRespMsg::sbeCapabilityRespMsg()
 
     capability[INSTRUCTION_CTRL_CAPABILITY_START_IDX] =
                                 CONTROL_INSTRUCTIONS_SUPPPORTED;
+
     capability[REGISTER_CAPABILITY_START_IDX] =
                                 GET_REGISTER_SUPPPORTED |
                                 PUT_REGISTER_SUPPPORTED ;
@@ -169,3 +176,81 @@ uint32_t sbeGetFfdc (uint8_t *i_pArg)
     return rc;
     #undef SBE_FUNC
 }
+
+//----------------------------------------------------------------------------
+uint32_t sbeFifoQuiesce( uint8_t *i_pArg )
+{
+    #define SBE_FUNC "sbeFifoQuiesce"
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
+    uint32_t len = 0;
+    sbeRespGenHdr_t respHdr;
+    respHdr.init();
+
+    do
+    {
+        // Dequeue the EOT entry as no more data is expected.
+        rc = sbeUpFifoDeq_mult (len, NULL);
+        CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(rc);
+
+        // Set Quiesce State
+        (void)SbeRegAccess::theSbeRegAccess().stateTransition(
+                                          SBE_QUIESCE_EVENT);
+
+        rc = sbeDsSendRespHdr(respHdr);
+        if(rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            SBE_ERROR(SBE_FUNC "sbeDsSendRespHdr failed");
+            // Not Breaking here since we can't revert back on the set state
+        }
+    }while(0);
+
+    if( rc )
+    {
+        SBE_ERROR( SBE_FUNC"Failed. rc[0x%X]", rc);
+    }
+    return rc;
+    #undef SBE_FUNC
+}
+
+//----------------------------------------------------------------------------
+uint32_t sbePsuQuiesce( uint8_t *i_pArg )
+{
+    #define SBE_FUNC "sbePsuQuiesce"
+    uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL;
+
+    do
+    {
+        // Send Ack to Host via SBE_SBE2PSU_DOORBELL_SET_BIT1
+        // This util method will check internally on the mbox0 register if
+        // ACK is requested.
+        rc = sbeAcknowledgeHost();
+        if (rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            SBE_ERROR(SBE_FUNC " Failed to Sent Ack to Host over "
+                "SBE_SBE2PSU_DOORBELL_SET_BIT1");
+            break;
+        }
+
+        // Set Quiesce State
+        (void)SbeRegAccess::theSbeRegAccess().stateTransition(
+                                          SBE_QUIESCE_EVENT);
+
+        rc = sbeWriteSbe2PsuMbxReg(SBE_HOST_PSU_MBOX_REG4,
+                         (uint64_t*)(&g_sbeSbe2PsuRespHdr),
+                         (sizeof(g_sbeSbe2PsuRespHdr)/sizeof(uint64_t)),
+                         true);
+        if(rc != SBE_SEC_OPERATION_SUCCESSFUL)
+        {
+            SBE_ERROR(SBE_FUNC" Failed to write SBE_HOST_PSU_MBOX_REG4");
+            // Not Breaking here since we can't revert back on the set state
+        }
+    }while(0);
+
+    if( rc )
+    {
+        SBE_ERROR( SBE_FUNC"Failed. rc[0x%X]", rc);
+    }
+    return rc;
+    #undef SBE_FUNC
+}
+
diff --git a/src/sbefw/sbecmdgeneric.H b/src/sbefw/sbecmdgeneric.H
index 451731ab..8b5cd385 100644
--- a/src/sbefw/sbecmdgeneric.H
+++ b/src/sbefw/sbecmdgeneric.H
@@ -52,4 +52,22 @@ uint32_t sbeGetFfdc(uint8_t *i_pArg);
   */
 uint32_t sbeGetCapabilities(uint8_t *i_pArg);
 
+/**
+  * @brief SBE Fifo Quiesce (0xA806)
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the FIFO access utility
+  */
+uint32_t sbeFifoQuiesce(uint8_t *i_pArg);
+
+/**
+  * @brief SBE Psu Quiesce (0xD705)
+  *
+  * @param[in] i_pArg Buffer to be passed to the function (not used as of now)
+  *
+  * @return    Rc from the Psu access utility
+  */
+uint32_t sbePsuQuiesce(uint8_t *i_pArg);
+
 #endif // __SBEFW_SBECMDGENERIC_H
diff --git a/src/sbefw/sbecmdparser.C b/src/sbefw/sbecmdparser.C
index b3398f40..856a45f5 100644
--- a/src/sbefw/sbecmdparser.C
+++ b/src/sbefw/sbecmdparser.C
@@ -49,8 +49,7 @@
 
 // Declaration
 static const uint16_t HARDWARE_FENCED_STATE =
-     SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE|
-     SBE_FENCE_AT_DMT;
+     SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_DMT;
 
 static const uint16_t PUT_HARDWARE_FENCED_STATE =
      HARDWARE_FENCED_STATE|SBE_FENCE_AT_MPIPL;
@@ -62,23 +61,23 @@ static sbeCmdStruct_t g_sbeScomCmdArray [] =
 {
     {sbeGetScom,
      SBE_CMD_GETSCOM,
-     HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
     {sbePutScom,
      SBE_CMD_PUTSCOM,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
     {sbeModifyScom,
      SBE_CMD_MODIFYSCOM,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
     {sbePutScomUnderMask,
      SBE_CMD_PUTSCOM_MASK,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
     {sbeMultiScom,
      SBE_CMD_MULTISCOM,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
 };
 
@@ -91,7 +90,7 @@ static sbeCmdStruct_t g_sbeIplControlCmdArray [] =
     {sbeHandleIstep,
      SBE_CMD_EXECUTE_ISTEP,
      PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_RUNTIME|
-     SBE_FENCE_AT_DUMPING,
+     SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_QUIESCE,
      // This is allowed in FFDC Collect state
      // TODO - Issue 157287 - Allow MPIIPL in Isteps state
     },
@@ -99,7 +98,8 @@ static sbeCmdStruct_t g_sbeIplControlCmdArray [] =
     {sbeContinueBoot,
      SBE_CMD_CONTINUE_BOOT,
      PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_RUNTIME|
-     SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ISTEP,
+     SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ISTEP|
+     SBE_FENCE_AT_QUIESCE,
      // This is allowed only in FFDC Collect State in PLCK mode
     },
 };
@@ -112,7 +112,7 @@ static sbeCmdStruct_t g_sbeGenericCmdArray [] =
 {
     {sbeGetCapabilities,
      SBE_CMD_GET_SBE_CAPABILITIES,
-     SBE_STATE_FFDC_COLLECT,
+     SBE_FENCE_AT_FFDC_COLLECT,
      // Fence in FFDC Collect State, since it might over-write traces
     },
 
@@ -120,6 +120,11 @@ static sbeCmdStruct_t g_sbeGenericCmdArray [] =
       SBE_CMD_GET_SBE_FFDC,
       SBE_NO_FENCE,
      },
+
+    {sbeFifoQuiesce,
+     SBE_CMD_QUIESCE,
+     SBE_NO_FENCE,
+    },
 };
 
 //////////////////////////////////////////////////////////////
@@ -130,22 +135,24 @@ static sbeCmdStruct_t g_sbeMemoryAccessCmdArray [] =
 {
     {sbeGetMem,
      SBE_CMD_GETMEM,
-     HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
 
     {sbePutMem,
      SBE_CMD_PUTMEM,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
 
     {sbeGetOccSram,
      SBE_CMD_GETSRAM_OCC,
-     HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT|
+     SBE_FENCE_AT_QUIESCE,
     },
 
     {sbePutOccSram,
      SBE_CMD_PUTSRAM_OCC,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT|
+     SBE_FENCE_AT_QUIESCE,
     },
 };
 
@@ -157,7 +164,7 @@ static sbeCmdStruct_t g_sbeInstructionCntlCmdArray[] =
 {
     {sbeCntlInst,
      SBE_CMD_CONTROL_INSTRUCTIONS,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT,
     },
 };
 
@@ -169,12 +176,14 @@ static sbeCmdStruct_t g_sbeRegAccessCmdArray [] =
 {
     {sbeGetReg,
      SBE_CMD_GETREG,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT|
+     SBE_FENCE_AT_QUIESCE,
     },
 
     {sbePutReg,
      SBE_CMD_PUTREG,
-     PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT,
+     PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT|
+     SBE_FENCE_AT_QUIESCE,
     },
 };
 
@@ -187,7 +196,8 @@ static sbeCmdStruct_t g_sbeMpiplCmdArray[] =
     {sbeEnterMpipl,
      SBE_CMD_MPIPL_ENTER,
      PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_ISTEP|
-     SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ABORT,
+     SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ABORT|
+     SBE_FENCE_AT_QUIESCE,
      // Allow Fspless system to enter MPIPL
      // Honour MPIPL at FFDC Collect state
      // Issue 157287
@@ -197,7 +207,8 @@ static sbeCmdStruct_t g_sbeMpiplCmdArray[] =
      SBE_CMD_MPIPL_CONTINUE,
      HARDWARE_FENCED_STATE|SBE_FENCE_AT_ISTEP|
      SBE_FENCE_AT_RUNTIME|SBE_FENCE_AT_DUMPING|
-     SBE_FENCE_AT_ABORT|SBE_FENCE_AT_FFDC_COLLECT,
+     SBE_FENCE_AT_ABORT|SBE_FENCE_AT_FFDC_COLLECT|
+     SBE_FENCE_AT_QUIESCE,
      // Only allowed State is MPIPL
     },
 };
@@ -210,7 +221,7 @@ static sbeCmdStruct_t g_sbeRingAccessCmdArray [] =
 {
     {sbeGetRing,
      SBE_CMD_GETRING,
-     SBE_FENCE_AT_CONTINUOUS_IPL,
+     SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE,
     },
 };
 
@@ -225,7 +236,7 @@ static sbeCmdStruct_t g_sbeCoreStateControlCmdArray [] =
      SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE|
      SBE_FENCE_AT_MPIPL|SBE_FENCE_AT_ISTEP|
      SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ABORT|
-     SBE_FENCE_AT_FFDC_COLLECT,
+     SBE_FENCE_AT_FFDC_COLLECT|SBE_FENCE_AT_QUIESCE,
     },
 };
 
@@ -237,10 +248,21 @@ static sbeCmdStruct_t g_sbePutRingFromImageCmdArray [] =
 {
     {sbePutRingFromImagePSU,
      SBE_PSU_MSG_PUT_RING_FROM_IMAGE,
-     SBE_FENCE_AT_CONTINUOUS_IPL,
+     SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE,
     },
 };
 
+//////////////////////////////////////////////////////////////
+// @brief g_sbePsuGenericCmdArray
+//
+//////////////////////////////////////////////////////////////
+static sbeCmdStruct_t g_sbePsuGenericCmdArray[] =
+{
+    {sbePsuQuiesce,
+     SBE_PSU_GENERIC_MSG_QUIESCE,
+     SBE_NO_FENCE,
+    },
+};
 
 ////////////////////////////////////////////////////////////////
 ////////////////////////////////////////////////////////////////
@@ -315,6 +337,12 @@ uint8_t sbeGetCmdStructAttr (const uint8_t  i_cmdClass,
             *o_ppCmd  = (sbeCmdStruct_t*)g_sbePutRingFromImageCmdArray;
             break;
 
+        case  SBE_PSU_CMD_CLASS_GENERIC:
+            l_numCmds = sizeof(g_sbePsuGenericCmdArray) /
+                        sizeof(sbeCmdStruct_t);
+            *o_ppCmd  = (sbeCmdStruct_t*)g_sbePsuGenericCmdArray;
+            break;
+
         // This will grow with each class of chipOp in future
         default:
                 break;
@@ -392,13 +420,18 @@ bool sbeIsCmdAllowedAtState (const uint8_t i_cmdClass,
 
             switch(l_state)
             {
-                case SBE_STATE_QUIESCE:
                 case SBE_STATE_UNKNOWN:
                 case SBE_STATE_FAILURE:
                     // All operations are fenced here, return false
                     // Reset is the only Option available
                     break;
 
+                case SBE_STATE_QUIESCE:
+                {
+                    l_ret = ((l_pCmd->cmd_state_fence &
+                             SBE_FENCE_AT_QUIESCE)? false:true);
+                    break;
+                }
                 case SBE_STATE_FFDC_COLLECT:
                 {
                     l_ret = ((l_pCmd->cmd_state_fence &
diff --git a/src/sbefw/sbeevents.H b/src/sbefw/sbeevents.H
index 1b085922..233bc6ad 100644
--- a/src/sbefw/sbeevents.H
+++ b/src/sbefw/sbeevents.H
@@ -52,6 +52,7 @@ enum sbeEvent
     SBE_DMT_COMP_EVENT                     = 0xA, // From DMT State
     SBE_FAILURE_EVENT                      = 0xB, // From Any State
     SBE_FFDC_COLLECT_EVENT                 = 0xC, // From Unknown State
+    SBE_QUIESCE_EVENT                      = 0xD, // From Any State
 };
 
 // Maximum number of Events per State
@@ -59,18 +60,18 @@ enum maxEventPerState
 {
     SBE_STATE_UNKNOWN_MAX_EVENT = 5,
     SBE_STATE_FFDC_COLLECT_MAX_EVENT = 4,
-    SBE_STATE_IPLING_MAX_EVENT = 4,
-    SBE_STATE_ISTEP_MAX_EVENT = 3,
-    SBE_STATE_RUNTIME_MAX_EVENT = 4,
-    SBE_STATE_MPIPL_MAX_EVENT = 2,
-    SBE_STATE_DMT_MAX_EVENT = 1,
+    SBE_STATE_IPLING_MAX_EVENT = 5,
+    SBE_STATE_ISTEP_MAX_EVENT = 4,
+    SBE_STATE_RUNTIME_MAX_EVENT = 5,
+    SBE_STATE_MPIPL_MAX_EVENT = 3,
+    SBE_STATE_DMT_MAX_EVENT = 2,
     SBE_STATE_DUMP_MAX_EVENT = 0,
     SBE_STATE_FAILURE_MAX_EVENT = 0,
     SBE_STATE_QUIESCE_MAX_EVENT = 0,
     SBE_STATE_ABORT_MAX_EVENT = 0,
 
     // Total number of State Transition Events, Addition of all the above
-    SBE_MAX_TRANSITIONS = 23,
+    SBE_MAX_TRANSITIONS = 28,
 };
 
 
@@ -83,14 +84,14 @@ enum entryToStateMap
     SBE_STATE_UNKNOWN_ENTRY_TO_MAP = 0,
     SBE_STATE_FFDC_COLLECT_ENTRY_TO_MAP = SBE_STATE_UNKNOWN_ENTRY_TO_MAP + SBE_STATE_UNKNOWN_MAX_EVENT, // 5
     SBE_STATE_IPLING_ENTRY_TO_MAP = SBE_STATE_FFDC_COLLECT_ENTRY_TO_MAP + SBE_STATE_FFDC_COLLECT_MAX_EVENT, //9
-    SBE_STATE_ISTEP_ENTRY_TO_MAP = SBE_STATE_IPLING_ENTRY_TO_MAP + SBE_STATE_IPLING_MAX_EVENT, //13
-    SBE_STATE_RUNTIME_ENTRY_TO_MAP = SBE_STATE_ISTEP_ENTRY_TO_MAP + SBE_STATE_ISTEP_MAX_EVENT, //16
-    SBE_STATE_MPIPL_ENTRY_TO_MAP = SBE_STATE_RUNTIME_ENTRY_TO_MAP + SBE_STATE_RUNTIME_MAX_EVENT, //20
-    SBE_STATE_DMT_ENTRY_TO_MAP = SBE_STATE_MPIPL_ENTRY_TO_MAP + SBE_STATE_MPIPL_MAX_EVENT, //22
-    SBE_STATE_DUMP_ENTRY_TO_MAP = SBE_STATE_DMT_ENTRY_TO_MAP + SBE_STATE_DMT_MAX_EVENT, //23
-    SBE_STATE_FAILURE_ENTRY_TO_MAP = SBE_STATE_DUMP_ENTRY_TO_MAP + SBE_STATE_DUMP_MAX_EVENT, //23
-    SBE_STATE_QUIESCE_ENTRY_TO_MAP = SBE_STATE_FAILURE_ENTRY_TO_MAP + SBE_STATE_FAILURE_MAX_EVENT, //23
-    SBE_STATE_ABORT_ENTRY_TO_MAP = SBE_STATE_QUIESCE_ENTRY_TO_MAP + SBE_STATE_QUIESCE_MAX_EVENT, //23
+    SBE_STATE_ISTEP_ENTRY_TO_MAP = SBE_STATE_IPLING_ENTRY_TO_MAP + SBE_STATE_IPLING_MAX_EVENT, //14
+    SBE_STATE_RUNTIME_ENTRY_TO_MAP = SBE_STATE_ISTEP_ENTRY_TO_MAP + SBE_STATE_ISTEP_MAX_EVENT, //18
+    SBE_STATE_MPIPL_ENTRY_TO_MAP = SBE_STATE_RUNTIME_ENTRY_TO_MAP + SBE_STATE_RUNTIME_MAX_EVENT, //23
+    SBE_STATE_DMT_ENTRY_TO_MAP = SBE_STATE_MPIPL_ENTRY_TO_MAP + SBE_STATE_MPIPL_MAX_EVENT, //26
+    SBE_STATE_DUMP_ENTRY_TO_MAP = SBE_STATE_DMT_ENTRY_TO_MAP + SBE_STATE_DMT_MAX_EVENT, //28
+    SBE_STATE_FAILURE_ENTRY_TO_MAP = SBE_STATE_DUMP_ENTRY_TO_MAP + SBE_STATE_DUMP_MAX_EVENT, //28
+    SBE_STATE_QUIESCE_ENTRY_TO_MAP = SBE_STATE_FAILURE_ENTRY_TO_MAP + SBE_STATE_FAILURE_MAX_EVENT, //28
+    SBE_STATE_ABORT_ENTRY_TO_MAP = SBE_STATE_QUIESCE_ENTRY_TO_MAP + SBE_STATE_QUIESCE_MAX_EVENT, //28
 };
 
 #endif //__SBEFW_SBEEVENTS_H
diff --git a/src/sbefw/sberegaccess.C b/src/sbefw/sberegaccess.C
index 1e6067d5..2fa26c5e 100644
--- a/src/sbefw/sberegaccess.C
+++ b/src/sbefw/sberegaccess.C
@@ -88,16 +88,21 @@ static const stateTransitionStr_t stateTransMap[SBE_MAX_TRANSITIONS] = {
     {SBE_STATE_IPLING, SBE_DUMP_FAILURE_EVENT, SBE_STATE_DUMP},
     {SBE_STATE_IPLING, SBE_FAILURE_EVENT, SBE_STATE_FAILURE},
     {SBE_STATE_IPLING, SBE_ABORT_EVENT, SBE_STATE_ABORT},
+    {SBE_STATE_IPLING, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE},
     {SBE_STATE_ISTEP, SBE_RUNTIME_EVENT, SBE_STATE_RUNTIME},
     {SBE_STATE_ISTEP, SBE_ABORT_EVENT, SBE_STATE_ABORT},
     {SBE_STATE_ISTEP, SBE_FAILURE_EVENT, SBE_STATE_FAILURE},
+    {SBE_STATE_ISTEP, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE},
     {SBE_STATE_RUNTIME, SBE_DUMP_FAILURE_EVENT, SBE_STATE_DUMP},
     {SBE_STATE_RUNTIME, SBE_ENTER_MPIPL_EVENT, SBE_STATE_MPIPL},
     {SBE_STATE_RUNTIME, SBE_DMT_ENTER_EVENT, SBE_STATE_DMT},
     {SBE_STATE_RUNTIME, SBE_FAILURE_EVENT, SBE_STATE_FAILURE},
+    {SBE_STATE_RUNTIME, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE},
     {SBE_STATE_MPIPL, SBE_CONTINUE_MPIPL_EVENT, SBE_STATE_RUNTIME},
     {SBE_STATE_MPIPL, SBE_DUMP_FAILURE_EVENT, SBE_STATE_DUMP},
+    {SBE_STATE_MPIPL, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE},
     {SBE_STATE_DMT, SBE_DMT_COMP_EVENT, SBE_STATE_RUNTIME},
+    {SBE_STATE_DMT, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE},
 };
 
 /**