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author | Raja Das <rajadas2@in.ibm.com> | 2016-09-08 03:49:46 -0500 |
---|---|---|
committer | AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> | 2016-09-30 06:36:43 -0400 |
commit | e34f7c585774440c9e02879993c59bcf08723a9b (patch) | |
tree | bfca5b61468de3fe824f77cb1d5a457a02675f15 /src | |
parent | d203132a331691e653aee54b339453b391b5e7a0 (diff) | |
download | talos-sbe-e34f7c585774440c9e02879993c59bcf08723a9b.tar.gz talos-sbe-e34f7c585774440c9e02879993c59bcf08723a9b.zip |
SBE Quiesce Implementation for FIFO/PSU
Change-Id: I25807d8114ed359347e842e2ca15d64f912865fb
RTC: 149642
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29365
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk | 7 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/Makefile | 2 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/nestfiles.mk | 5 | ||||
-rw-r--r-- | src/sbefw/sbe_host_intf.H | 10 | ||||
-rw-r--r-- | src/sbefw/sbe_sp_intf.H | 4 | ||||
-rw-r--r-- | src/sbefw/sbecmdgeneric.C | 87 | ||||
-rw-r--r-- | src/sbefw/sbecmdgeneric.H | 18 | ||||
-rw-r--r-- | src/sbefw/sbecmdparser.C | 79 | ||||
-rw-r--r-- | src/sbefw/sbeevents.H | 29 | ||||
-rw-r--r-- | src/sbefw/sberegaccess.C | 5 | ||||
-rwxr-xr-x | src/test/testcases/test.xml | 1 | ||||
-rwxr-xr-x | src/test/testcases/testGetCapabilities.py | 2 | ||||
-rwxr-xr-x | src/test/testcases/testQuiesce.py | 57 | ||||
-rw-r--r-- | src/test/testcases/testQuiesce.xml | 45 |
14 files changed, 308 insertions, 43 deletions
diff --git a/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk index 69b681fb..feb937d5 100644 --- a/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk +++ b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk @@ -44,8 +44,11 @@ CORE-CPP-SOURCES += p9_hcd_core_runinit.C CORE-CPP-SOURCES += p9_hcd_core_scomcust.C CORE-CPP-SOURCES += p9_hcd_core_scominit.C CORE-CPP-SOURCES += p9_hcd_core_startclocks.C -CORE-CPP-SOURCES += p9_thread_control.C -CORE-CPP-SOURCES += p9_sbe_instruct_start.C +# TODO via RTC 152424 +# thread control procedure is in core directory, but this procedure needs to be +# in PIBMEM for quiesce case, So compiling in nest makefile +#CORE-CPP-SOURCES += p9_thread_control.C +#CORE-CPP-SOURCES += p9_sbe_instruct_start.C CORE-C-SOURCES += CORE-S-SOURCES += diff --git a/src/import/chips/p9/procedures/hwp/nest/Makefile b/src/import/chips/p9/procedures/hwp/nest/Makefile index 24976437..d774f604 100644 --- a/src/import/chips/p9/procedures/hwp/nest/Makefile +++ b/src/import/chips/p9/procedures/hwp/nest/Makefile @@ -36,7 +36,7 @@ include nestfiles.mk # Adding VPATH as there are few procedures which are in # perv folder but we are compiling them here. Refer to # nestfiles.mk for details. -export VPATH = $(PERV_SRCDIR):$(NEST_SRCDIR) +export VPATH = $(PERV_SRCDIR):$(CORE_SRCDIR):$(NEST_SRCDIR) OBJS := $(addprefix $(OBJDIR)/, $(NEST_OBJECTS)) libnest.a: nest diff --git a/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk b/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk index 847d6015..d9360a39 100644 --- a/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk +++ b/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk @@ -51,6 +51,11 @@ NEST-CPP-SOURCES +=p9_ram_core.C # be executed from PIBMEM. So compiling these is nest makefile. NEST-CPP-SOURCES +=p9_sbe_gear_switcher.C NEST-CPP-SOURCES +=p9_sbe_tp_switch_gears.C +# TODO via RTC 152424 +# thread control procedure is in core directory, but this procedure needs to be +# in PIBMEM for quiesce case, So compiling in nest makefile +NEST-CPP-SOURCES +=p9_thread_control.C +NEST-CPP-SOURCES +=p9_sbe_instruct_start.C NEST-C-SOURCES = NEST-S-SOURCES = diff --git a/src/sbefw/sbe_host_intf.H b/src/sbefw/sbe_host_intf.H index dc9a83ea..a197a432 100644 --- a/src/sbefw/sbe_host_intf.H +++ b/src/sbefw/sbe_host_intf.H @@ -51,6 +51,7 @@ enum sbePsuCommandClass SBE_PSU_CMD_CLASS_UNKNOWN = 0, SBE_PSU_CMD_CLASS_CORE_STATE = 0xD1, SBE_PSU_CMD_CLASS_RING_ACCESS = 0xD3, + SBE_PSU_CMD_CLASS_GENERIC = 0xD7, }; /** @@ -72,6 +73,15 @@ enum sbePsuRingAccessMessages }; /** + * @brief enums for SBE-Host interface for generic commands + */ +enum sbePsuGenericMessages +{ + SBE_PSU_GENERIC_MSG_QUIESCE = 0x05, + SBE_PSU_GENERIC_MSG_UNKNOWN = 0xFF, +}; + +/** * @brief enums denoting control flags * */ diff --git a/src/sbefw/sbe_sp_intf.H b/src/sbefw/sbe_sp_intf.H index 93a05148..b983b307 100644 --- a/src/sbefw/sbe_sp_intf.H +++ b/src/sbefw/sbe_sp_intf.H @@ -161,6 +161,7 @@ enum sbeGenericMessageCommands SBE_CMD_GET_SBE_CAPABILITIES = 0x02, /* GET SBE capabilities */ SBE_CMD_GET_FREQ_SUPPORTED = 0x03, /* Get Supported frequencies */ SBE_CMD_ABORT = 0x05, /* Sbe Abort */ + SBE_CMD_QUIESCE = 0x06, /* Sbe Quiesce */ }; enum sbeMpIplCommands @@ -263,7 +264,7 @@ enum GET_SRAM_OCC_SUPPPORTED = 0xA4000004, PUT_SRAM_OCC_SUPPPORTED = 0xA4000008, GET_SRAM_CME_SUPPPORTED = 0xA4000010, - PUT_SRAM_CME_SUPPPORTED = 0xA4000011, + PUT_SRAM_CME_SUPPPORTED = 0xA4000020, GET_REGISTER_SUPPPORTED = 0xA5000001, PUT_REGISTER_SUPPPORTED = 0xA5000002, READ_FAST_ARRAY_SUPPPORTED = 0xA6000001, @@ -274,6 +275,7 @@ enum GET_SBE_CAPABILITIES_SUPPPORTED = 0xA8000002, GET_SBE_FREQUENCIES_SUPPPORTED = 0xA8000004, GET_SBE_STATE_SUPPPORTED = 0xA8000008, + SBE_QUIESCE = 0xA8000010, }; /** diff --git a/src/sbefw/sbecmdgeneric.C b/src/sbefw/sbecmdgeneric.C index c45a70a6..7ec6d2db 100644 --- a/src/sbefw/sbecmdgeneric.C +++ b/src/sbefw/sbecmdgeneric.C @@ -36,6 +36,11 @@ #include "sbe_build_info.H" #include "sbeFifoMsgUtils.H" #include "sbeFFDC.H" +#include "sberegaccess.H" +#include "sbestates.H" +#include "sbeHostMsg.H" +#include "sbeHostUtils.H" + // Forward declaration sbeCapabilityRespMsg::sbeCapabilityRespMsg() @@ -62,7 +67,8 @@ sbeCapabilityRespMsg::sbeCapabilityRespMsg() capability[GENERIC_CHIPOP_CAPABILITY_START_IDX] = GET_SBE_FFDC_SUPPPORTED | - GET_SBE_CAPABILITIES_SUPPPORTED; + GET_SBE_CAPABILITIES_SUPPPORTED| + SBE_QUIESCE; capability[MEMORY_CAPABILITY_START_IDX] = GET_MEMORY_SUPPPORTED | @@ -72,6 +78,7 @@ sbeCapabilityRespMsg::sbeCapabilityRespMsg() capability[INSTRUCTION_CTRL_CAPABILITY_START_IDX] = CONTROL_INSTRUCTIONS_SUPPPORTED; + capability[REGISTER_CAPABILITY_START_IDX] = GET_REGISTER_SUPPPORTED | PUT_REGISTER_SUPPPORTED ; @@ -169,3 +176,81 @@ uint32_t sbeGetFfdc (uint8_t *i_pArg) return rc; #undef SBE_FUNC } + +//---------------------------------------------------------------------------- +uint32_t sbeFifoQuiesce( uint8_t *i_pArg ) +{ + #define SBE_FUNC "sbeFifoQuiesce" + uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL; + uint32_t len = 0; + sbeRespGenHdr_t respHdr; + respHdr.init(); + + do + { + // Dequeue the EOT entry as no more data is expected. + rc = sbeUpFifoDeq_mult (len, NULL); + CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(rc); + + // Set Quiesce State + (void)SbeRegAccess::theSbeRegAccess().stateTransition( + SBE_QUIESCE_EVENT); + + rc = sbeDsSendRespHdr(respHdr); + if(rc != SBE_SEC_OPERATION_SUCCESSFUL) + { + SBE_ERROR(SBE_FUNC "sbeDsSendRespHdr failed"); + // Not Breaking here since we can't revert back on the set state + } + }while(0); + + if( rc ) + { + SBE_ERROR( SBE_FUNC"Failed. rc[0x%X]", rc); + } + return rc; + #undef SBE_FUNC +} + +//---------------------------------------------------------------------------- +uint32_t sbePsuQuiesce( uint8_t *i_pArg ) +{ + #define SBE_FUNC "sbePsuQuiesce" + uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL; + + do + { + // Send Ack to Host via SBE_SBE2PSU_DOORBELL_SET_BIT1 + // This util method will check internally on the mbox0 register if + // ACK is requested. + rc = sbeAcknowledgeHost(); + if (rc != SBE_SEC_OPERATION_SUCCESSFUL) + { + SBE_ERROR(SBE_FUNC " Failed to Sent Ack to Host over " + "SBE_SBE2PSU_DOORBELL_SET_BIT1"); + break; + } + + // Set Quiesce State + (void)SbeRegAccess::theSbeRegAccess().stateTransition( + SBE_QUIESCE_EVENT); + + rc = sbeWriteSbe2PsuMbxReg(SBE_HOST_PSU_MBOX_REG4, + (uint64_t*)(&g_sbeSbe2PsuRespHdr), + (sizeof(g_sbeSbe2PsuRespHdr)/sizeof(uint64_t)), + true); + if(rc != SBE_SEC_OPERATION_SUCCESSFUL) + { + SBE_ERROR(SBE_FUNC" Failed to write SBE_HOST_PSU_MBOX_REG4"); + // Not Breaking here since we can't revert back on the set state + } + }while(0); + + if( rc ) + { + SBE_ERROR( SBE_FUNC"Failed. rc[0x%X]", rc); + } + return rc; + #undef SBE_FUNC +} + diff --git a/src/sbefw/sbecmdgeneric.H b/src/sbefw/sbecmdgeneric.H index 451731ab..8b5cd385 100644 --- a/src/sbefw/sbecmdgeneric.H +++ b/src/sbefw/sbecmdgeneric.H @@ -52,4 +52,22 @@ uint32_t sbeGetFfdc(uint8_t *i_pArg); */ uint32_t sbeGetCapabilities(uint8_t *i_pArg); +/** + * @brief SBE Fifo Quiesce (0xA806) + * + * @param[in] i_pArg Buffer to be passed to the function (not used as of now) + * + * @return Rc from the FIFO access utility + */ +uint32_t sbeFifoQuiesce(uint8_t *i_pArg); + +/** + * @brief SBE Psu Quiesce (0xD705) + * + * @param[in] i_pArg Buffer to be passed to the function (not used as of now) + * + * @return Rc from the Psu access utility + */ +uint32_t sbePsuQuiesce(uint8_t *i_pArg); + #endif // __SBEFW_SBECMDGENERIC_H diff --git a/src/sbefw/sbecmdparser.C b/src/sbefw/sbecmdparser.C index b3398f40..856a45f5 100644 --- a/src/sbefw/sbecmdparser.C +++ b/src/sbefw/sbecmdparser.C @@ -49,8 +49,7 @@ // Declaration static const uint16_t HARDWARE_FENCED_STATE = - SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE| - SBE_FENCE_AT_DMT; + SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_DMT; static const uint16_t PUT_HARDWARE_FENCED_STATE = HARDWARE_FENCED_STATE|SBE_FENCE_AT_MPIPL; @@ -62,23 +61,23 @@ static sbeCmdStruct_t g_sbeScomCmdArray [] = { {sbeGetScom, SBE_CMD_GETSCOM, - HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, {sbePutScom, SBE_CMD_PUTSCOM, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, {sbeModifyScom, SBE_CMD_MODIFYSCOM, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, {sbePutScomUnderMask, SBE_CMD_PUTSCOM_MASK, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, {sbeMultiScom, SBE_CMD_MULTISCOM, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, }; @@ -91,7 +90,7 @@ static sbeCmdStruct_t g_sbeIplControlCmdArray [] = {sbeHandleIstep, SBE_CMD_EXECUTE_ISTEP, PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_RUNTIME| - SBE_FENCE_AT_DUMPING, + SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_QUIESCE, // This is allowed in FFDC Collect state // TODO - Issue 157287 - Allow MPIIPL in Isteps state }, @@ -99,7 +98,8 @@ static sbeCmdStruct_t g_sbeIplControlCmdArray [] = {sbeContinueBoot, SBE_CMD_CONTINUE_BOOT, PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_RUNTIME| - SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ISTEP, + SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ISTEP| + SBE_FENCE_AT_QUIESCE, // This is allowed only in FFDC Collect State in PLCK mode }, }; @@ -112,7 +112,7 @@ static sbeCmdStruct_t g_sbeGenericCmdArray [] = { {sbeGetCapabilities, SBE_CMD_GET_SBE_CAPABILITIES, - SBE_STATE_FFDC_COLLECT, + SBE_FENCE_AT_FFDC_COLLECT, // Fence in FFDC Collect State, since it might over-write traces }, @@ -120,6 +120,11 @@ static sbeCmdStruct_t g_sbeGenericCmdArray [] = SBE_CMD_GET_SBE_FFDC, SBE_NO_FENCE, }, + + {sbeFifoQuiesce, + SBE_CMD_QUIESCE, + SBE_NO_FENCE, + }, }; ////////////////////////////////////////////////////////////// @@ -130,22 +135,24 @@ static sbeCmdStruct_t g_sbeMemoryAccessCmdArray [] = { {sbeGetMem, SBE_CMD_GETMEM, - HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, {sbePutMem, SBE_CMD_PUTMEM, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, {sbeGetOccSram, SBE_CMD_GETSRAM_OCC, - HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT| + SBE_FENCE_AT_QUIESCE, }, {sbePutOccSram, SBE_CMD_PUTSRAM_OCC, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT| + SBE_FENCE_AT_QUIESCE, }, }; @@ -157,7 +164,7 @@ static sbeCmdStruct_t g_sbeInstructionCntlCmdArray[] = { {sbeCntlInst, SBE_CMD_CONTROL_INSTRUCTIONS, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT, }, }; @@ -169,12 +176,14 @@ static sbeCmdStruct_t g_sbeRegAccessCmdArray [] = { {sbeGetReg, SBE_CMD_GETREG, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT| + SBE_FENCE_AT_QUIESCE, }, {sbePutReg, SBE_CMD_PUTREG, - PUT_HARDWARE_FENCED_STATE|SBE_STATE_FFDC_COLLECT, + PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_FFDC_COLLECT| + SBE_FENCE_AT_QUIESCE, }, }; @@ -187,7 +196,8 @@ static sbeCmdStruct_t g_sbeMpiplCmdArray[] = {sbeEnterMpipl, SBE_CMD_MPIPL_ENTER, PUT_HARDWARE_FENCED_STATE|SBE_FENCE_AT_ISTEP| - SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ABORT, + SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ABORT| + SBE_FENCE_AT_QUIESCE, // Allow Fspless system to enter MPIPL // Honour MPIPL at FFDC Collect state // Issue 157287 @@ -197,7 +207,8 @@ static sbeCmdStruct_t g_sbeMpiplCmdArray[] = SBE_CMD_MPIPL_CONTINUE, HARDWARE_FENCED_STATE|SBE_FENCE_AT_ISTEP| SBE_FENCE_AT_RUNTIME|SBE_FENCE_AT_DUMPING| - SBE_FENCE_AT_ABORT|SBE_FENCE_AT_FFDC_COLLECT, + SBE_FENCE_AT_ABORT|SBE_FENCE_AT_FFDC_COLLECT| + SBE_FENCE_AT_QUIESCE, // Only allowed State is MPIPL }, }; @@ -210,7 +221,7 @@ static sbeCmdStruct_t g_sbeRingAccessCmdArray [] = { {sbeGetRing, SBE_CMD_GETRING, - SBE_FENCE_AT_CONTINUOUS_IPL, + SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE, }, }; @@ -225,7 +236,7 @@ static sbeCmdStruct_t g_sbeCoreStateControlCmdArray [] = SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE| SBE_FENCE_AT_MPIPL|SBE_FENCE_AT_ISTEP| SBE_FENCE_AT_DUMPING|SBE_FENCE_AT_ABORT| - SBE_FENCE_AT_FFDC_COLLECT, + SBE_FENCE_AT_FFDC_COLLECT|SBE_FENCE_AT_QUIESCE, }, }; @@ -237,10 +248,21 @@ static sbeCmdStruct_t g_sbePutRingFromImageCmdArray [] = { {sbePutRingFromImagePSU, SBE_PSU_MSG_PUT_RING_FROM_IMAGE, - SBE_FENCE_AT_CONTINUOUS_IPL, + SBE_FENCE_AT_CONTINUOUS_IPL|SBE_FENCE_AT_QUIESCE, }, }; +////////////////////////////////////////////////////////////// +// @brief g_sbePsuGenericCmdArray +// +////////////////////////////////////////////////////////////// +static sbeCmdStruct_t g_sbePsuGenericCmdArray[] = +{ + {sbePsuQuiesce, + SBE_PSU_GENERIC_MSG_QUIESCE, + SBE_NO_FENCE, + }, +}; //////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////// @@ -315,6 +337,12 @@ uint8_t sbeGetCmdStructAttr (const uint8_t i_cmdClass, *o_ppCmd = (sbeCmdStruct_t*)g_sbePutRingFromImageCmdArray; break; + case SBE_PSU_CMD_CLASS_GENERIC: + l_numCmds = sizeof(g_sbePsuGenericCmdArray) / + sizeof(sbeCmdStruct_t); + *o_ppCmd = (sbeCmdStruct_t*)g_sbePsuGenericCmdArray; + break; + // This will grow with each class of chipOp in future default: break; @@ -392,13 +420,18 @@ bool sbeIsCmdAllowedAtState (const uint8_t i_cmdClass, switch(l_state) { - case SBE_STATE_QUIESCE: case SBE_STATE_UNKNOWN: case SBE_STATE_FAILURE: // All operations are fenced here, return false // Reset is the only Option available break; + case SBE_STATE_QUIESCE: + { + l_ret = ((l_pCmd->cmd_state_fence & + SBE_FENCE_AT_QUIESCE)? false:true); + break; + } case SBE_STATE_FFDC_COLLECT: { l_ret = ((l_pCmd->cmd_state_fence & diff --git a/src/sbefw/sbeevents.H b/src/sbefw/sbeevents.H index 1b085922..233bc6ad 100644 --- a/src/sbefw/sbeevents.H +++ b/src/sbefw/sbeevents.H @@ -52,6 +52,7 @@ enum sbeEvent SBE_DMT_COMP_EVENT = 0xA, // From DMT State SBE_FAILURE_EVENT = 0xB, // From Any State SBE_FFDC_COLLECT_EVENT = 0xC, // From Unknown State + SBE_QUIESCE_EVENT = 0xD, // From Any State }; // Maximum number of Events per State @@ -59,18 +60,18 @@ enum maxEventPerState { SBE_STATE_UNKNOWN_MAX_EVENT = 5, SBE_STATE_FFDC_COLLECT_MAX_EVENT = 4, - SBE_STATE_IPLING_MAX_EVENT = 4, - SBE_STATE_ISTEP_MAX_EVENT = 3, - SBE_STATE_RUNTIME_MAX_EVENT = 4, - SBE_STATE_MPIPL_MAX_EVENT = 2, - SBE_STATE_DMT_MAX_EVENT = 1, + SBE_STATE_IPLING_MAX_EVENT = 5, + SBE_STATE_ISTEP_MAX_EVENT = 4, + SBE_STATE_RUNTIME_MAX_EVENT = 5, + SBE_STATE_MPIPL_MAX_EVENT = 3, + SBE_STATE_DMT_MAX_EVENT = 2, SBE_STATE_DUMP_MAX_EVENT = 0, SBE_STATE_FAILURE_MAX_EVENT = 0, SBE_STATE_QUIESCE_MAX_EVENT = 0, SBE_STATE_ABORT_MAX_EVENT = 0, // Total number of State Transition Events, Addition of all the above - SBE_MAX_TRANSITIONS = 23, + SBE_MAX_TRANSITIONS = 28, }; @@ -83,14 +84,14 @@ enum entryToStateMap SBE_STATE_UNKNOWN_ENTRY_TO_MAP = 0, SBE_STATE_FFDC_COLLECT_ENTRY_TO_MAP = SBE_STATE_UNKNOWN_ENTRY_TO_MAP + SBE_STATE_UNKNOWN_MAX_EVENT, // 5 SBE_STATE_IPLING_ENTRY_TO_MAP = SBE_STATE_FFDC_COLLECT_ENTRY_TO_MAP + SBE_STATE_FFDC_COLLECT_MAX_EVENT, //9 - SBE_STATE_ISTEP_ENTRY_TO_MAP = SBE_STATE_IPLING_ENTRY_TO_MAP + SBE_STATE_IPLING_MAX_EVENT, //13 - SBE_STATE_RUNTIME_ENTRY_TO_MAP = SBE_STATE_ISTEP_ENTRY_TO_MAP + SBE_STATE_ISTEP_MAX_EVENT, //16 - SBE_STATE_MPIPL_ENTRY_TO_MAP = SBE_STATE_RUNTIME_ENTRY_TO_MAP + SBE_STATE_RUNTIME_MAX_EVENT, //20 - SBE_STATE_DMT_ENTRY_TO_MAP = SBE_STATE_MPIPL_ENTRY_TO_MAP + SBE_STATE_MPIPL_MAX_EVENT, //22 - SBE_STATE_DUMP_ENTRY_TO_MAP = SBE_STATE_DMT_ENTRY_TO_MAP + SBE_STATE_DMT_MAX_EVENT, //23 - SBE_STATE_FAILURE_ENTRY_TO_MAP = SBE_STATE_DUMP_ENTRY_TO_MAP + SBE_STATE_DUMP_MAX_EVENT, //23 - SBE_STATE_QUIESCE_ENTRY_TO_MAP = SBE_STATE_FAILURE_ENTRY_TO_MAP + SBE_STATE_FAILURE_MAX_EVENT, //23 - SBE_STATE_ABORT_ENTRY_TO_MAP = SBE_STATE_QUIESCE_ENTRY_TO_MAP + SBE_STATE_QUIESCE_MAX_EVENT, //23 + SBE_STATE_ISTEP_ENTRY_TO_MAP = SBE_STATE_IPLING_ENTRY_TO_MAP + SBE_STATE_IPLING_MAX_EVENT, //14 + SBE_STATE_RUNTIME_ENTRY_TO_MAP = SBE_STATE_ISTEP_ENTRY_TO_MAP + SBE_STATE_ISTEP_MAX_EVENT, //18 + SBE_STATE_MPIPL_ENTRY_TO_MAP = SBE_STATE_RUNTIME_ENTRY_TO_MAP + SBE_STATE_RUNTIME_MAX_EVENT, //23 + SBE_STATE_DMT_ENTRY_TO_MAP = SBE_STATE_MPIPL_ENTRY_TO_MAP + SBE_STATE_MPIPL_MAX_EVENT, //26 + SBE_STATE_DUMP_ENTRY_TO_MAP = SBE_STATE_DMT_ENTRY_TO_MAP + SBE_STATE_DMT_MAX_EVENT, //28 + SBE_STATE_FAILURE_ENTRY_TO_MAP = SBE_STATE_DUMP_ENTRY_TO_MAP + SBE_STATE_DUMP_MAX_EVENT, //28 + SBE_STATE_QUIESCE_ENTRY_TO_MAP = SBE_STATE_FAILURE_ENTRY_TO_MAP + SBE_STATE_FAILURE_MAX_EVENT, //28 + SBE_STATE_ABORT_ENTRY_TO_MAP = SBE_STATE_QUIESCE_ENTRY_TO_MAP + SBE_STATE_QUIESCE_MAX_EVENT, //28 }; #endif //__SBEFW_SBEEVENTS_H diff --git a/src/sbefw/sberegaccess.C b/src/sbefw/sberegaccess.C index 1e6067d5..2fa26c5e 100644 --- a/src/sbefw/sberegaccess.C +++ b/src/sbefw/sberegaccess.C @@ -88,16 +88,21 @@ static const stateTransitionStr_t stateTransMap[SBE_MAX_TRANSITIONS] = { {SBE_STATE_IPLING, SBE_DUMP_FAILURE_EVENT, SBE_STATE_DUMP}, {SBE_STATE_IPLING, SBE_FAILURE_EVENT, SBE_STATE_FAILURE}, {SBE_STATE_IPLING, SBE_ABORT_EVENT, SBE_STATE_ABORT}, + {SBE_STATE_IPLING, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE}, {SBE_STATE_ISTEP, SBE_RUNTIME_EVENT, SBE_STATE_RUNTIME}, {SBE_STATE_ISTEP, SBE_ABORT_EVENT, SBE_STATE_ABORT}, {SBE_STATE_ISTEP, SBE_FAILURE_EVENT, SBE_STATE_FAILURE}, + {SBE_STATE_ISTEP, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE}, {SBE_STATE_RUNTIME, SBE_DUMP_FAILURE_EVENT, SBE_STATE_DUMP}, {SBE_STATE_RUNTIME, SBE_ENTER_MPIPL_EVENT, SBE_STATE_MPIPL}, {SBE_STATE_RUNTIME, SBE_DMT_ENTER_EVENT, SBE_STATE_DMT}, {SBE_STATE_RUNTIME, SBE_FAILURE_EVENT, SBE_STATE_FAILURE}, + {SBE_STATE_RUNTIME, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE}, {SBE_STATE_MPIPL, SBE_CONTINUE_MPIPL_EVENT, SBE_STATE_RUNTIME}, {SBE_STATE_MPIPL, SBE_DUMP_FAILURE_EVENT, SBE_STATE_DUMP}, + {SBE_STATE_MPIPL, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE}, {SBE_STATE_DMT, SBE_DMT_COMP_EVENT, SBE_STATE_RUNTIME}, + {SBE_STATE_DMT, SBE_QUIESCE_EVENT, SBE_STATE_QUIESCE}, }; /** diff --git a/src/test/testcases/test.xml b/src/test/testcases/test.xml index 32be24f4..668aa841 100755 --- a/src/test/testcases/test.xml +++ b/src/test/testcases/test.xml @@ -41,6 +41,7 @@ <include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include> <include>../simics/targets/p9_nimbus/sbeTest/testExecutorPutRing.xml</include> <include>../simics/targets/p9_nimbus/sbeTest/testGetRing.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testQuiesce.xml</include> <testcase> <simcmd>sbe-trace 0</simcmd> </testcase> diff --git a/src/test/testcases/testGetCapabilities.py b/src/test/testcases/testGetCapabilities.py index 006d17c2..33971638 100755 --- a/src/test/testcases/testGetCapabilities.py +++ b/src/test/testcases/testGetCapabilities.py @@ -48,7 +48,7 @@ EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc 0xa7,0x0,0x0,0x1, # control Instruction 0x00,0x0,0x0,0x0]; -EXPDATA3 = [0xa8,0x0,0x0,0x03, #getcapability/getSbeFFDC +EXPDATA3 = [0xa8,0x0,0x0,0x13, #getcapability/getSbeFFDC/quiesce 0x0,0x0,0x0,0x0, 0xc0,0xde,0xa8,0x02, 0x0,0x0,0x0,0x0, diff --git a/src/test/testcases/testQuiesce.py b/src/test/testcases/testQuiesce.py new file mode 100755 index 00000000..55aa2194 --- /dev/null +++ b/src/test/testcases/testQuiesce.py @@ -0,0 +1,57 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testQuiesce.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +TESTDATA = [0,0,0,2, + 0,0,0xA8,0x06 ] + +EXPDATA = [0xc0,0xde,0xa8,0x06, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x3]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( EXPDATA ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testQuiesce.xml b/src/test/testcases/testQuiesce.xml new file mode 100644 index 00000000..8b502949 --- /dev/null +++ b/src/test/testcases/testQuiesce.xml @@ -0,0 +1,45 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/test/testcases/testQuiesce.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<?xml version="1.0" encoding="UTF-8"?> + + <!-- SBE Quiesce Test case --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testQuiesce.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- A Get Capabilities chip-op should succeed post the Quiesce --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetCapabilities.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- A GetScom/PutScom chip-op should succeed post the Quiesce --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> + <!-- An Adu put chip-op should succeed post the Quiesce --> + <testcase> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd> + <exitonerror>yes</exitonerror> + </testcase> |