cresp address error handling updates

  This commit sets up the FBC trace arrays to stop on a combined response
  address error, for MPIPL FFDC collection.

  It also adjusts the FIR configuration for several units, to trigger
  a system checkstop (based on their own LFIR) if they master a command
  which recieves a combined response address error cresp, and we do
  not support MPIPL from that condition.    Unlike in past projects, the
  FBC level cresp address error FIR bit cannot be set to checkstop (in order
  to support MPIPL scenarios where the unacknowledged access eminates from
  the core)

  FIR action bits modified:
    PSIHB bits 15:20
    PBA bit 1

Change-Id: Ie569600c2c937644740636e8a33097f7979d8d6f
CQ: SW411054
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52604
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52634
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

0 files changed, 0 insertions, 0 deletions