cresp address error handling updates

  This commit sets up the FBC trace arrays to stop on a combined response
  address error, for MPIPL FFDC collection.

  It also adjusts the FIR configuration for several units, to trigger
  a system checkstop (based on their own LFIR) if they master a command
  which recieves a combined response address error cresp, and we do
  not support MPIPL from that condition.    Unlike in past projects, the
  FBC level cresp address error FIR bit cannot be set to checkstop (in order
  to support MPIPL scenarios where the unacknowledged access eminates from
  the core)

  FIR action bits modified:
    PSIHB bits 15:20
    PBA bit 1

Change-Id: Ie569600c2c937644740636e8a33097f7979d8d6f
CQ: SW411054
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52604
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52634
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 24 insertions, 1 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index 3f6c633d..29698fd9 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -50,6 +50,7 @@
 #include <p9_misc_scom_addresses_fld.H>
 #include <p9_perv_scom_addresses.H>
 #include <p9_perv_scom_addresses_fld.H>
+#include <p9n2_perv_scom_addresses_fld.H>
 #include <p9_xbus_scom_addresses.H>
 #include <p9_obus_scom_addresses.H>
 #include <p9_sbe_common.H>
@@ -82,7 +83,7 @@ const uint64_t LPC_FIR_MASK    = 0x18F0000000000000ULL;
 // PBA FIR constants
 const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL;
 const uint64_t PBA_FIR_ACTION1 = 0x0C0100600C000000ULL;
-const uint64_t PBA_FIR_MASK = 0x7082448062FC0000ULL;
+const uint64_t PBA_FIR_MASK = 0x3082448062FC0000ULL;
 
 // PPE FIR constants
 // FBC
@@ -98,6 +99,9 @@ const uint64_t OB_PPE_FIR_ACTION0 = 0x0000000000000000ULL;
 const uint64_t OB_PPE_FIR_ACTION1 = 0xF1C0000000000000ULL;
 const uint64_t OB_PPE_FIR_MASK    = 0x0E38000000000000ULL;
 
+// nest trace setup constants
+const uint8_t N1_PROBE1_SEL = 0x11;
+
 // nest DTS enablement constants
 const uint8_t NEST_THERM_MODE_SAMPLE_PULSE_COUNT = 0xF;
 const uint8_t NEST_THERM_MODE_LOOP0_ENABLE = 0x2;
@@ -477,6 +481,25 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
         }
     }
 
+    // configure NEST tracing logic
+    {
+        // mux N1 DBG broadcast(1) onto oob(5)
+        fapi2::buffer<uint64_t> l_cplt_conf0;
+        FAPI_TRY(fapi2::getScom(i_target, PERV_N1_CPLT_CONF0, l_cplt_conf0),
+                 "Error from getScom (PERV_N1_CPLT_CONF0)");
+        l_cplt_conf0.insertFromRight<PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC,
+                                     PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN>(N1_PROBE1_SEL);
+        FAPI_TRY(fapi2::putScom(i_target, PERV_N1_CPLT_CONF0, l_cplt_conf0),
+                 "Error from putScom (PERV_N1_CPLT_CONF0)");
+
+        // ungate global broadcast input on N3 DBG
+        FAPI_TRY(fapi2::getScom(i_target, PERV_N3_CPLT_CONF0, l_cplt_conf0),
+                 "Error from getScom (PERV_N3_CPLT_CONF0)");
+        l_cplt_conf0.setBit<P9N2_PERV_1_CPLT_CONF0_TC_PCB_DBG_GLB_BRCST_EN>();
+        FAPI_TRY(fapi2::putScom(i_target, PERV_N3_CPLT_CONF0, l_cplt_conf0),
+                 "Error from putScom (PERV_N3_CPLT_CONF0)");
+    }
+
     // configure PCI tracing logic
     {
         for (auto& l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV>