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author | Joe McGill <jmcgill@us.ibm.com> | 2017-01-04 20:45:43 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-01-16 23:31:32 -0500 |
commit | 6e530eb5259bc186e878e7cdf878ce6fb5aee93e (patch) | |
tree | c9fd03291172cb9052926765c258d33c514068bf /src/import/tools | |
parent | 6b72e2618482554e40ce0bb8c379ff94dadbcc91 (diff) | |
download | talos-sbe-6e530eb5259bc186e878e7cdf878ce6fb5aee93e.tar.gz talos-sbe-6e530eb5259bc186e878e7cdf878ce6fb5aee93e.zip |
add SS PLL settings to support 94 MHz PCI operation
support PCIE on DD1.x by lowering input refclock
Change-Id: Ic69f0b4cdcba9d667d08aa37aced6dbc4c156c98
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34389
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34469
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/tools')
0 files changed, 0 insertions, 0 deletions