diff options
-rwxr-xr-x | customrc | 2 | ||||
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 18 |
2 files changed, 19 insertions, 1 deletions
@@ -33,6 +33,6 @@ export SANDBOXNAME=test_sb #export WORKSPACE=<set it to your root ppe directory. This is required if you # to use build script locally> export MACHINE=NIMBUS -export BACKING_BUILD=/esw/fips910/Builds/b0107a_1702.910/ +export BACKING_BUILD=/esw/fips910/Builds/b0115a_1704.910/ export SIMICSOPTIONS="-nre" diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 698d6b59..562c53ad 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -426,6 +426,24 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 only: leverage SS PLL to provide reduced frequency reference clock + (94 MHz, instead of nominal 100 MHz) for PCI PLL + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> <!-- ******************************************************************** --> <!-- Memory Section --> |