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authorJoachim Fenkes <fenkes@de.ibm.com>2019-07-15 17:08:29 +0200
committerRAJA DAS <rajadas2@in.ibm.com>2019-07-30 13:56:48 -0500
commitace8002539d41d4f320e7d7e3d76d4089eec6542 (patch)
tree051f7f88c6a62ccd0217a987ab839a9442dcf860 /src/import/chips
parentdfae3a84ef5c82b843e9a242f92e0c589af2424d (diff)
downloadtalos-sbe-ace8002539d41d4f320e7d7e3d76d4089eec6542.tar.gz
talos-sbe-ace8002539d41d4f320e7d7e3d76d4089eec6542.zip
Streamline the way PIB/NET are initialized between SBE and Cronus
Instead of p9_start_cbs swinging the PCB mux to PIB2PCB, do it in p9_sbe_tp_chiplet_init1. The PIBMEM repair code on the SBE does it this way already so no change is needed there. This way, even if we start the SBE but then run isteps in Cronus, both pieces of code will work correctly since they don't depend on previous steps leaving the mux in a specific state. Change-Id: I4a2bd53f813cbb0a00486effb156a3c2a7f4336a CQ: SW470122 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81162 Reviewed-by: Joseph J McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Milton D Miller <miltonm@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81191 Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C59
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H7
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C62
3 files changed, 55 insertions, 73 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
index f2ae836c..56401c8c 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2018 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -515,60 +515,3 @@ fapi_try_exit:
return fapi2::current_err;
}
-
-#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
-/// @brief Switching to PCB2PCB Path via scom
-///
-/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP
-/// @return FAPI2_RC_SUCCESS if success, else error code.
-fapi2::ReturnCode p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom(const
- fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
-{
- fapi2::buffer<uint64_t> l_read_reg;
- FAPI_INF("p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom: Entering ...");
-
- FAPI_DBG("Reading ROOT_CTRL0_REG");
- FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
-
- if (!l_read_reg.getBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>())
- {
- FAPI_DBG("Setting PCB RESET bit in ROOT_CTRL0_REG");
- l_read_reg.setBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
- FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
- }
-
- if (!l_read_reg.getBit<PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL>())
- {
- FAPI_DBG("Setting PCB2PCB bit in ROOT_CTRL0_REG");
- l_read_reg.setBit<PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL>();
- FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
- }
-
- if (l_read_reg.getBit<PERV_ROOT_CTRL0_PIB2PCB_DC>())
- {
- FAPI_DBG("Clearing FSI2PCB bit in ROOT_CTRL0_REG");
- l_read_reg.clearBit<PERV_ROOT_CTRL0_PIB2PCB_DC>();
- FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
- }
-
- if (l_read_reg.getBit<PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL>())
- {
- FAPI_DBG("Clearing PIB2PCB bit in ROOT_CTRL0_REG");
- l_read_reg.clearBit<PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL>();
- FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
- }
-
- if (l_read_reg.getBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>())
- {
- FAPI_DBG("Clearing PCB RESET bit in ROOT_CTRL0_REG");
- l_read_reg.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
- FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_read_reg));
- }
-
- FAPI_INF("p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom: Exiting ...");
-
-fapi_try_exit:
- return fapi2::current_err;
-
-}
-#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
index 348ca281..edee80d2 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2018 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -66,9 +66,4 @@ fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const
const fapi2::buffer<uint16_t> i_regions,
const fapi2::buffer<uint16_t> i_scan_types);
-#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__)
-fapi2::ReturnCode p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom(const
- fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
-#endif
-
#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
index 3855979f..dac6a42a 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2018 */
+/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -41,6 +41,7 @@
#include <p9_perv_scom_addresses.H>
#include <p9_perv_scom_addresses_fld.H>
#include <p9n2_perv_scom_addresses_fld.H>
+#include <p9a_perv_scom_addresses_fld.H>
#include <p9_perv_sbe_cmn.H>
#include <p9_sbe_common.H>
@@ -55,6 +56,48 @@ enum P9_SBE_TP_CHIPLET_INIT1_Private_Constants
SCAN_TYPES_TIME_GPTR_REPR = 0x230
};
+#ifndef __PPE__
+/// @brief Switch PCB mux via CFAM
+///
+/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP
+/// @param[in] i_new_position Desired new mux position (bit position in ROOT_CTRL0)
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode switch_pcb_mux_cfam(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip,
+ const uint32_t i_new_position)
+{
+ fapi2::buffer<uint32_t> l_pcb_reset, l_mux_select;
+
+ l_pcb_reset.flush<0>().setBit<PERV_ROOT_CTRL0_PCB_RESET_DC>();
+
+ l_mux_select.flush<0>()
+ .setBit<P9A_PERV_ROOT_CTRL0_PIB2PCB_DC>()
+ .setBit<P9A_PERV_ROOT_CTRL0_PCB2PCB_DC>();
+
+ FAPI_DBG("Setting PCB RESET bit in ROOT_CTRL0_REG");
+ FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_SET_FSI, l_pcb_reset));
+
+ // This will unconditionally set both bits (PIB2PCB, PCB2PCB), switching to a safe
+ // intermediate state from either of the two settings.
+ FAPI_DBG("Setting PCB mux to intermediate state");
+ FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_SET_FSI, l_mux_select));
+
+ // We CLEAR the bit corresponding to the desired new position in l_mux_select
+ // and then use the CLEAR address of RC0 to effectively clear the _other_ bit,
+ // so that the bit left standing is our desired new position.
+ FAPI_DBG("Setting PCB mux to final state");
+ l_mux_select.clearBit(i_new_position);
+ FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_CLEAR_FSI, l_mux_select));
+
+ FAPI_DBG("Clearing PCB RESET bit in ROOT_CTRL0_REG");
+ FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_CLEAR_FSI, l_pcb_reset));
+
+fapi_try_exit:
+ return fapi2::current_err;
+
+}
+#endif
+
fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
@@ -102,12 +145,14 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
#ifndef __PPE__
- if(l_is_axone)
+ if (l_is_axone)
{
- FAPI_DBG("Release PCB Reset");
- //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
- l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
- FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0));
+ /*
+ * In some lab configurations, the SBE might have done these exact steps
+ * before us already, but it won't hurt to do them all again.
+ */
+ FAPI_DBG("Switch PCB mux to PIB2PCB position");
+ FAPI_TRY(switch_pcb_mux_cfam(i_target_chip, P9A_PERV_ROOT_CTRL0_PIB2PCB_DC));
FAPI_DBG("Set Chiplet Enable");
//PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
@@ -130,9 +175,8 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
FAPI_DBG("l_clk_regions value: %#018lX", l_clk_regions);
FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_clk_regions, CLOCK_TYPES_ALL));
- FAPI_DBG("Switching to PCB2PCB path");
- FAPI_TRY(p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom(
- i_target_chip));
+ FAPI_DBG("Switch PCB mux to PCB2PCB position");
+ FAPI_TRY(switch_pcb_mux_cfam(i_target_chip, P9A_PERV_ROOT_CTRL0_PCB2PCB_DC));
//Getting ROOT_CTRL0 register value again as it is changed in above function
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM,
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