diff options
author | Joe McGill <jmcgill@us.ibm.com> | 2017-07-29 13:15:12 -0500 |
---|---|---|
committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-11-13 11:41:54 -0500 |
commit | a99727e54d98ae1db3a9ef8ad0d071af9200e22f (patch) | |
tree | 9a21792113d16f6b51ebb492a21f8f4ac3531993 /src/import/chips | |
parent | 2ad7f676c15fdc6c3e07cad43a40fdad2cf57e87 (diff) | |
download | talos-sbe-a99727e54d98ae1db3a9ef8ad0d071af9200e22f.tar.gz talos-sbe-a99727e54d98ae1db3a9ef8ad0d071af9200e22f.zip |
IO, FBC updates to enable ABUS for Fleetwood
Attributes:
-------------------------------------------------------------------------------
nest_attributes.xml
add ATTR_LINK_TRAIN, written by platform on X, O endpoints to specify
whether half or full link should be trained
add ATTR_PROC_FABRIC_LINK_ACTIVE, written by p9_fbc_eff_config_links
adjust enums for ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG, written
by p9_fbc_eff_config_links
add ATTR_PROC_FABRIC_[XA]_LINKS_CNFG, written by p9_fbc_eff_config_links
pervasive_attributes.xml
create ATTR_PROC_NPU_REGION_ENABLED to encapsulate accessibility of
NPU logic domain, written by p9_chiplet_scominit
chip_ec_attributes.xml
add EC feature attribute controlling DL training workaround
Initfiles:
-------------------------------------------------------------------------------
p9.fbc.ab_hp.scom.initfile
add logic to permit reset of chg_rate master dials in second phase SMP build
adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
p9.fbc.cd_hp.scom.initfile
p9.fbc.no_hp.scom.initfile
consume number of configured X/A links from new attribute, simple addition
won't work any longer given new ATTACHED_CHIP_CNFG enums
p9.fbc.ioe_dl.scom.initfile
support half-link operation, based on ATTR_LINK_TRAIN on X endpoint target
p9.fbc.ioe_tl.scom.initifle
adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
p9.fbc.ioo_dl.scom.initfile
support half-link operation, based on ATTR_LINK_TRAIN on O endpoint target
qualify OLL enablement based on use as active fabric link
adjust PHY training parameters based on current lab learning
p9.fbc.ioo_tl.scom.initfile
adjust link enable expressions to reflect new ATTACHED_CHIP_CNFG enums
support half-link operation, based on ATTACHED_CHIP_CNFG
qualify TOD_ENABLE to apply only to O links carrying X traffic
p9.npu.scom.initfile
clear OPTICAL_IO_CONFIG when not actively using NVLINK, finer-grained
updates needed to support mix of O SMP and NVLINK usage
HWPs:
-------------------------------------------------------------------------------
p9_io_obus_dccal
execute only on links actively carrying fabric protocol
p9_io_obus_linktrain
p9_io_regs
encapsulate PHY FIFO reset sequence needed prior to FBC DL training execution
p9_chiplet_scominit
p9_npu_scominit
partial good updates for NPU region
p9_fab_iovalid
adjust iovalid manipulation/checking, as well as link delay reporting, to
support half-link configuration
p9_smp_link_layer
support half-link configuration via ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG
implement OBUS PHY specific workarounds
p9_eff_config_links
update ATTR_PROC_FABRIC_[XA]_ATTACHED_CHIP_CNFG to support half-link
configuration
write ATTR_PROC_FABRIC_LINK_ACTIVE on X/O endpoint targets
write ATTR_PROC_FABRIC_[XA]_LINKS_CNFG to reflect total number of logically
configured links, for initfile consumption
Istep wrappers:
-------------------------------------------------------------------------------
p9_build_smp_wrap
correctly loop over all system targets for second phase SMP build
p9_sys_chiplet_scominit_wrap
initial release
Change-Id: Ic1d87df4d3ff0feca7ac2437fa61b6d2fc4a2d68
CQ: HW419022
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43905
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46996
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
3 files changed, 105 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 93a6af9e..1373bc75 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1870,6 +1870,24 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW424691</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Cumulus DD1.0: enable workarounds for HW424691 in FBC initfile + Set alink token inits via scan for dd1.0 to avoid serial scom conflict + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>LESS_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW409019</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -5556,4 +5574,22 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW419022</id>> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Cumulus DD1: Use alternate training sequence to establish + OBUS fabric DL layer to avoid HW419022 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> </attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 850cb305..cce29eb4 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -475,6 +475,38 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_LINK_ACTIVE</id> + <targetType>TARGET_TYPE_XBUS,TARGET_TYPE_OBUS</targetType> + <description> + Indicates if the endpoint target is actively being used as a fabric link + </description> + <valueType>uint8</valueType> + <enum> + FALSE = 0x0, + TRUE = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_LINK_TRAIN</id> + <targetType>TARGET_TYPE_XBUS,TARGET_TYPE_OBUS</targetType> + <description> + Indicates which sublinks should be initialized/trained + </description> + <valueType>uint8</valueType> + <enum> + BOTH = 0x0, + EVEN_ONLY = 0x1, + ODD_ONLY = 0x2 + </enum> + <writeable/> + <initToZero/> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -485,13 +517,26 @@ <array>7</array> <enum> FALSE = 0x0, - TRUE = 0x1 + TRUE = 0x1, + EVEN_ONLY = 0x2, + ODD_ONLY = 0x3 </enum> <writeable/> <initToZero/> </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_X_LINKS_CNFG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Contains the total number of active X links on this chip + </description> + <valueType>uint8</valueType> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -502,13 +547,26 @@ <array>4</array> <enum> FALSE = 0x0, - TRUE = 0x1 + TRUE = 0x1, + EVEN_ONLY = 0x2, + ODD_ONLY = 0x3 </enum> <writeable/> <initToZero/> </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_A_LINKS_CNFG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Contains the total number of active A links on this chip + </description> + <valueType>uint8</valueType> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_ID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 2a8e04d1..d58e393e 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -29,6 +29,15 @@ <attributes> <attribute> + <id>ATTR_PROC_NPU_REGION_ENABLED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Boolean indicating accessibilty of NPU logic region</description> + <valueType>uint8</valueType> + <writeable/> + <initToZero/> +</attribute> + +<attribute> <id>ATTR_CLOCK_PLL_MUX</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>setup clock mux settings</description> |