Update quad power off so HB can call it on Slave Quads

Previously this HWP was only being called by the SBE down the MPIPL
but we also need to call it during HB to power down the slave quads.
There is a tricky workaround in this HWP where we need to save off
some ring data EQ pointers for the PB. On the SBE we just saved
the rings in global variables but we cannot do that in HB because
the Hcode would not have access to the global varibles. Instead
we will write the ring data to the OCC SRAM to do this I will
just pass the data out of the hwp via an out param
The same ring data is fetch during cache_initf procedure to init

Change-Id: I4f20cd8dd9ca1b53604db1bc3020c0d57bbd1172
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36828
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37977
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

4 files changed, 37 insertions, 44 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
index 03e6add2..6dd1f766 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
@@ -52,25 +52,28 @@
 #include <p9_quad_scom_addresses.H>
 #include <p9_ring_id.h>
 
+static const uint64_t RING_INDEX[10] =
+{
+    0, 5039, 5100, 5664, 5725, 5973, 6034, 6282, 6343, 17871
+};
+
 //------------------------------------------------------------------------------
 // Procedure: EX (non-core) scan init
 //------------------------------------------------------------------------------
 
 fapi2::ReturnCode
 p9_hcd_cache_initf(
-    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+    const uint64_t* i_ring_save_data)
 {
     FAPI_INF(">>p9_hcd_cache_initf");
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     fapi2::buffer<uint64_t> l_data64;
-
-#ifdef __PPE__
-    fapi2::buffer<uint64_t>  l_data64_2;
+    fapi2::buffer<uint64_t> l_data64_2;
     uint8_t                 l_isMpipl = 0;
     uint8_t                 l_isRingSaveMpipl = 0;
     fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
         i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
-#endif
 
 #ifndef __PPE__
     uint8_t l_attr_system_ipl_phase;
@@ -84,12 +87,10 @@ p9_hcd_cache_initf(
 
 #endif
 
-#ifdef __PPE__
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, l_sys, l_isMpipl),
              "fapiGetAttribute of ATTR_IS_MPIPL failed!");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
              "fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
-#endif
 
     FAPI_DBG("Scan eq_fure ring");
     FAPI_TRY(fapi2::putRing(i_target, eq_fure),
@@ -151,8 +152,6 @@ p9_hcd_cache_initf(
 
 #endif
 
-#ifdef __PPE__
-
     if (l_isMpipl && l_isRingSaveMpipl)
     {
         l_data64.flush<0>();
@@ -172,7 +171,7 @@ p9_hcd_cache_initf(
 
         for(uint32_t l_spin = 1; l_spin < 10; l_spin++)
         {
-            /***********G_ring_index***********/
+            /***********RING_INDEX***********/
             //  {0,    0},
             //  {5039, 0xE000000000000000}, //3
             //  {5100, 0xC1E061FFED5F0000}, //29
@@ -186,7 +185,7 @@ p9_hcd_cache_initf(
             /**********************************/
             uint64_t l_scandata = ((l_spin == 0) || (l_spin == 9)) ? 0x0 : (l_spin & 0x1) ?
                                   0xE000000000000000 : 0xC1E061FFED5F0000;
-            l_data64.flush<0>().set((G_ring_index[l_spin] - G_ring_index[l_spin - 1]) << 32);
+            l_data64.flush<0>().set((RING_INDEX[l_spin] - RING_INDEX[l_spin - 1]) << 32);
 
             FAPI_TRY(fapi2::putScom(i_target,
                                     EQ_SCAN_LONG_ROTATE,
@@ -224,7 +223,7 @@ p9_hcd_cache_initf(
                                         EQ_SCAN64,
                                         l_data64));
 
-                l_data64_2.set( (l_data64 & ~l_scandata) | G_ring_save[l_spin - 1]);
+                l_data64_2.set( (l_data64 & ~l_scandata) | i_ring_save_data[l_spin - 1]);
                 FAPI_TRY(fapi2::putScom(i_target,
                                         EQ_SCAN64,
                                         l_data64_2));
@@ -237,8 +236,6 @@ p9_hcd_cache_initf(
                                 l_data64));
     }
 
-#endif
-
 fapi_try_exit:
     FAPI_INF("<<p9_hcd_cache_initf");
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
index 2934b7d9..2931703f 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
@@ -43,7 +43,8 @@
 /// @typedef p9_hcd_cache_initf_FP_t
 /// function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) (
-    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+    const uint64_t* i_ring_save_data);
 
 extern "C"
 {
@@ -51,6 +52,7 @@ extern "C"
 /// @brief EX (non-core) scan init
 ///
 /// @param [in] i_target TARGET_TYPE_EQ target
+/// @param [in] i_ring_save_data ring data EQ pointers for the PB
 ///
 /// @attr
 /// @attritem ATTR_CACHE_L2_FUNC_RING - EX target, uint32
@@ -59,7 +61,8 @@ extern "C"
 /// @retval FAPI_RC_SUCCESS
     fapi2::ReturnCode
     p9_hcd_cache_initf(
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+        const uint64_t* i_ring_save_data);
 
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
index 8939f7bb..96164c76 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
@@ -49,14 +49,11 @@
 #include <p9_quad_power_off.H>
 #include <p9_block_wakeup_intr.H>
 
+
 // ----------------------------------------------------------------------
 // Function definitions
 // ----------------------------------------------------------------------
 
-
-#ifdef __PPE__
-uint64_t G_ring_save[8] = {0, 0, 0, 0, 0, 0, 0, 0};
-
 //    {0,    0},
 //    {5039, 0xE000000000000000}, //3
 //    {5100, 0xC1E061FFED5F0000}, //29
@@ -67,40 +64,38 @@ uint64_t G_ring_save[8] = {0, 0, 0, 0, 0, 0, 0, 0};
 //    {6282, 0xE000000000000000}, //3
 //    {6343, 0xC1E061FFED5F0000}, //29
 //    {17871, 0}                  //128
-const uint64_t G_ring_index[10] =
+
+static const uint64_t RING_INDEX[10] =
 {
     0, 5039, 5100, 5664, 5725, 5973, 6034, 6282, 6343, 17871,
 };
-#endif
-
 
 // Procedure p9_quad_power_off entry point, comments in header
 fapi2::ReturnCode p9_quad_power_off(
-    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+    uint64_t* o_ring_save_data)
 {
     fapi2::buffer<uint64_t> l_data64;
     constexpr uint64_t l_rawData = 0x1100000000000000ULL; // Bit 3 & 7 are set to be manipulated
     constexpr uint32_t MAX_CORE_PER_QUAD = 4;
     fapi2::ReturnCode rc = fapi2::FAPI2_RC_SUCCESS;
     uint32_t l_cnt = 0;
-#ifdef __PPE__
-    uint8_t  l_isMpipl = 0;
-    uint8_t  l_isRingSaveMpipl = 0;
-    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
         i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_isMpipl), "fapiGetAttribute of ATTR_IS_MPIPL failed!");
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
-             "fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
-#endif
+    uint8_t  l_isMpipl = 0;
+    uint8_t  l_isRingSaveMpipl = 0;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
 
     FAPI_INF("p9_quad_power_off: Entering...");
 
     // Print chiplet position
     FAPI_INF("Quad power off chiplet no.%d", i_target.getChipletNumber());
 
-#ifdef __PPE__
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_isMpipl), "fapiGetAttribute of ATTR_IS_MPIPL failed!");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
+             "fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
+
 
     if (l_isMpipl && l_isRingSaveMpipl)
     {
@@ -123,7 +118,7 @@ fapi2::ReturnCode p9_quad_power_off(
         {
             uint64_t l_scandata = ((l_spin == 0) || (l_spin == 9)) ? 0x0 : (l_spin & 0x1) ?
                                   0xE000000000000000 : 0xC1E061FFED5F0000;
-            l_data64.flush<0>().set((G_ring_index[l_spin] - G_ring_index[l_spin - 1]) << 32);
+            l_data64.flush<0>().set((RING_INDEX[l_spin] - RING_INDEX[l_spin - 1]) << 32);
 
             FAPI_TRY(fapi2::putScom(i_target,
                                     EQ_SCAN_LONG_ROTATE,
@@ -160,7 +155,7 @@ fapi2::ReturnCode p9_quad_power_off(
                 FAPI_TRY(fapi2::getScom(i_target,
                                         EQ_SCAN64,
                                         l_data64));
-                G_ring_save[l_spin - 1] = l_scandata & l_data64;
+                o_ring_save_data[l_spin - 1] = l_scandata & l_data64;
             }
         }
 
@@ -170,7 +165,6 @@ fapi2::ReturnCode p9_quad_power_off(
                                 l_data64));
     }
 
-#endif
 
     FAPI_DBG("Disabling bits 20/22/24/26 in EQ_QPPM_QPMMR_CLEAR, to gain access"
              " to PFET controller, otherwise Quad Power off scom will fail");
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
index 9c684aaf..4c6b0065 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
@@ -48,14 +48,10 @@
 // Constant definitions
 //------------------------------------------------------------------------------
 
-#ifdef __PPE__
-    extern uint64_t G_ring_save[8];
-    extern const uint64_t G_ring_index[10];
-#endif
-
 // function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_quad_power_off_FP_t) (
-    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+    uint64_t* o_ring_save_data);
 
 extern "C"
 {
@@ -66,12 +62,15 @@ extern "C"
     /**
      ** @brief Power off the EQ including the functional cores associatated with it.
      **
-     ** @param[in] i_target    Targe type EQ
+     ** @param[in]  i_target         Targe type EQ
+     ** @param[out] o_ring_save_data The ring data that tells the PB how to find the
+     **                              EQ will need to be saved away for when we p-on
      **
      ** @return FAPI2_RC_SUCCESS if success, error otherwise
      **/
     fapi2::ReturnCode p9_quad_power_off (
-        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+        uint64_t* o_ring_save_data);
 
 } // extern "C"