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-rw-r--r--src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C25
-rw-r--r--src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H7
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C34
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H15
-rw-r--r--src/sbefw/sbecmdiplcontrol.C111
-rw-r--r--src/sbefw/sbecmdiplcontrol.H5
6 files changed, 92 insertions, 105 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
index 03e6add2..6dd1f766 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
@@ -52,25 +52,28 @@
#include <p9_quad_scom_addresses.H>
#include <p9_ring_id.h>
+static const uint64_t RING_INDEX[10] =
+{
+ 0, 5039, 5100, 5664, 5725, 5973, 6034, 6282, 6343, 17871
+};
+
//------------------------------------------------------------------------------
// Procedure: EX (non-core) scan init
//------------------------------------------------------------------------------
fapi2::ReturnCode
p9_hcd_cache_initf(
- const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+ const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+ const uint64_t* i_ring_save_data)
{
FAPI_INF(">>p9_hcd_cache_initf");
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
fapi2::buffer<uint64_t> l_data64;
-
-#ifdef __PPE__
- fapi2::buffer<uint64_t> l_data64_2;
+ fapi2::buffer<uint64_t> l_data64_2;
uint8_t l_isMpipl = 0;
uint8_t l_isRingSaveMpipl = 0;
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
-#endif
#ifndef __PPE__
uint8_t l_attr_system_ipl_phase;
@@ -84,12 +87,10 @@ p9_hcd_cache_initf(
#endif
-#ifdef __PPE__
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, l_sys, l_isMpipl),
"fapiGetAttribute of ATTR_IS_MPIPL failed!");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
"fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
-#endif
FAPI_DBG("Scan eq_fure ring");
FAPI_TRY(fapi2::putRing(i_target, eq_fure),
@@ -151,8 +152,6 @@ p9_hcd_cache_initf(
#endif
-#ifdef __PPE__
-
if (l_isMpipl && l_isRingSaveMpipl)
{
l_data64.flush<0>();
@@ -172,7 +171,7 @@ p9_hcd_cache_initf(
for(uint32_t l_spin = 1; l_spin < 10; l_spin++)
{
- /***********G_ring_index***********/
+ /***********RING_INDEX***********/
// {0, 0},
// {5039, 0xE000000000000000}, //3
// {5100, 0xC1E061FFED5F0000}, //29
@@ -186,7 +185,7 @@ p9_hcd_cache_initf(
/**********************************/
uint64_t l_scandata = ((l_spin == 0) || (l_spin == 9)) ? 0x0 : (l_spin & 0x1) ?
0xE000000000000000 : 0xC1E061FFED5F0000;
- l_data64.flush<0>().set((G_ring_index[l_spin] - G_ring_index[l_spin - 1]) << 32);
+ l_data64.flush<0>().set((RING_INDEX[l_spin] - RING_INDEX[l_spin - 1]) << 32);
FAPI_TRY(fapi2::putScom(i_target,
EQ_SCAN_LONG_ROTATE,
@@ -224,7 +223,7 @@ p9_hcd_cache_initf(
EQ_SCAN64,
l_data64));
- l_data64_2.set( (l_data64 & ~l_scandata) | G_ring_save[l_spin - 1]);
+ l_data64_2.set( (l_data64 & ~l_scandata) | i_ring_save_data[l_spin - 1]);
FAPI_TRY(fapi2::putScom(i_target,
EQ_SCAN64,
l_data64_2));
@@ -237,8 +236,6 @@ p9_hcd_cache_initf(
l_data64));
}
-#endif
-
fapi_try_exit:
FAPI_INF("<<p9_hcd_cache_initf");
return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
index 2934b7d9..2931703f 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
@@ -43,7 +43,8 @@
/// @typedef p9_hcd_cache_initf_FP_t
/// function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) (
- const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+ const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+ const uint64_t* i_ring_save_data);
extern "C"
{
@@ -51,6 +52,7 @@ extern "C"
/// @brief EX (non-core) scan init
///
/// @param [in] i_target TARGET_TYPE_EQ target
+/// @param [in] i_ring_save_data ring data EQ pointers for the PB
///
/// @attr
/// @attritem ATTR_CACHE_L2_FUNC_RING - EX target, uint32
@@ -59,7 +61,8 @@ extern "C"
/// @retval FAPI_RC_SUCCESS
fapi2::ReturnCode
p9_hcd_cache_initf(
- const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+ const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+ const uint64_t* i_ring_save_data);
}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
index 8939f7bb..96164c76 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.C
@@ -49,14 +49,11 @@
#include <p9_quad_power_off.H>
#include <p9_block_wakeup_intr.H>
+
// ----------------------------------------------------------------------
// Function definitions
// ----------------------------------------------------------------------
-
-#ifdef __PPE__
-uint64_t G_ring_save[8] = {0, 0, 0, 0, 0, 0, 0, 0};
-
// {0, 0},
// {5039, 0xE000000000000000}, //3
// {5100, 0xC1E061FFED5F0000}, //29
@@ -67,40 +64,38 @@ uint64_t G_ring_save[8] = {0, 0, 0, 0, 0, 0, 0, 0};
// {6282, 0xE000000000000000}, //3
// {6343, 0xC1E061FFED5F0000}, //29
// {17871, 0} //128
-const uint64_t G_ring_index[10] =
+
+static const uint64_t RING_INDEX[10] =
{
0, 5039, 5100, 5664, 5725, 5973, 6034, 6282, 6343, 17871,
};
-#endif
-
// Procedure p9_quad_power_off entry point, comments in header
fapi2::ReturnCode p9_quad_power_off(
- const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+ const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+ uint64_t* o_ring_save_data)
{
fapi2::buffer<uint64_t> l_data64;
constexpr uint64_t l_rawData = 0x1100000000000000ULL; // Bit 3 & 7 are set to be manipulated
constexpr uint32_t MAX_CORE_PER_QUAD = 4;
fapi2::ReturnCode rc = fapi2::FAPI2_RC_SUCCESS;
uint32_t l_cnt = 0;
-#ifdef __PPE__
- uint8_t l_isMpipl = 0;
- uint8_t l_isRingSaveMpipl = 0;
- const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_isMpipl), "fapiGetAttribute of ATTR_IS_MPIPL failed!");
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
- "fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
-#endif
+ uint8_t l_isMpipl = 0;
+ uint8_t l_isRingSaveMpipl = 0;
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
FAPI_INF("p9_quad_power_off: Entering...");
// Print chiplet position
FAPI_INF("Quad power off chiplet no.%d", i_target.getChipletNumber());
-#ifdef __PPE__
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_isMpipl), "fapiGetAttribute of ATTR_IS_MPIPL failed!");
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL, l_chip, l_isRingSaveMpipl),
+ "fapiGetAttribute of ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL failed");
+
if (l_isMpipl && l_isRingSaveMpipl)
{
@@ -123,7 +118,7 @@ fapi2::ReturnCode p9_quad_power_off(
{
uint64_t l_scandata = ((l_spin == 0) || (l_spin == 9)) ? 0x0 : (l_spin & 0x1) ?
0xE000000000000000 : 0xC1E061FFED5F0000;
- l_data64.flush<0>().set((G_ring_index[l_spin] - G_ring_index[l_spin - 1]) << 32);
+ l_data64.flush<0>().set((RING_INDEX[l_spin] - RING_INDEX[l_spin - 1]) << 32);
FAPI_TRY(fapi2::putScom(i_target,
EQ_SCAN_LONG_ROTATE,
@@ -160,7 +155,7 @@ fapi2::ReturnCode p9_quad_power_off(
FAPI_TRY(fapi2::getScom(i_target,
EQ_SCAN64,
l_data64));
- G_ring_save[l_spin - 1] = l_scandata & l_data64;
+ o_ring_save_data[l_spin - 1] = l_scandata & l_data64;
}
}
@@ -170,7 +165,6 @@ fapi2::ReturnCode p9_quad_power_off(
l_data64));
}
-#endif
FAPI_DBG("Disabling bits 20/22/24/26 in EQ_QPPM_QPMMR_CLEAR, to gain access"
" to PFET controller, otherwise Quad Power off scom will fail");
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
index 9c684aaf..4c6b0065 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_quad_power_off.H
@@ -48,14 +48,10 @@
// Constant definitions
//------------------------------------------------------------------------------
-#ifdef __PPE__
- extern uint64_t G_ring_save[8];
- extern const uint64_t G_ring_index[10];
-#endif
-
// function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode (*p9_quad_power_off_FP_t) (
- const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+ const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+ uint64_t* o_ring_save_data);
extern "C"
{
@@ -66,12 +62,15 @@ extern "C"
/**
** @brief Power off the EQ including the functional cores associatated with it.
**
- ** @param[in] i_target Targe type EQ
+ ** @param[in] i_target Targe type EQ
+ ** @param[out] o_ring_save_data The ring data that tells the PB how to find the
+ ** EQ will need to be saved away for when we p-on
**
** @return FAPI2_RC_SUCCESS if success, error otherwise
**/
fapi2::ReturnCode p9_quad_power_off (
- const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+ const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
+ uint64_t* o_ring_save_data);
} // extern "C"
diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C
index 841c764c..5f60b1d3 100644
--- a/src/sbefw/sbecmdiplcontrol.C
+++ b/src/sbefw/sbecmdiplcontrol.C
@@ -38,7 +38,6 @@
#include "sberegaccess.H"
#include "sbestates.H"
#include "sbecmdcntrldmt.H"
-#include "sbeglobals.H"
#include "fapi2.H"
#include "p9_misc_scom_addresses_fld.H"
@@ -141,6 +140,14 @@ typedef ReturnCode (*sbeIstepHwpSequenceDrtm_t)
(const Target<TARGET_TYPE_PROC_CHIP> & i_target,
uint8_t & o_status);
+typedef ReturnCode (*sbeIstepHwpQuadPoweroff_t)
+ (const Target<TARGET_TYPE_EQ> & i_target,
+ uint64_t * o_ring_save_data);
+
+typedef ReturnCode (*sbeIstepHwpCacheInitf_t)
+ (const Target<TARGET_TYPE_EQ> & i_target,
+ const uint64_t * i_ring_save_data);
+
typedef union
{
sbeIstepHwpProc_t procHwp;
@@ -151,6 +158,8 @@ typedef union
sbeIstepHwpCoreBlockIntr_t coreBlockIntrHwp;
sbeIstepHwpCoreScomState_t coreScomStateHwp;
sbeIstepHwpSequenceDrtm_t procSequenceDrtm;
+ sbeIstepHwpQuadPoweroff_t quadPoweroffHwp;
+ sbeIstepHwpCacheInitf_t cacheInitfHwp;
}sbeIstepHwp_t;
// Wrapper function for HWP IPl functions
@@ -170,6 +179,7 @@ ReturnCode istepWithCoreConditional( sbeIstepHwp_t i_hwp);
ReturnCode istepWithEqConditional( sbeIstepHwp_t i_hwp);
ReturnCode istepNestFreq( sbeIstepHwp_t i_hwp);
ReturnCode istepLpcInit( sbeIstepHwp_t i_hwp);
+ReturnCode istepCacheInitf( sbeIstepHwp_t i_hwp );
//MPIPL Specific
ReturnCode istepWithCoreSetBlock( sbeIstepHwp_t i_hwp );
@@ -183,11 +193,6 @@ ReturnCode istepWithProcSequenceDrtm( sbeIstepHwp_t i_hwp );
ReturnCode istepMpiplSetFunctionalState( sbeIstepHwp_t i_hwp );
ReturnCode istepMpiplQuadPoweroff( sbeIstepHwp_t i_hwp );
ReturnCode istepStopClockMpipl( sbeIstepHwp_t i_hwp );
-// BMC Isteps, No-op in Fsp
-ReturnCode istepMpiplDumpRegs( sbeIstepHwp_t i_hwp );
-ReturnCode istepMpiplQueryQuadAccessState( sbeIstepHwp_t i_hwp );
-ReturnCode istepMpiplHcdCoreStopClocks( sbeIstepHwp_t i_hwp );
-ReturnCode istepMpiplHcdCacheStopClocks( sbeIstepHwp_t i_hwp );
// Utility function to do TPM reset
ReturnCode performTpmReset();
@@ -220,7 +225,11 @@ static const uint64_t N3_FIR_SYSTEM_CHECKSTOP_BIT = 33;
// Globals
// TODO: via RTC 123602 This global needs to move to a class that will store the
// SBE FFDC.
-static fapi2::ReturnCode g_iplFailRc = FAPI2_RC_SUCCESS;
+fapi2::ReturnCode g_iplFailRc = FAPI2_RC_SUCCESS;
+
+uint64_t G_ring_save[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+sbeRole g_sbeRole = SBE_ROLE_MASTER;
static istepMap_t g_istepMpiplStartPtrTbl[MPIPL_START_MAX_SUBSTEPS] =
{
@@ -252,16 +261,8 @@ static istepMap_t g_istepMpiplContinuePtrTbl[MPIPL_CONTINUE_MAX_SUBSTEPS] =
#ifdef SEEPROM_IMAGE
// Setup EC/EQ guard records
{ &istepMpiplSetFunctionalState, NULL},
- // Collect master quad regs, BMC Only istep, No-op in FSP
- { &istepMpiplDumpRegs, NULL},
- // Query Master quad, BMC Only istep, No-op in Fsp
- { &istepMpiplQueryQuadAccessState, NULL},
- // Master Quad Core stop clocks, BMC Only istep, No-op in Fsp
- { &istepMpiplHcdCoreStopClocks, NULL},
- // Master Quad Cache stop clocks, BMC Only istep, No-op in Fsp
- { &istepMpiplHcdCacheStopClocks, NULL},
// p9_quad_power_off
- { istepMpiplQuadPoweroff, { .eqHwp = &p9_quad_power_off} },
+ { istepMpiplQuadPoweroff, { .quadPoweroffHwp = &p9_quad_power_off} },
// No-op
{ &istepNoOp, NULL},
#endif
@@ -341,7 +342,7 @@ static istepMap_t g_istep4PtrTbl[ ISTEP4_MAX_SUBSTEPS ] =
{ &istepWithEq, { .eqHwp = &p9_hcd_cache_arrayinit }},
{ &istepNoOp, NULL }, // DFT Only
{ &istepNoOp, NULL }, // DFT Only
- { &istepWithEq, { .eqHwp = &p9_hcd_cache_initf }},
+ { &istepCacheInitf, { .cacheInitfHwp = &p9_hcd_cache_initf }},
{ &istepWithEqConditional, { .eqHwp = &p9_hcd_cache_startclocks }},
{ &istepWithEqConditional, { .eqHwp = &p9_hcd_cache_scominit }},
{ &istepWithEqConditional, { .eqHwp = &p9_hcd_cache_scomcust }},
@@ -552,7 +553,7 @@ bool validateIstep (const uint8_t i_major, const uint8_t i_minor)
case SBE_ISTEP3:
if( (i_minor > ISTEP3_MAX_SUBSTEPS ) ||
- ((SBE_ROLE_SLAVE == SBE_GLOBAL->SBERole) &&
+ ((SBE_ROLE_SLAVE == g_sbeRole) &&
(i_minor > SLAVE_LAST_MINOR_ISTEP)) )
{
valid = false;
@@ -561,7 +562,7 @@ bool validateIstep (const uint8_t i_major, const uint8_t i_minor)
case SBE_ISTEP4:
if( (i_minor > ISTEP4_MAX_SUBSTEPS ) ||
- (SBE_ROLE_SLAVE == SBE_GLOBAL->SBERole) )
+ (SBE_ROLE_SLAVE == g_sbeRole) )
{
valid = false;
}
@@ -569,7 +570,7 @@ bool validateIstep (const uint8_t i_major, const uint8_t i_minor)
case SBE_ISTEP5:
if( (i_minor > ISTEP5_MAX_SUBSTEPS ) ||
- (SBE_ROLE_SLAVE == SBE_GLOBAL->SBERole) )
+ (SBE_ROLE_SLAVE == g_sbeRole) )
{
valid = false;
}
@@ -683,8 +684,6 @@ ReturnCode istepSelectEx( sbeIstepHwp_t i_hwp)
}
//----------------------------------------------------------------------------
-
-
ReturnCode istepWithEq( sbeIstepHwp_t i_hwp)
{
ReturnCode rc = FAPI2_RC_SUCCESS;
@@ -708,6 +707,30 @@ ReturnCode istepWithEq( sbeIstepHwp_t i_hwp)
}
//----------------------------------------------------------------------------
+ReturnCode istepCacheInitf (sbeIstepHwp_t i_hwp )
+{
+ #define SBE_FUNC "istepCacheInitf"
+ SBE_ENTER(SBE_FUNC);
+ ReturnCode l_rc = FAPI2_RC_SUCCESS;
+
+ // TODO via RTC 135345
+ fapi2::Target<fapi2::TARGET_TYPE_EQ > eqTgt;
+ // Put this in scope so that vector can be freed up before calling hwp.
+ {
+ Target<TARGET_TYPE_PROC_CHIP > proc = plat_getChipTarget();
+ auto eqList = proc.getChildren<fapi2::TARGET_TYPE_EQ>();
+ // As it is workaround lets assume there will always be atleast one
+ // functional eq. No need to validate.
+ eqTgt = eqList[0];
+ }
+
+ SBE_EXEC_HWP(l_rc, i_hwp.cacheInitfHwp, eqTgt, G_ring_save)
+ SBE_EXIT(SBE_FUNC);
+ return l_rc;
+ #undef SBE_FUNC
+}
+
+//----------------------------------------------------------------------------
ReturnCode istepWithCore( sbeIstepHwp_t i_hwp)
{
@@ -819,10 +842,10 @@ ReturnCode istepCheckSbeMaster( sbeIstepHwp_t i_hwp)
SBE_ERROR(SBE_FUNC" performTpmReset failed");
break;
}
- SBE_GLOBAL->SBERole = SbeRegAccess::theSbeRegAccess().isSbeSlave() ?
+ g_sbeRole = SbeRegAccess::theSbeRegAccess().isSbeSlave() ?
SBE_ROLE_SLAVE : SBE_ROLE_MASTER;
- SBE_INFO(SBE_FUNC"SBE_GLOBAL->SBERole [%x]", SBE_GLOBAL->SBERole);
- if(SBE_ROLE_SLAVE == SBE_GLOBAL->SBERole)
+ SBE_INFO(SBE_FUNC"g_sbeRole [%x]", g_sbeRole);
+ if(SBE_ROLE_SLAVE == g_sbeRole)
{
(void)SbeRegAccess::theSbeRegAccess().stateTransition(
SBE_RUNTIME_EVENT);
@@ -890,7 +913,7 @@ void sbeDoContinuousIpl()
// Check if we are at step 3.20 on the slave SBE
if(((SBE_ISTEP_LAST_SLAVE == l_major) &&
(SLAVE_LAST_MINOR_ISTEP == l_minor)) &&
- (SBE_ROLE_SLAVE == SBE_GLOBAL->SBERole))
+ (SBE_ROLE_SLAVE == g_sbeRole))
{
l_done = true;
break;
@@ -1121,7 +1144,7 @@ ReturnCode istepMpiplQuadPoweroff( sbeIstepHwp_t i_hwp)
#define SBE_FUNC "istepMpiplQuadPoweroff"
SBE_ENTER(SBE_FUNC);
ReturnCode l_rc = FAPI2_RC_SUCCESS;
- if(SBE_GLOBAL->SBERole == SBE_ROLE_MASTER)
+ if(g_sbeRole == SBE_ROLE_MASTER)
{
Target<TARGET_TYPE_PROC_CHIP > l_proc = plat_getChipTarget();
// Fetch the MASTER_CORE attribute
@@ -1133,7 +1156,7 @@ ReturnCode istepMpiplQuadPoweroff( sbeIstepHwp_t i_hwp)
l_coreId + CORE_CHIPLET_OFFSET));
fapi2::Target<fapi2::TARGET_TYPE_EQ> l_quad =
l_core.getParent<fapi2::TARGET_TYPE_EQ>();
- SBE_EXEC_HWP(l_rc, i_hwp.eqHwp, l_quad)
+ SBE_EXEC_HWP(l_rc, i_hwp.quadPoweroffHwp, l_quad, G_ring_save)
}
SBE_EXIT(SBE_FUNC);
return l_rc;
@@ -1328,35 +1351,3 @@ ReturnCode istepStopClockMpipl( sbeIstepHwp_t i_hwp )
#undef SBE_FUNC
}
-// BMC - Istep
-ReturnCode istepMpiplDumpRegs( sbeIstepHwp_t i_hwp )
-{
- #define SBE_FUNC "istepMpiplDumpRegs"
- return FAPI2_RC_SUCCESS;
- #undef SBE_FUNC
-}
-//----------------------------------------------------------------------------
-// BMC - Istep
-ReturnCode istepMpiplQueryQuadAccessState( sbeIstepHwp_t i_hwp )
-{
- #define SBE_FUNC "istepMpiplQueryQuadAccessState"
- return FAPI2_RC_SUCCESS;
- #undef SBE_FUNC
-}
-//----------------------------------------------------------------------------
-// BMC - Istep
-ReturnCode istepMpiplHcdCoreStopClocks( sbeIstepHwp_t i_hwp )
-{
- #define SBE_FUNC "istepMpiplHcdCoreStopClocks"
- return FAPI2_RC_SUCCESS;
- #undef SBE_FUNC
-}
-//----------------------------------------------------------------------------
-// BMC - Istep
-ReturnCode istepMpiplHcdCacheStopClocks( sbeIstepHwp_t i_hwp )
-{
- #define SBE_FUNC "istepMpiplHcdCacheStopClocks"
- return FAPI2_RC_SUCCESS;
- #undef SBE_FUNC
-}
-//----------------------------------------------------------------------------
diff --git a/src/sbefw/sbecmdiplcontrol.H b/src/sbefw/sbecmdiplcontrol.H
index 0895cad6..d19baf09 100644
--- a/src/sbefw/sbecmdiplcontrol.H
+++ b/src/sbefw/sbecmdiplcontrol.H
@@ -56,8 +56,8 @@ static const uint32_t SBE_ISTEP_MPIPL_START = 96;
static const uint32_t SBE_ISTEP_MPIPL_CONTINUE = 97;
static const uint32_t SBE_ISTEP_STOPCLOCK = 98;
static const uint32_t MPIPL_START_MAX_SUBSTEPS = 8;
+static const uint32_t MPIPL_CONTINUE_MAX_SUBSTEPS = 3;
static const uint32_t ISTEP_STOPCLOCK_MAX_SUBSTEPS = 1;
-static const uint32_t MPIPL_CONTINUE_MAX_SUBSTEPS = 7;
// constants
static const uint32_t ISTEP2_MAX_SUBSTEPS = 17;
@@ -68,6 +68,9 @@ static const uint8_t ISTEP_MINOR_START = 1;
static const uint8_t SLAVE_LAST_MINOR_ISTEP = 20;
static const uint8_t ISTEP2_MINOR_START = 2;
+extern uint64_t G_ring_save[8];
+extern const uint64_t G_ring_index[10];
+
/**
* @brief Support function to execute specific istep
*
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