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| author | Claus Michael Olsen <cmolsen@us.ibm.com> | 2017-11-13 13:53:08 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-11-16 20:12:01 -0500 |
| commit | 348d8d20dc496cb5e8cf4326a4f9cf5fb81f98e2 (patch) | |
| tree | ea46c6a3e1b14698dcdc59a4080d211e8986b1f1 /src/import/chips | |
| parent | 722d8a4cdb59ba19c1828cfde061335cad6e13a4 (diff) | |
| download | talos-sbe-348d8d20dc496cb5e8cf4326a4f9cf5fb81f98e2.tar.gz talos-sbe-348d8d20dc496cb5e8cf4326a4f9cf5fb81f98e2.zip | |
HW425038 INT ARX timeout workaround - Updated initfiles to 49241
Change-Id: I42a3601917ab4d4b32b32e03d33ffa1f8c0da25f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49608
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Dev-Ready: Kahn C. Evans <kahnevan@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49621
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 36 |
1 files changed, 33 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 382e306c..d29bad2d 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -5575,10 +5575,40 @@ </ec> </chip> </chipEcFeature> +</attribute> + <!-- ******************************************************************** --> + <!-- NOTE: This attribute is used in an initfile to qualify the contents + of a GPTR ring. There is special processing in place to move the + GPTR content into the OVERLAYS section for Nimbus DD2+ and + Cumulus systems, due to this additional special processing + two attributes are required. DD2+ GPTR ring content should + be placed in p9.xx.gptr.scan.overlays.initfiles --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW407330_DD2</id>> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1/DD2: State Latches for Atomic CAS during ntl fence don't get reset. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> </attribute> + <!-- ******************************************************************** --> + <!-- NOTE: This attribute is used in an initfile to qualify the contents + of a GPTR ring. There is special processing in place to move the + GPTR content into the OVERLAYS section for Nimbus DD2+ and + Cumulus systems, due to this additional special processing + two attributes are required. DD1 GPTR ring content should + be placed in p9.xx.gptr.scan.initfiles --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_HW407330</id>> + <id>ATTR_CHIP_EC_FEATURE_HW407330_DD1</id>> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> Nimbus DD1/DD2: State Latches for Atomic CAS during ntl fence don't get reset. @@ -5587,8 +5617,8 @@ <chip> <name>ENUM_ATTR_NAME_NIMBUS</name> <ec> - <value>0x21</value> - <test>LESS_THAN</test> + <value>0x10</value> + <test>EQUAL</test> </ec> </chip> </chipEcFeature> |
