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author | Alvin Wang <wangat@tw.ibm.com> | 2019-01-14 00:18:01 -0600 |
---|---|---|
committer | RAJA DAS <rajadas2@in.ibm.com> | 2019-07-30 13:56:00 -0500 |
commit | 0bb6050f327837045cfd3e573b19020b63b07d16 (patch) | |
tree | c0c3fd65bdce9eba695fa7e53f596844897bb46b /src/import/chips/p9 | |
parent | 3624a9930d432d58634fcce5b68863c6c3cc6e1a (diff) | |
download | talos-sbe-0bb6050f327837045cfd3e573b19020b63b07d16.tar.gz talos-sbe-0bb6050f327837045cfd3e573b19020b63b07d16.zip |
Adds p9a_omi_train procedure(START)
Change-Id: Iafa88363b862e9175982836f1686199e9366d555
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69721
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81259
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
3 files changed, 124 insertions, 2 deletions
diff --git a/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fixes.H index c391d44e..c113d3bc 100644 --- a/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fixes.H +++ b/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fixes.H @@ -22,3 +22,29 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file p9a_mc_scom_addresses_fixed.H +/// @brief Defines constants for scom addresses +/// +// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: SOA +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE + + +#ifndef __P9A_MC_SCOM_ADDRESSES_FIXES_H +#define __P9A_MC_SCOM_ADDRESSES_FIXES_H + +static const uint64_t P9A_MC_REG2_DL0_ERROR_ACTION = 0x070133DDull; + +static const uint64_t P9A_MC_REG2_DL0_RMT_CONFIG = 0x070133D8ull; + +static const uint64_t P9A_MC_REG0_CMN_CONFIG = 0x0701334Eull; + +static const uint64_t P9A_MC_REG1_CMN_CONFIG = 0x0701338Eull; + +static const uint64_t P9A_MC_REG2_CMN_CONFIG = 0x070133CEull; + +#endif diff --git a/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld.H index 8077ee51..9de5808d 100644 --- a/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld.H +++ b/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld.H @@ -4059,8 +4059,8 @@ static const uint8_t P9A_MC_REG2_DL0_CONFIG0_CFG_RETRAIN = 6 static const uint8_t P9A_MC_REG2_DL0_CONFIG0_CFG_RESET = 63 ; static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_CFG1_SPARE = 0 ; -static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_CFG1_SPARE_LEN = 6 ; -static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH = 6 ; +static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_CFG1_SPARE_LEN = 2 ; +static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH = 2 ; static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH_LEN = 2 ; static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS = 8 ; static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN = 4 ; diff --git a/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld_fixes.H index deeb9226..acf77368 100644 --- a/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld_fixes.H +++ b/src/import/chips/p9/common/include/p9a_mc_scom_addresses_fld_fixes.H @@ -22,3 +22,99 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file p9a_mc_scom_addresses_fld_fixes.H +/// @brief Defines constants for scom addresses +/// +// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com> +// *HWP FW Owner: Thi Tran <thi@us.ibm.com> +// *HWP Team: SOA +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE + + +#ifndef __P9A_MC_SCOM_ADDRESSES_FLD_FIXES_H +#define __P9A_MC_SCOM_ADDRESSES_FLD_FIXES_H + +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_CONST = 0; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_CONST_LEN = 16; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR11_ACTION = 16; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR11_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR10_ACTION = 20; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR10_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR9_ACTION = 24; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR9_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR8_ACTION = 28; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR8_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR7_ACTION = 32; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR7_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR6_ACTION = 36; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR6_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR5_ACTION = 40; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR5_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR4_ACTION = 44; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR4_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR3_ACTION = 48; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR3_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR2_ACTION = 52; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR2_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR1_ACTION = 56; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR1_ACTION_LEN = 4; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR0_ACTION = 60; +static const uint8_t P9A_MC_REG2_DL0_ERROR_ACTION_FIR0_ACTION_LEN = 4; + +static const uint8_t P9A_MC_REG2_DL0_RMT_CONFIG_CONST = 0; +static const uint8_t P9A_MC_REG2_DL0_RMT_CONFIG_CONST_LEN = 32; +static const uint8_t P9A_MC_REG2_DL0_RMT_CONFIG_CFG_DLX2 = 32; +static const uint8_t P9A_MC_REG2_DL0_RMT_CONFIG_CFG_DLX2_LEN = 32; + +static const uint8_t P9A_MC_REG0_CMN_CONFIG_SPARE = 0; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_SPARE_LEN = 4; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PM_CDR_TIMER = 4; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PM_CDR_TIMER_LEN = 4; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PM_DIDT_TIMER = 8; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PM_DIDT_TIMER_LEN = 4; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PSAV_STS_ENABLE = 12; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_RECAL_TIMER = 13; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_RECAL_TIMER_LEN = 3; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR = 16; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR_LEN = 12; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CFG_CMN_DBG_EN = 28; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_DBG_SEL = 29; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_DBG_SEL_LEN = 3; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_RD_RST = 32; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PRE_SCALAR = 33; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PRE_SCALAR_LEN = 3; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CFG_CMN_FREEZE = 36; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PORT_SEL = 37; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_PORT_SEL_LEN = 3; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR3_PS = 40; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR3_PS_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR3_ES = 42; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR3_ES_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR2_PS = 44; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR2_PS_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR2_ES = 46; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR2_ES_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR1_PS = 48; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR1_PS_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR1_ES = 50; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR1_ES_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR0_PS = 52; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR0_PS_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR0_ES = 54; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR0_ES_LEN = 2; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR3_PE = 56; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR2_PE = 57; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR1_PE = 58; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR0_PE = 59; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR3_EN = 60; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR2_EN = 61; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR1_EN = 62; +static const uint8_t P9A_MC_REG0_CMN_CONFIG_CNTR0_EN = 63; + +static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA = 4; +static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME = 5; +static const uint8_t P9A_MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN = 3; + +#endif |