PM: Delete deprecated attributes

- Complete the move to platform SYSTEM_*_DISABLED and HWP *_ENABLED attributes
- Added VDM DPLL response attribute to CME header mapping
- Updated review comments

Change-Id: If8f8e42fd94825623315e8a7c28105cca8c8c8b2
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42918
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42919
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

5 files changed, 425 insertions, 110 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
index 0f155e64..e97c9082 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
@@ -78,7 +78,7 @@ p9_hcd_cache_stopclocks(
     uint32_t                                       l_loops1ms                  = 0;
     uint32_t                                       l_scom_addr                 = 0;
     uint8_t                                        l_attr_chip_unit_pos        = 0;
-    uint8_t                                        l_attr_vdm_enable           = 0;
+    uint8_t                                        l_attr_vdm_enabled           = 0;
     uint8_t                                        l_is_mpipl                  = 0;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     auto l_perv = i_target.getParent<fapi2::TARGET_TYPE_PERV>();
@@ -135,8 +135,8 @@ p9_hcd_cache_stopclocks(
         FAPI_TRY(fapi2::putScom(i_target, EQ_QPPM_QCCR_SCOM1, l_data64));
     }
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE,    l_sys,
-                           l_attr_vdm_enable));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLED, l_chip,
+                           l_attr_vdm_enabled));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
                            l_attr_chip_unit_pos));
 //  l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET;
@@ -263,7 +263,7 @@ p9_hcd_cache_stopclocks(
     // Disable VDM
     // -------------------------------
 
-    if (l_attr_vdm_enable == fapi2::ENUM_ATTR_VDM_ENABLE_ON)
+    if (l_attr_vdm_enabled == fapi2::ENUM_ATTR_VDM_ENABLED_TRUE)
     {
         FAPI_DBG("Clear Jump Protect Enable via DPLL_CTRL[1] (no need to poll DPLL_STAT)");
         FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(1)));
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
index 892d3b45..0b72b51e 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
@@ -74,7 +74,7 @@ p9_hcd_core_stopclocks(
     fapi2::buffer<uint64_t>                        l_temp64;
     uint32_t                                       l_loops1ms;
     uint8_t                                        l_attr_chip_unit_pos;
-    uint8_t                                        l_attr_vdm_enable;
+    uint8_t                                        l_attr_vdm_enabled;
     uint8_t                                        l_attr_sdisn_setup;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     auto  l_quad = i_target.getParent<fapi2::TARGET_TYPE_EQ>();
@@ -84,8 +84,8 @@ p9_hcd_core_stopclocks(
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, l_chip,
                            l_attr_sdisn_setup));
 
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE,       l_sys,
-                           l_attr_vdm_enable));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLED,      l_chip,
+                           l_attr_vdm_enabled));
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,    l_perv,
                            l_attr_chip_unit_pos));
     l_attr_chip_unit_pos = (l_attr_chip_unit_pos -
@@ -240,7 +240,7 @@ p9_hcd_core_stopclocks(
     // Disable VDM
     // -------------------------------
 
-    if (l_attr_vdm_enable == fapi2::ENUM_ATTR_VDM_ENABLE_ON)
+    if (l_attr_vdm_enabled == fapi2::ENUM_ATTR_VDM_ENABLED_TRUE)
     {
         FAPI_DBG("Set VDM Disable via CPPM_VDMCR[1]");
         FAPI_TRY(putScom(i_target, C_PPM_VDMCR_OR, MASK_SET(1)));
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index e6d68e9f..83a6d1aa 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -319,7 +319,7 @@
            <value>0x0</value>
   </entry>
   <entry>
-           <name>ATTR_VDM_ENABLE</name>
+           <name>ATTR_VDM_ENABLED</name>
            <value>0x0</value>
   </entry>
   <entry>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml
new file mode 100644
index 00000000..15b6c3aa
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml
@@ -0,0 +1,416 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2017                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<attributes>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PROC_DPLL_DIVIDER</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>The product of the DPLL internal prescalar divide
+      (CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC).  This estalishes
+      the step size of the DPLL in terms of this number divided into the
+      processor reference clock.
+
+      if 0, consuming procedures will assume a default of 8.
+
+      Provided to override default value
+      </description>
+      <valueType>uint32</valueType>
+      <writeable/>
+      <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>Set by p9_hcode_image build with the offset value from
+      the HOMER base where the SGPE Boot Copier interrupt vectors reside.  This
+      value must be 512B aligned. The HOMER base address will be pre-establish
+      in PBABAR0 so the address needs to be off the form  0x8XXXXX00. The SGPE
+      will be Sreset after this value is established.
+      </description>
+      <valueType>uint32</valueType>
+      <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>Set by p9_hcode_image build with the offset value from
+      the HOMER base where the PGPE Boot Copier interrupt vectors reside. This
+      value must be 512B aligned. The HOMER base address will be pre-establish
+      in PBABAR0 so the address needs to be off the form  0x8XXXXX00. The PGPE
+      will be Sreset after this value is established
+      </description>
+      <valueType>uint32</valueType>
+      <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>Flag storage to have the Special Wakeup procedure ignore a
+      checkstop condition.
+      </description>
+      <valueType>uint8</valueType>
+      <initToZero/>
+      <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_OCC_LFIR</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>The attribute stores the Local FIR value of OCC taken
+      during the reset phase.
+      </description>
+      <valueType>uint32</valueType>
+      <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PBA_LFIR</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>The attribute stores the Local FIR value of PBA taken
+      during the reset phase.
+      </description>
+      <valueType>uint32</valueType>
+      <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_PM_FIRINIT_DONE_ONCE_FLAG</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+      0 = OCC has never been loaded and FIR Masks have never been initialized,
+      1 = FIR masks have been initialized and the hardware should reflect
+          correct values,
+      2 = FIR masks have been initialized but the current hardware state is the
+          reset value
+      </description>
+      <valueType>uint8</valueType>
+      <initToZero/>
+      <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_QUAD_PPM_ERRMASK</id>
+       <targetType>TARGET_TYPE_EQ</targetType>
+       <description>The error mask value that has to be restored to the PPM
+       ERRMASK register for the Quad. This value will be stored during the
+       reset phase when the ERRMASK will be cleared as part of the
+       cleanup action.
+       </description>
+       <valueType>uint32</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_CORE_PPM_ERRMASK</id>
+       <targetType>TARGET_TYPE_CORE</targetType>
+       <description>The error mask value that has to be restored to the PPM
+       ERRMASK register for the CORE. This value will be stored during the
+       reset phase when the ERRMASK will be cleared as part of the
+       cleanup action.
+       </description>
+       <valueType>uint32</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_CME_LOCAL_FIRMASK</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>The FIR mask value that has to be restored to the CME FIR
+       register. This value will be stored during the reset phase when the
+       FIRMASK will be cleared as part of the cleanup action.
+       </description>
+       <valueType>uint32</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_L2_HASCLOCKS</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates the L2 region has clocks running and scommable
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_L3_HASCLOCKS</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates the L3 region has clocks running and scommable
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_C0_EXEC_HASCLOCKS</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates the execution units in core 0 have clocks running
+       and scommable
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_C1_EXEC_HASCLOCKS</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates the execution units in core 1 have clocks running
+       and scommable
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_C0_PC_HASCLOCKS</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates the core pervasive unit in core 0 has clocks
+       running and scommable
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_C1_PC_HASCLOCKS</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates the core pervasive unit in core 1 has clocks
+       running and scommable
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_L2_HASPOWER</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates L2 has power and has valid latch state that could
+       be scanned
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_L3_HASPOWER</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates L3 has power and has valid latch state that could
+       be scanned
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_C0_HASPOWER</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates core 0 has power and has valid latch state that
+       could be scanned
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+       <id>ATTR_C1_HASPOWER</id>
+       <targetType>TARGET_TYPE_EX</targetType>
+       <description>Indicates core 1 has power and has valid latch state that
+       could be scanned
+       </description>
+       <valueType>uint8</valueType>
+       <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_SPIPSS_FRAME_SIZE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Number of data bits per individual SPIPSS transaction
+      (also referred to as frame) during chip select assertion.
+      Supported values: 0x20 (32d)
+      Chip Select assertion duration is frame_size + 2
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_SPIPSS_IN_DELAY</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Number of SPI clocks after chip select to wait before capturing
+      MISO input.
+      Supported values: 0x000 to spi_frame_size.
+      Values beyond spi_frame_size result in the input not being captured
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      SPIPSS Clock Polarity
+      CPOL=0 means that clk idle is deasserted,
+      CPOH=1 means that clk idle is asserted
+    </description>
+    <valueType>uint8</valueType>
+    <enum>CPOL=0, CPOH=1</enum>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      SPIPSS clock phase
+      CPHA=0 means to change/sample values of data signals on first edge,
+      otherwise on 2nd
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FIRSTEDGE=0, SECONDEDGE=1</enum>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      SPI clock speed divider to divide the nest_nclk/4 mesh clock,
+      which results in a divider = ((nest_freq / (SPI_freq*8)) - 1)
+    </description>
+    <valueType>uint16</valueType>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Delay is computed as:
+      (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time
+      0x00000: Wait 1 PSS Clock
+      0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses
+      For values greater than 0x00000, the actual delay is 1 PSS Clock +
+      the time delay designated by the value defined.
+      Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle.
+    </description>
+    <valueType>uint32</valueType>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PSTATES_ENABLED</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Indicator that all relevant attributes and required data for
+    Pstates to be enabled is present and valid
+
+    Producer: p9_build_pstate_datablock
+
+    Consumers: p9_pm_pstate_gpe_init
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE=0, TRUE=1</enum>
+    <writeable/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_RESCLK_ENABLED</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Indicator that all relevant attributes and required data for
+    Resonant Clocking to be enabled is present and valid
+
+    Producer: p9_build_pstate_datablock
+
+    Consumers: p9_hcode_image_build ->
+                      PGPE Header
+                      CME Header
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE=0, TRUE=1</enum>
+    <writeable/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VDM_ENABLED</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Indicator that all relevant attributes and required data for
+    Voltage Droop Monitors (VDM) to be enabled is present and valid
+
+    Producer: p9_build_pstate_datablock
+
+    Consumers: p9_hcode_image_build ->
+                      SGPE Header
+                      CME Header
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE=0, TRUE=1</enum>
+    <writeable/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_IVRM_ENABLED</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Indicator that all relevant attributes and required data for
+    Internal Voltage Regulator Macros (IVRMs) to be enabled is present and valid
+
+    Producer: p9_build_pstate_datablock
+
+    Consumers: p9_hcode_image_build ->
+                      PGPE Header
+                      CME Header
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE=0, TRUE=1</enum>
+    <writeable/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_WOF_ENABLED</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Indicator that all relevent attributes and required data for
+    WOF to be enabled is present and valid
+
+    Producer: p9_build_pstate_datablock
+
+    Consumers: p9_hcode_image_build ->
+                      PGPE Header
+                      CME Header
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE=0, TRUE=1</enum>
+    <writeable/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
index 09ead340..e529ecb2 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
@@ -900,20 +900,6 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_SYSTEM_WOF_ENABLED</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <description>
-    <!-- @todo RTC 173736 -->
-    !!!!! Deprecated for ATTR_SYSTEM_WOF_DISABLE
-    !!!!! Will be removed in the future
-    </description>
-    <valueType>uint8</valueType>
-    <enum>FALSE=0, TRUE=1</enum>
-    <platInit/>
-    <initToZero/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
     <id>ATTR_SYSTEM_WOF_DISABLE</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>Disables Work Load Optimized Frequency (WOF) algorithms to
@@ -939,20 +925,6 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-    <id>ATTR_SYSTEM_IVRMS_ENABLED</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
-    <!-- @todo RTC 173736 -->
-    <description>
-    !!!!! Deprecated for ATTR_SYSTEM_IVRM_DISABLE
-    !!!!! Will be removed in the future
-    </description>
-    <valueType>uint8</valueType>
-    <enum>FALSE=0, TRUE=1</enum>
-    <platInit/>
-    <initToZero/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
     <id>ATTR_SYSTEM_IVRM_DISABLE</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>Disables IVRM enablement in the system
@@ -1168,20 +1140,6 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-      <id>ATTR_VDM_ENABLE</id>
-      <targetType>TARGET_TYPE_SYSTEM</targetType>
-      <!-- @todo RTC 173736 -->
-      <description>
-      !!!!! Deprecated for ATTR_SYSTEM_VDM_ENABLE
-      !!!!! Will be removed in the future
-      </description>
-      <valueType>uint8</valueType>
-      <enum>OFF = 0x00, ON = 0x01</enum>
-      <initToZero/>
-      <platInit/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
       <id>ATTR_SYSTEM_VDM_DISABLE</id>
       <targetType>TARGET_TYPE_SYSTEM</targetType>
       <description>
@@ -1513,51 +1471,6 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-      <id>ATTR_DPLL_DYNAMIC_FMAX_ENABLE</id>
-      <description>
-        !!!!! Deprecated for ATTR_DPLL_VDM_RESPONSE
-        !!!!! Will be removed in the future
-      </description>
-      <targetType>TARGET_TYPE_SYSTEM</targetType>
-      <valueType>uint8</valueType>
-      <enum>
-          OFF = 0x00,ON = 0x01
-      </enum>
-      <initToZero/>
-      <platInit/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
-      <id>ATTR_DPLL_DYNAMIC_FMIN_ENABLE</id>
-      <description>
-        !!!!! Deprecated for ATTR_DPLL_VDM_RESPONSE
-        !!!!! Will be removed in the future
-      </description>
-      <targetType>TARGET_TYPE_SYSTEM</targetType>
-      <valueType>uint8</valueType>
-      <enum>
-          OFF = 0x00,ON = 0x01
-      </enum>
-      <initToZero/>
-      <platInit/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
-      <id>ATTR_DPLL_DROOP_PROTECT_ENABLE</id>
-      <description>
-        !!!!! Deprecated for ATTR_DPLL_VDM_RESPONSE
-        !!!!! Will be removed in the future
-      </description>
-      <targetType>TARGET_TYPE_SYSTEM</targetType>
-      <valueType>uint8</valueType>
-      <enum>
-          OFF = 0x00,ON = 0x01
-      </enum>
-      <platInit/>
-      <initToZero/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
       <id>ATTR_DPLL_VDM_RESPONSE</id>
       <targetType>TARGET_TYPE_SYSTEM</targetType>
       <description>
@@ -1719,20 +1632,6 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
-      <id>ATTR_SYSTEM_RESCLK_ENABLE</id>
-      <targetType>TARGET_TYPE_SYSTEM</targetType>
-      <description>
-      <!-- @todo RTC 173736 -->
-      !!!!! Deprecated for ATTR_SYSTEM_RESCLK_DISABLE
-      !!!!! Will be removed in the future
-      </description>
-      <valueType>uint8</valueType>
-      <enum>OFF = 0x00, ON = 0x01</enum>
-      <initToZero/>
-      <platInit/>
-  </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
       <id>ATTR_SYSTEM_RESCLK_DISABLE</id>
       <targetType>TARGET_TYPE_SYSTEM</targetType>
       <description>