diff options
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml | 416 |
1 files changed, 416 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml new file mode 100644 index 00000000..15b6c3aa --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml @@ -0,0 +1,416 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2017 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_DPLL_DIVIDER</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>The product of the DPLL internal prescalar divide + (CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC). This estalishes + the step size of the DPLL in terms of this number divided into the + processor reference clock. + + if 0, consuming procedures will assume a default of 8. + + Provided to override default value + </description> + <valueType>uint32</valueType> + <writeable/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Set by p9_hcode_image build with the offset value from + the HOMER base where the SGPE Boot Copier interrupt vectors reside. This + value must be 512B aligned. The HOMER base address will be pre-establish + in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The SGPE + will be Sreset after this value is established. + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Set by p9_hcode_image build with the offset value from + the HOMER base where the PGPE Boot Copier interrupt vectors reside. This + value must be 512B aligned. The HOMER base address will be pre-establish + in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The PGPE + will be Sreset after this value is established + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Flag storage to have the Special Wakeup procedure ignore a + checkstop condition. + </description> + <valueType>uint8</valueType> + <initToZero/> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_OCC_LFIR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>The attribute stores the Local FIR value of OCC taken + during the reset phase. + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PBA_LFIR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>The attribute stores the Local FIR value of PBA taken + during the reset phase. + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_FIRINIT_DONE_ONCE_FLAG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + 0 = OCC has never been loaded and FIR Masks have never been initialized, + 1 = FIR masks have been initialized and the hardware should reflect + correct values, + 2 = FIR masks have been initialized but the current hardware state is the + reset value + </description> + <valueType>uint8</valueType> + <initToZero/> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_QUAD_PPM_ERRMASK</id> + <targetType>TARGET_TYPE_EQ</targetType> + <description>The error mask value that has to be restored to the PPM + ERRMASK register for the Quad. This value will be stored during the + reset phase when the ERRMASK will be cleared as part of the + cleanup action. + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CORE_PPM_ERRMASK</id> + <targetType>TARGET_TYPE_CORE</targetType> + <description>The error mask value that has to be restored to the PPM + ERRMASK register for the CORE. This value will be stored during the + reset phase when the ERRMASK will be cleared as part of the + cleanup action. + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CME_LOCAL_FIRMASK</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>The FIR mask value that has to be restored to the CME FIR + register. This value will be stored during the reset phase when the + FIRMASK will be cleared as part of the cleanup action. + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_L2_HASCLOCKS</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates the L2 region has clocks running and scommable + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_L3_HASCLOCKS</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates the L3 region has clocks running and scommable + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_C0_EXEC_HASCLOCKS</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates the execution units in core 0 have clocks running + and scommable + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_C1_EXEC_HASCLOCKS</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates the execution units in core 1 have clocks running + and scommable + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_C0_PC_HASCLOCKS</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates the core pervasive unit in core 0 has clocks + running and scommable + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_C1_PC_HASCLOCKS</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates the core pervasive unit in core 1 has clocks + running and scommable + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_L2_HASPOWER</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates L2 has power and has valid latch state that could + be scanned + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_L3_HASPOWER</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates L3 has power and has valid latch state that could + be scanned + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_C0_HASPOWER</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates core 0 has power and has valid latch state that + could be scanned + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_C1_HASPOWER</id> + <targetType>TARGET_TYPE_EX</targetType> + <description>Indicates core 1 has power and has valid latch state that + could be scanned + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_SPIPSS_FRAME_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Number of data bits per individual SPIPSS transaction + (also referred to as frame) during chip select assertion. + Supported values: 0x20 (32d) + Chip Select assertion duration is frame_size + 2 + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_SPIPSS_IN_DELAY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Number of SPI clocks after chip select to wait before capturing + MISO input. + Supported values: 0x000 to spi_frame_size. + Values beyond spi_frame_size result in the input not being captured + </description> + <valueType>uint8</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + SPIPSS Clock Polarity + CPOL=0 means that clk idle is deasserted, + CPOH=1 means that clk idle is asserted + </description> + <valueType>uint8</valueType> + <enum>CPOL=0, CPOH=1</enum> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + SPIPSS clock phase + CPHA=0 means to change/sample values of data signals on first edge, + otherwise on 2nd + </description> + <valueType>uint8</valueType> + <enum>FIRSTEDGE=0, SECONDEDGE=1</enum> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + SPI clock speed divider to divide the nest_nclk/4 mesh clock, + which results in a divider = ((nest_freq / (SPI_freq*8)) - 1) + </description> + <valueType>uint16</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Delay is computed as: + (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time + 0x00000: Wait 1 PSS Clock + 0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses + For values greater than 0x00000, the actual delay is 1 PSS Clock + + the time delay designated by the value defined. + Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle. + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PSTATES_ENABLED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicator that all relevant attributes and required data for + Pstates to be enabled is present and valid + + Producer: p9_build_pstate_datablock + + Consumers: p9_pm_pstate_gpe_init + </description> + <valueType>uint8</valueType> + <enum>FALSE=0, TRUE=1</enum> + <writeable/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_RESCLK_ENABLED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicator that all relevant attributes and required data for + Resonant Clocking to be enabled is present and valid + + Producer: p9_build_pstate_datablock + + Consumers: p9_hcode_image_build -> + PGPE Header + CME Header + </description> + <valueType>uint8</valueType> + <enum>FALSE=0, TRUE=1</enum> + <writeable/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_ENABLED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicator that all relevant attributes and required data for + Voltage Droop Monitors (VDM) to be enabled is present and valid + + Producer: p9_build_pstate_datablock + + Consumers: p9_hcode_image_build -> + SGPE Header + CME Header + </description> + <valueType>uint8</valueType> + <enum>FALSE=0, TRUE=1</enum> + <writeable/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_IVRM_ENABLED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicator that all relevant attributes and required data for + Internal Voltage Regulator Macros (IVRMs) to be enabled is present and valid + + Producer: p9_build_pstate_datablock + + Consumers: p9_hcode_image_build -> + PGPE Header + CME Header + </description> + <valueType>uint8</valueType> + <enum>FALSE=0, TRUE=1</enum> + <writeable/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_WOF_ENABLED</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicator that all relevent attributes and required data for + WOF to be enabled is present and valid + + Producer: p9_build_pstate_datablock + + Consumers: p9_hcode_image_build -> + PGPE Header + CME Header + </description> + <valueType>uint8</valueType> + <enum>FALSE=0, TRUE=1</enum> + <writeable/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> +</attributes> |
