add support for OBUS PLL buckets

p9_frequency_buckets.H
p9.obus.pll.scan.initfile
  document and support base frequencies
    1611 MHz - 25.78G, 156.25 MHz ref
    1250 MHz - 25G, 156.25 MHz ref
    1200 MHz - 19.2G, 133.33 MHz ref

pervasive_attributes.xml
  define ATTR_OB[0123]_PLL_BUCKET to hold encoded ring bucket select value

nest_attributes.xml
  define ATTR_FREQ_O_MHZ array to hold per chiplet OBUS frequency
  retain ATTR_FREQ_A_MHZ to serve as FBC A link frequency indicator

p9_setup_sbe_config.C
p9_sbe_attr_setup.C
  transmit bucket selection through FSP/BMC->SBE mailbox
  encode OBUS bucket selects in Scratch Reg2 bits 24:31

p9_sbe_chiplet_pll_initf.C
p9_sbe_chiplet_pll_initf_errors.xml
  scan correct ring image based on bucket selector attributes

p9_ringId.C
p9_ringId.H
p9_ring_id.h
  accomodate three copies of obX_pll_bndy (use ID previously reserved for
  obX_pll_func, which should not be necessary to scan init)

scan_procedures.mk
generateWrapper.pl
  initCompiler infrastructure changes to support build of bucket data

p9.fbc.ab_hp.scom.initfile
p9.fbc.ioo_tl.scom.initfile
p9_tod_setup.C
  updates to handle A,O frequency attribute changes

CMVC-Prereq: 1027320
CMVC-Prereq: 1027496
CMVC-Prereq: 1027579

Change-Id: I42f9bb4037a587f7e3ec8dd9848bdb853ac3d7a0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40159
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40164
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

6 files changed, 215 insertions, 17 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
index 5c09e9e1..03f15303 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
@@ -54,6 +54,14 @@ enum P9_SETUP_SBE_CONFIG_scratch4
     ATTR_I2C_BUS_DIV_REF_LENGTH        = 16,
     ATTR_NDL_MESHCTRL_SETUP_STARTBIT   = 16,
     ATTR_NDL_MESHCTRL_SETUP_LENGTH     = 4,
+    ATTR_OB0_PLL_BUCKET_STARTBIT       = 24,
+    ATTR_OB0_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB1_PLL_BUCKET_STARTBIT       = 26,
+    ATTR_OB1_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB2_PLL_BUCKET_STARTBIT       = 28,
+    ATTR_OB2_PLL_BUCKET_LENGTH         = 2,
+    ATTR_OB3_PLL_BUCKET_STARTBIT       = 30,
+    ATTR_OB3_PLL_BUCKET_LENGTH         = 2,
 
     // Scratch_reg_3
     ATTR_BOOT_FLAGS_STARTBIT           = 0,
@@ -62,14 +70,14 @@ enum P9_SETUP_SBE_CONFIG_scratch4
     // Scratch_reg_4
     ATTR_BOOT_FREQ_MULT_STARTBIT       = 0,
     ATTR_BOOT_FREQ_MULT_LENGTH         = 16,
-    ATTR_NEST_PLL_BUCKET_STARTBIT      = 24,
-    ATTR_NEST_PLL_BUCKET_LENGTH        = 8,
-    ATTR_OBUS_RATIO_VALUE_BIT          = 21,
     ATTR_CP_FILTER_BYPASS_BIT          = 16,
     ATTR_SS_FILTER_BYPASS_BIT          = 17,
     ATTR_IO_FILTER_BYPASS_BIT          = 18,
     ATTR_DPLL_BYPASS_BIT               = 19,
     ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT   = 20,
+    ATTR_OBUS_RATIO_VALUE_BIT          = 21,
+    ATTR_NEST_PLL_BUCKET_STARTBIT      = 29,
+    ATTR_NEST_PLL_BUCKET_LENGTH        = 3,
 
     // Scratch_reg_5
     ATTR_PLL_MUX_STARTBIT              = 12,
@@ -204,6 +212,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
     }
     //read_scratch2_reg
     {
+        uint8_t l_ob0_pll_bucket = 0;
+        uint8_t l_ob1_pll_bucket = 0;
+        uint8_t l_ob2_pll_bucket = 0;
+        uint8_t l_ob3_pll_bucket = 0;
+
         if ( l_read_scratch8.getBit<1>() )
         {
             uint8_t l_ndl_meshctrl_setup = 0x0;
@@ -215,6 +228,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
 
             l_read_scratch_reg.extractToRight<0, 16>(l_read_4);
 
+            l_read_scratch_reg.extractToRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket);
+            l_read_scratch_reg.extractToRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket);
+            l_read_scratch_reg.extractToRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket);
+            l_read_scratch_reg.extractToRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket);
+
             FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF");
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));
 
@@ -222,6 +240,12 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             l_ndl_meshctrl_setup = (~l_ndl_meshctrl_setup) & 0x0F;
             FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP");
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_ndl_meshctrl_setup));
+
+            FAPI_DBG("Setting up ATTR_OBX_PLL_BUCKET");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket));
         }
         else
         {
@@ -237,6 +261,17 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             l_read_scratch_reg.insertFromRight< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >(l_read_1);
             l_read_scratch_reg.flipBit< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >();
 
+            FAPI_DBG("Reading OB PLL buckets");
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket));
+
+            l_read_scratch_reg.insertFromRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket);
+            l_read_scratch_reg.insertFromRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket);
+            l_read_scratch_reg.insertFromRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket);
+            l_read_scratch_reg.insertFromRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket);
+
             FAPI_DBG("Setting up value of Scratch_reg2");
             //Setting SCRATCH_REGISTER_2 register value
             FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM,
@@ -309,7 +344,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             l_read_scratch_reg.extractToRight<19, 1>(l_dpll_bypass);
             l_read_scratch_reg.extractToRight<20, 1>(l_nest_mem_x_o_pci_bypass);
             l_read_scratch_reg.extractToRight<ATTR_OBUS_RATIO_VALUE_BIT, 1>(l_attr_obus_ratio);
-            l_read_scratch_reg.extractToRight<24, 8>(l_read_1);
+            l_read_scratch_reg.extractToRight<ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH>(l_read_1);
 
             FAPI_DBG("Setting up PLL bypass attributes");
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass));
@@ -348,7 +383,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
 
             l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4);
-            l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1);
+            l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1 & 0x7);
 
             l_read_scratch_reg.writeBit<ATTR_CP_FILTER_BYPASS_BIT>(l_cp_filter_bypass & 0x1);
             l_read_scratch_reg.writeBit<ATTR_SS_FILTER_BYPASS_BIT>(l_ss_filter_bypass & 0x1);
@@ -580,7 +615,6 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
                                    l_read_2));
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip,
                                    l_read_3));
-
         }
         else
         {
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
index 92fc5206..c1eb02ac 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
@@ -40,11 +40,38 @@
 #include "p9_sbe_chiplet_pll_initf.H"
 #include "p9_perv_scom_addresses.H"
 #include <p9_ring_id.h>
+#include "p9_frequency_buckets.H"
 
 fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     FAPI_INF("p9_sbe_chiplet_pll_initf: Entering ...");
+    uint8_t l_ob0_pll_bucket = 0;
+    uint8_t l_ob1_pll_bucket = 0;
+    uint8_t l_ob2_pll_bucket = 0;
+    uint8_t l_ob3_pll_bucket = 0;
+
+    // determine obus pll buckets
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket),
+             "Error from FAPI_ATTR_GET (ATTR_OB0_PLL_BUCKET)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket),
+             "Error from FAPI_ATTR_GET (ATTR_OB1_PLL_BUCKET)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket),
+             "Error from FAPI_ATTR_GET (ATTR_OB2_PLL_BUCKET)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket),
+             "Error from FAPI_ATTR_GET (ATTR_OB3_PLL_BUCKET)");
+
+    FAPI_ASSERT((l_ob0_pll_bucket && (l_ob0_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) &&
+                (l_ob1_pll_bucket && (l_ob1_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) &&
+                (l_ob2_pll_bucket && (l_ob2_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) &&
+                (l_ob3_pll_bucket && (l_ob3_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)),
+                fapi2::P9_SBE_CHIPLET_PLL_INITF_UNSUPPORTED_OBUS_BUCKET().
+                set_TARGET(i_target_chip).
+                set_OB0_BUCKET_INDEX(l_ob0_pll_bucket).
+                set_OB1_BUCKET_INDEX(l_ob1_pll_bucket).
+                set_OB2_BUCKET_INDEX(l_ob2_pll_bucket).
+                set_OB3_BUCKET_INDEX(l_ob3_pll_bucket),
+                "Unsupported OBUS PLL bucket value!");
 
     for (auto& l_chplt_trgt :  i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
          (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_XBUS |
@@ -64,23 +91,79 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
                 break;
 
             case 0x9:
-                FAPI_DBG("Scan ob0_pll_bndy ring");
-                l_ring_id = ob0_pll_bndy;
+                if (l_ob0_pll_bucket == 1)
+                {
+                    FAPI_DBG("Scan ob0_pll_bndy_bucket1 ring");
+                    l_ring_id = ob0_pll_bndy_bucket_1;
+                }
+                else if (l_ob0_pll_bucket == 2)
+                {
+                    FAPI_DBG("Scan ob0_pll_bndy_bucket2 ring");
+                    l_ring_id = ob0_pll_bndy_bucket_2;
+                }
+                else
+                {
+                    FAPI_DBG("Scan ob0_pll_bndy_bucket3 ring");
+                    l_ring_id = ob0_pll_bndy_bucket_3;
+                }
+
                 break;
 
             case 0xa:
-                FAPI_DBG("Scan ob1_pll_bndy ring");
-                l_ring_id = ob1_pll_bndy;
+                if (l_ob1_pll_bucket == 1)
+                {
+                    FAPI_DBG("Scan ob1_pll_bndy_bucket1 ring");
+                    l_ring_id = ob1_pll_bndy_bucket_1;
+                }
+                else if (l_ob1_pll_bucket == 2)
+                {
+                    FAPI_DBG("Scan ob1_pll_bndy_bucket2 ring");
+                    l_ring_id = ob1_pll_bndy_bucket_2;
+                }
+                else
+                {
+                    FAPI_DBG("Scan ob1_pll_bndy_bucket3 ring");
+                    l_ring_id = ob1_pll_bndy_bucket_3;
+                }
+
                 break;
 
             case 0xb:
-                FAPI_DBG("Scan ob2_pll_bndy ring");
-                l_ring_id = ob2_pll_bndy;
+                if (l_ob2_pll_bucket == 1)
+                {
+                    FAPI_DBG("Scan ob2_pll_bndy_bucket1 ring");
+                    l_ring_id = ob2_pll_bndy_bucket_1;
+                }
+                else if (l_ob2_pll_bucket == 2)
+                {
+                    FAPI_DBG("Scan ob2_pll_bndy_bucket2 ring");
+                    l_ring_id = ob2_pll_bndy_bucket_2;
+                }
+                else
+                {
+                    FAPI_DBG("Scan ob2_pll_bndy_bucket3 ring");
+                    l_ring_id = ob2_pll_bndy_bucket_3;
+                }
+
                 break;
 
             case 0xc:
-                FAPI_DBG("Scan ob3_pll_bndy ring");
-                l_ring_id = ob3_pll_bndy;
+                if (l_ob3_pll_bucket == 1)
+                {
+                    FAPI_DBG("Scan ob3_pll_bndy_bucket1 ring");
+                    l_ring_id = ob3_pll_bndy_bucket_1;
+                }
+                else if (l_ob3_pll_bucket == 2)
+                {
+                    FAPI_DBG("Scan ob3_pll_bndy_bucket2 ring");
+                    l_ring_id = ob3_pll_bndy_bucket_2;
+                }
+                else
+                {
+                    FAPI_DBG("Scan ob3_pll_bndy_bucket3 ring");
+                    l_ring_id = ob3_pll_bndy_bucket_3;
+                }
+
                 break;
 
             case 0xd:
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index 208bb98e..8ad33b9c 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -46,22 +46,36 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
+  <id>ATTR_FREQ_O_MHZ</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    The frequency of a processor's Obus mesh clocks, in MHz.
+    Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+  <writeable/>
+  <array>4</array>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
   <id>ATTR_FREQ_A_MHZ</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>
-    The frequency of a processor's A link clocks, in MHz.
+    The frequency of a processor's Abus, in MHz.
     This is the same for all chips in the system.
     Provided by the MRW.
   </description>
   <valueType>uint32</valueType>
   <platInit/>
+  <writeable/>
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
   <id>ATTR_FREQ_X_MHZ</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>
-    The frequency of a processor's X link clocks, in MHz.
+    The frequency of a processor's Xbus mesh clocks, in MHz.
     This is the same for all chips in the system.
     Provided by the MRW.
   </description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 6558a63b..67f0b7e0 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -62,6 +62,22 @@
     <value>0x05</value>
   </entry>
   <entry>
+    <name>ATTR_OB0_PLL_BUCKET</name>
+    <value>0x01</value>
+  </entry>
+  <entry>
+    <name>ATTR_OB1_PLL_BUCKET</name>
+    <value>0x01</value>
+  </entry>
+  <entry>
+    <name>ATTR_OB2_PLL_BUCKET</name>
+    <value>0x01</value>
+  </entry>
+  <entry>
+    <name>ATTR_OB3_PLL_BUCKET</name>
+    <value>0x01</value>
+  </entry>
+  <entry>
     <name>ATTR_BOOT_FREQ_MULT</name>
     <value>0x00B4</value>
   </entry>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
index d273bb39..8ed45ed6 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -141,6 +141,46 @@
 </attribute>
 
 <attribute>
+  <id>ATTR_OB0_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS0 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_OB1_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS1 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_OB2_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS2 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_OB3_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Select OBUS3 pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
   <id>ATTR_BOOT_FREQ_MULT</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description>EQ boot frequency multiplier
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
index 75a9c3b9..f82fa041 100755
--- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER sbe Project                                                  -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -33,4 +33,15 @@
     <ffdc>UNIT_POS</ffdc>
   </hwpError>
   <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_CHIPLET_PLL_INITF_UNSUPPORTED_OBUS_BUCKET</rc>
+    <description>Unsupported OBUS PLL bucket select</description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>OB0_BUCKET_INDEX</ffdc>
+    <ffdc>OB1_BUCKET_INDEX</ffdc>
+    <ffdc>OB2_BUCKET_INDEX</ffdc>
+    <ffdc>OB3_BUCKET_INDEX</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
 </hwpErrors>