diff options
10 files changed, 326 insertions, 99 deletions
diff --git a/src/import/chips/p9/common/include/p9_frequency_buckets.H b/src/import/chips/p9/common/include/p9_frequency_buckets.H index 68a2bf56..b8b8872d 100644 --- a/src/import/chips/p9/common/include/p9_frequency_buckets.H +++ b/src/import/chips/p9/common/include/p9_frequency_buckets.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -64,3 +64,16 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] = 2666, 2666 }; + +// constant definining number of OBUS PLL frequency options ('buckets') +// to be built into unsigned HW image +const uint8_t OBUS_PLL_FREQ_BUCKETS = 3; + +// OBUS PLL frequency in MHz +// index is bucket number +const uint32_t OBUS_PLL_FREQ_LIST[OBUS_PLL_FREQ_BUCKETS] = +{ + 1611, + 1250, + 1200 +}; diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index 5c09e9e1..03f15303 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -54,6 +54,14 @@ enum P9_SETUP_SBE_CONFIG_scratch4 ATTR_I2C_BUS_DIV_REF_LENGTH = 16, ATTR_NDL_MESHCTRL_SETUP_STARTBIT = 16, ATTR_NDL_MESHCTRL_SETUP_LENGTH = 4, + ATTR_OB0_PLL_BUCKET_STARTBIT = 24, + ATTR_OB0_PLL_BUCKET_LENGTH = 2, + ATTR_OB1_PLL_BUCKET_STARTBIT = 26, + ATTR_OB1_PLL_BUCKET_LENGTH = 2, + ATTR_OB2_PLL_BUCKET_STARTBIT = 28, + ATTR_OB2_PLL_BUCKET_LENGTH = 2, + ATTR_OB3_PLL_BUCKET_STARTBIT = 30, + ATTR_OB3_PLL_BUCKET_LENGTH = 2, // Scratch_reg_3 ATTR_BOOT_FLAGS_STARTBIT = 0, @@ -62,14 +70,14 @@ enum P9_SETUP_SBE_CONFIG_scratch4 // Scratch_reg_4 ATTR_BOOT_FREQ_MULT_STARTBIT = 0, ATTR_BOOT_FREQ_MULT_LENGTH = 16, - ATTR_NEST_PLL_BUCKET_STARTBIT = 24, - ATTR_NEST_PLL_BUCKET_LENGTH = 8, - ATTR_OBUS_RATIO_VALUE_BIT = 21, ATTR_CP_FILTER_BYPASS_BIT = 16, ATTR_SS_FILTER_BYPASS_BIT = 17, ATTR_IO_FILTER_BYPASS_BIT = 18, ATTR_DPLL_BYPASS_BIT = 19, ATTR_NEST_MEM_X_O_PCI_BYPASS_BIT = 20, + ATTR_OBUS_RATIO_VALUE_BIT = 21, + ATTR_NEST_PLL_BUCKET_STARTBIT = 29, + ATTR_NEST_PLL_BUCKET_LENGTH = 3, // Scratch_reg_5 ATTR_PLL_MUX_STARTBIT = 12, @@ -204,6 +212,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const } //read_scratch2_reg { + uint8_t l_ob0_pll_bucket = 0; + uint8_t l_ob1_pll_bucket = 0; + uint8_t l_ob2_pll_bucket = 0; + uint8_t l_ob3_pll_bucket = 0; + if ( l_read_scratch8.getBit<1>() ) { uint8_t l_ndl_meshctrl_setup = 0x0; @@ -215,6 +228,11 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_read_scratch_reg.extractToRight<0, 16>(l_read_4); + l_read_scratch_reg.extractToRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket); + l_read_scratch_reg.extractToRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket); + l_read_scratch_reg.extractToRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket); + l_read_scratch_reg.extractToRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket); + FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); @@ -222,6 +240,12 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_ndl_meshctrl_setup = (~l_ndl_meshctrl_setup) & 0x0F; FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_ndl_meshctrl_setup)); + + FAPI_DBG("Setting up ATTR_OBX_PLL_BUCKET"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket)); } else { @@ -237,6 +261,17 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_read_scratch_reg.insertFromRight< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >(l_read_1); l_read_scratch_reg.flipBit< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >(); + FAPI_DBG("Reading OB PLL buckets"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket)); + + l_read_scratch_reg.insertFromRight<ATTR_OB0_PLL_BUCKET_STARTBIT, ATTR_OB0_PLL_BUCKET_LENGTH>(l_ob0_pll_bucket); + l_read_scratch_reg.insertFromRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket); + l_read_scratch_reg.insertFromRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket); + l_read_scratch_reg.insertFromRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket); + FAPI_DBG("Setting up value of Scratch_reg2"); //Setting SCRATCH_REGISTER_2 register value FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, @@ -309,7 +344,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_read_scratch_reg.extractToRight<19, 1>(l_dpll_bypass); l_read_scratch_reg.extractToRight<20, 1>(l_nest_mem_x_o_pci_bypass); l_read_scratch_reg.extractToRight<ATTR_OBUS_RATIO_VALUE_BIT, 1>(l_attr_obus_ratio); - l_read_scratch_reg.extractToRight<24, 8>(l_read_1); + l_read_scratch_reg.extractToRight<ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH>(l_read_1); FAPI_DBG("Setting up PLL bypass attributes"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip, l_cp_filter_bypass)); @@ -348,7 +383,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); l_read_scratch_reg.insertFromRight< ATTR_BOOT_FREQ_MULT_STARTBIT, ATTR_BOOT_FREQ_MULT_LENGTH >(l_read_4); - l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1); + l_read_scratch_reg.insertFromRight< ATTR_NEST_PLL_BUCKET_STARTBIT, ATTR_NEST_PLL_BUCKET_LENGTH >(l_read_1 & 0x7); l_read_scratch_reg.writeBit<ATTR_CP_FILTER_BYPASS_BIT>(l_cp_filter_bypass & 0x1); l_read_scratch_reg.writeBit<ATTR_SS_FILTER_BYPASS_BIT>(l_ss_filter_bypass & 0x1); @@ -580,7 +615,6 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_read_2)); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target_chip, l_read_3)); - } else { diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C index 92fc5206..c1eb02ac 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C @@ -40,11 +40,38 @@ #include "p9_sbe_chiplet_pll_initf.H" #include "p9_perv_scom_addresses.H" #include <p9_ring_id.h> +#include "p9_frequency_buckets.H" fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { FAPI_INF("p9_sbe_chiplet_pll_initf: Entering ..."); + uint8_t l_ob0_pll_bucket = 0; + uint8_t l_ob1_pll_bucket = 0; + uint8_t l_ob2_pll_bucket = 0; + uint8_t l_ob3_pll_bucket = 0; + + // determine obus pll buckets + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket), + "Error from FAPI_ATTR_GET (ATTR_OB0_PLL_BUCKET)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket), + "Error from FAPI_ATTR_GET (ATTR_OB1_PLL_BUCKET)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB2_PLL_BUCKET, i_target_chip, l_ob2_pll_bucket), + "Error from FAPI_ATTR_GET (ATTR_OB2_PLL_BUCKET)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket), + "Error from FAPI_ATTR_GET (ATTR_OB3_PLL_BUCKET)"); + + FAPI_ASSERT((l_ob0_pll_bucket && (l_ob0_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) && + (l_ob1_pll_bucket && (l_ob1_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) && + (l_ob2_pll_bucket && (l_ob2_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) && + (l_ob3_pll_bucket && (l_ob3_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)), + fapi2::P9_SBE_CHIPLET_PLL_INITF_UNSUPPORTED_OBUS_BUCKET(). + set_TARGET(i_target_chip). + set_OB0_BUCKET_INDEX(l_ob0_pll_bucket). + set_OB1_BUCKET_INDEX(l_ob1_pll_bucket). + set_OB2_BUCKET_INDEX(l_ob2_pll_bucket). + set_OB3_BUCKET_INDEX(l_ob3_pll_bucket), + "Unsupported OBUS PLL bucket value!"); for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_XBUS | @@ -64,23 +91,79 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const break; case 0x9: - FAPI_DBG("Scan ob0_pll_bndy ring"); - l_ring_id = ob0_pll_bndy; + if (l_ob0_pll_bucket == 1) + { + FAPI_DBG("Scan ob0_pll_bndy_bucket1 ring"); + l_ring_id = ob0_pll_bndy_bucket_1; + } + else if (l_ob0_pll_bucket == 2) + { + FAPI_DBG("Scan ob0_pll_bndy_bucket2 ring"); + l_ring_id = ob0_pll_bndy_bucket_2; + } + else + { + FAPI_DBG("Scan ob0_pll_bndy_bucket3 ring"); + l_ring_id = ob0_pll_bndy_bucket_3; + } + break; case 0xa: - FAPI_DBG("Scan ob1_pll_bndy ring"); - l_ring_id = ob1_pll_bndy; + if (l_ob1_pll_bucket == 1) + { + FAPI_DBG("Scan ob1_pll_bndy_bucket1 ring"); + l_ring_id = ob1_pll_bndy_bucket_1; + } + else if (l_ob1_pll_bucket == 2) + { + FAPI_DBG("Scan ob1_pll_bndy_bucket2 ring"); + l_ring_id = ob1_pll_bndy_bucket_2; + } + else + { + FAPI_DBG("Scan ob1_pll_bndy_bucket3 ring"); + l_ring_id = ob1_pll_bndy_bucket_3; + } + break; case 0xb: - FAPI_DBG("Scan ob2_pll_bndy ring"); - l_ring_id = ob2_pll_bndy; + if (l_ob2_pll_bucket == 1) + { + FAPI_DBG("Scan ob2_pll_bndy_bucket1 ring"); + l_ring_id = ob2_pll_bndy_bucket_1; + } + else if (l_ob2_pll_bucket == 2) + { + FAPI_DBG("Scan ob2_pll_bndy_bucket2 ring"); + l_ring_id = ob2_pll_bndy_bucket_2; + } + else + { + FAPI_DBG("Scan ob2_pll_bndy_bucket3 ring"); + l_ring_id = ob2_pll_bndy_bucket_3; + } + break; case 0xc: - FAPI_DBG("Scan ob3_pll_bndy ring"); - l_ring_id = ob3_pll_bndy; + if (l_ob3_pll_bucket == 1) + { + FAPI_DBG("Scan ob3_pll_bndy_bucket1 ring"); + l_ring_id = ob3_pll_bndy_bucket_1; + } + else if (l_ob3_pll_bucket == 2) + { + FAPI_DBG("Scan ob3_pll_bndy_bucket2 ring"); + l_ring_id = ob3_pll_bndy_bucket_2; + } + else + { + FAPI_DBG("Scan ob3_pll_bndy_bucket3 ring"); + l_ring_id = ob3_pll_bndy_bucket_3; + } + break; case 0xd: diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 208bb98e..8ad33b9c 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -46,22 +46,36 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_FREQ_O_MHZ</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + The frequency of a processor's Obus mesh clocks, in MHz. + Provided by the MRW. + </description> + <valueType>uint32</valueType> + <platInit/> + <writeable/> + <array>4</array> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_FREQ_A_MHZ</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> - The frequency of a processor's A link clocks, in MHz. + The frequency of a processor's Abus, in MHz. This is the same for all chips in the system. Provided by the MRW. </description> <valueType>uint32</valueType> <platInit/> + <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> <id>ATTR_FREQ_X_MHZ</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> - The frequency of a processor's X link clocks, in MHz. + The frequency of a processor's Xbus mesh clocks, in MHz. This is the same for all chips in the system. Provided by the MRW. </description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 6558a63b..67f0b7e0 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -62,6 +62,22 @@ <value>0x05</value> </entry> <entry> + <name>ATTR_OB0_PLL_BUCKET</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_OB1_PLL_BUCKET</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_OB2_PLL_BUCKET</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_OB3_PLL_BUCKET</name> + <value>0x01</value> + </entry> + <entry> <name>ATTR_BOOT_FREQ_MULT</name> <value>0x00B4</value> </entry> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index d273bb39..8ed45ed6 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -141,6 +141,46 @@ </attribute> <attribute> + <id>ATTR_OB0_PLL_BUCKET</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Select OBUS0 pll setting from one of the supported frequencies</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_OB1_PLL_BUCKET</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Select OBUS1 pll setting from one of the supported frequencies</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_OB2_PLL_BUCKET</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Select OBUS2 pll setting from one of the supported frequencies</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_OB3_PLL_BUCKET</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Select OBUS3 pll setting from one of the supported frequencies</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> <id>ATTR_BOOT_FREQ_MULT</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>EQ boot frequency multiplier diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml index 75a9c3b9..f82fa041 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -33,4 +33,15 @@ <ffdc>UNIT_POS</ffdc> </hwpError> <!-- ******************************************************************** --> + <hwpError> + <sbeError/> + <rc>RC_P9_SBE_CHIPLET_PLL_INITF_UNSUPPORTED_OBUS_BUCKET</rc> + <description>Unsupported OBUS PLL bucket select</description> + <ffdc>TARGET</ffdc> + <ffdc>OB0_BUCKET_INDEX</ffdc> + <ffdc>OB1_BUCKET_INDEX</ffdc> + <ffdc>OB2_BUCKET_INDEX</ffdc> + <ffdc>OB3_BUCKET_INDEX</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.C b/src/import/chips/p9/utils/imageProcs/p9_ringId.C index 6bcda87c..da08274f 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.C +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.C @@ -222,16 +222,17 @@ namespace OB0 { const GenRingIdList RING_ID_LIST_COMMON[] = { - {"ob0_fure" , 0x00, 0x09, 0x09, EKB_RING , 0x0903700F}, - {"ob0_gptr" , 0x01, 0x09, 0x09, EKB_RING , 0x09037002}, - {"ob0_time" , 0x02, 0x09, 0x09, VPD_RING , 0x09037007}, - {"ob0_pll_gptr" , 0x03, 0x09, 0x09, EKB_RING , 0x09030012}, - {"ob0_pll_bndy" , 0x04, 0x09, 0x09, EKB_RING , 0x09030018}, - {"ob0_pll_func" , 0x05, 0x09, 0x09, EKB_RING , 0x09030010}, + {"ob0_fure" , 0x00, 0x09, 0x09, EKB_RING , 0x0903700F}, + {"ob0_gptr" , 0x01, 0x09, 0x09, EKB_RING , 0x09037002}, + {"ob0_time" , 0x02, 0x09, 0x09, VPD_RING , 0x09037007}, + {"ob0_pll_gptr" , 0x03, 0x09, 0x09, EKB_RING , 0x09030012}, + {"ob0_pll_bndy_bucket_1" , 0x04, 0x09, 0x09, EKB_RING , 0x09030018}, + {"ob0_pll_bndy_bucket_2" , 0x05, 0x09, 0x09, EKB_RING , 0x09030018}, + {"ob0_pll_bndy_bucket_3" , 0x06, 0x09, 0x09, EKB_RING , 0x09030018}, }; const GenRingIdList RING_ID_LIST_INSTANCE[] = { - {"ob0_repr" , 0x0a, 0x09, 0x09, VPD_RING , 0x09037006}, + {"ob0_repr" , 0x0a, 0x09, 0x09, VPD_RING , 0x09037006}, }; const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID }; }; @@ -241,16 +242,17 @@ namespace OB1 { const GenRingIdList RING_ID_LIST_COMMON[] = { - {"ob1_fure" , 0x00, 0x0a, 0x0a, EKB_RING , 0x0A03700F}, - {"ob1_gptr" , 0x01, 0x0a, 0x0a, EKB_RING , 0x0A037002}, - {"ob1_time" , 0x02, 0x0a, 0x0a, VPD_RING , 0x0A037007}, - {"ob1_pll_gptr" , 0x03, 0x0a, 0x0a, EKB_RING , 0x0A030012}, - {"ob1_pll_bndy" , 0x04, 0x0a, 0x0a, EKB_RING , 0x0A030018}, - {"ob1_pll_func" , 0x05, 0x0a, 0x0a, EKB_RING , 0x0A030010}, + {"ob1_fure" , 0x00, 0x0a, 0x0a, EKB_RING , 0x0A03700F}, + {"ob1_gptr" , 0x01, 0x0a, 0x0a, EKB_RING , 0x0A037002}, + {"ob1_time" , 0x02, 0x0a, 0x0a, VPD_RING , 0x0A037007}, + {"ob1_pll_gptr" , 0x03, 0x0a, 0x0a, EKB_RING , 0x0A030012}, + {"ob1_pll_bndy_bucket_1" , 0x04, 0x0a, 0x0a, EKB_RING , 0x0A030018}, + {"ob1_pll_bndy_bucket_2" , 0x05, 0x0a, 0x0a, EKB_RING , 0x0A030018}, + {"ob1_pll_bndy_bucket_3" , 0x06, 0x0a, 0x0a, EKB_RING , 0x0A030018}, }; const GenRingIdList RING_ID_LIST_INSTANCE[] = { - {"ob1_repr" , 0x0a, 0x0a, 0x0a, VPD_RING , 0x0A037006}, + {"ob1_repr" , 0x0a, 0x0a, 0x0a, VPD_RING , 0x0A037006}, }; const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID }; }; @@ -260,16 +262,17 @@ namespace OB2 { const GenRingIdList RING_ID_LIST_COMMON[] = { - {"ob2_fure" , 0x00, 0x0b, 0x0b, EKB_RING , 0x0B03700F}, - {"ob2_gptr" , 0x01, 0x0b, 0x0b, EKB_RING , 0x0B037002}, - {"ob2_time" , 0x02, 0x0b, 0x0b, VPD_RING , 0x0B037007}, - {"ob2_pll_gptr" , 0x03, 0x0b, 0x0b, EKB_RING , 0x0B030012}, - {"ob2_pll_bndy" , 0x04, 0x0b, 0x0b, EKB_RING , 0x0B030018}, - {"ob2_pll_func" , 0x05, 0x0b, 0x0b, EKB_RING , 0x0B030010}, + {"ob2_fure" , 0x00, 0x0b, 0x0b, EKB_RING , 0x0B03700F}, + {"ob2_gptr" , 0x01, 0x0b, 0x0b, EKB_RING , 0x0B037002}, + {"ob2_time" , 0x02, 0x0b, 0x0b, VPD_RING , 0x0B037007}, + {"ob2_pll_gptr" , 0x03, 0x0b, 0x0b, EKB_RING , 0x0B030012}, + {"ob2_pll_bndy_bucket_1" , 0x04, 0x0b, 0x0b, EKB_RING , 0x0B030018}, + {"ob2_pll_bndy_bucket_2" , 0x05, 0x0b, 0x0b, EKB_RING , 0x0B030018}, + {"ob2_pll_bndy_bucket_3" , 0x06, 0x0b, 0x0b, EKB_RING , 0x0B030018}, }; const GenRingIdList RING_ID_LIST_INSTANCE[] = { - {"ob2_repr" , 0x0a, 0x0b, 0x0b, VPD_RING , 0x0B037006}, + {"ob2_repr" , 0x0a, 0x0b, 0x0b, VPD_RING , 0x0B037006}, }; const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID }; }; @@ -279,16 +282,17 @@ namespace OB3 { const GenRingIdList RING_ID_LIST_COMMON[] = { - {"ob3_fure" , 0x00, 0x0c, 0x0c, EKB_RING , 0x0C03700F}, - {"ob3_gptr" , 0x01, 0x0c, 0x0c, EKB_RING , 0x0C037002}, - {"ob3_time" , 0x02, 0x0c, 0x0c, VPD_RING , 0x0C037007}, - {"ob3_pll_gptr" , 0x03, 0x0c, 0x0c, EKB_RING , 0x0C030012}, - {"ob3_pll_bndy" , 0x04, 0x0c, 0x0c, EKB_RING , 0x0C030018}, - {"ob3_pll_func" , 0x05, 0x0c, 0x0c, EKB_RING , 0x0C030010}, + {"ob3_fure" , 0x00, 0x0c, 0x0c, EKB_RING , 0x0C03700F}, + {"ob3_gptr" , 0x01, 0x0c, 0x0c, EKB_RING , 0x0C037002}, + {"ob3_time" , 0x02, 0x0c, 0x0c, VPD_RING , 0x0C037007}, + {"ob3_pll_gptr" , 0x03, 0x0c, 0x0c, EKB_RING , 0x0C030012}, + {"ob3_pll_bndy_bucket_1" , 0x04, 0x0c, 0x0c, EKB_RING , 0x0C030018}, + {"ob3_pll_bndy_bucket_2" , 0x05, 0x0c, 0x0c, EKB_RING , 0x0C030018}, + {"ob3_pll_bndy_bucket_3" , 0x06, 0x0c, 0x0c, EKB_RING , 0x0C030018}, }; const GenRingIdList RING_ID_LIST_INSTANCE[] = { - {"ob3_repr" , 0x0a, 0x0c, 0x0c, VPD_RING , 0x0C037006}, + {"ob3_repr" , 0x0a, 0x0c, 0x0c, VPD_RING , 0x0C037006}, }; const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, RL, NOT_VALID }; }; diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H index a1e75788..26fcd537 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H +++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H @@ -533,7 +533,9 @@ enum RingOffset ob0_time = 2, ob0_pll_gptr = 3, ob0_pll_bndy = 4, - ob0_pll_func = 5, + ob0_pll_bndy_bucket_1 = 4, + ob0_pll_bndy_bucket_2 = 5, + ob0_pll_bndy_bucket_3 = 6, // Instance Rings ob0_repr = (0 | INSTANCE_RING_MARK) }; @@ -541,7 +543,7 @@ enum RingOffset static const CHIPLET_DATA g_ob0Data = { 9, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 6, // 6 common rings for OB Chiplet + 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1 }; @@ -563,7 +565,9 @@ enum RingOffset ob1_time = 2, ob1_pll_gptr = 3, ob1_pll_bndy = 4, - ob1_pll_func = 5, + ob1_pll_bndy_bucket_1 = 4, + ob1_pll_bndy_bucket_2 = 5, + ob1_pll_bndy_bucket_3 = 6, // Instance Rings ob1_repr = (0 | INSTANCE_RING_MARK) }; @@ -571,7 +575,7 @@ enum RingOffset static const CHIPLET_DATA g_ob1Data = { 10, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 6, // 6 common rings for OB Chiplet + 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1 }; @@ -594,7 +598,9 @@ enum RingOffset ob2_time = 2, ob2_pll_gptr = 3, ob2_pll_bndy = 4, - ob2_pll_func = 5, + ob2_pll_bndy_bucket_1 = 4, + ob2_pll_bndy_bucket_2 = 5, + ob2_pll_bndy_bucket_3 = 6, // Instance Rings ob2_repr = (0 | INSTANCE_RING_MARK) }; @@ -602,7 +608,7 @@ enum RingOffset static const CHIPLET_DATA g_ob2Data = { 11, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 6, // 6 common rings for OB Chiplet + 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1 }; @@ -624,7 +630,9 @@ enum RingOffset ob3_time = 2, ob3_pll_gptr = 3, ob3_pll_bndy = 4, - ob3_pll_func = 5, + ob3_pll_bndy_bucket_1 = 4, + ob3_pll_bndy_bucket_2 = 5, + ob3_pll_bndy_bucket_3 = 6, // Instance Rings ob3_repr = (0 | INSTANCE_RING_MARK) }; @@ -632,7 +640,7 @@ enum RingOffset static const CHIPLET_DATA g_ob3Data = { 12, // O-Bus Chiplet ID range is 9 - 12. The base ID is 9. - 6, // 10 common rings for OB Chiplet + 7, // 7 common rings for OB Chiplet 1, // 1 instance specific rings for each OB chiplet 1 }; @@ -999,37 +1007,37 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = { OB0::ob0_time , "ob0_time" , OB0_TYPE }, // 120 { OB0::ob0_pll_gptr , "ob0_pll_gptr" , OB0_TYPE }, // 121 { OB0::ob0_pll_bndy , "ob0_pll_bndy" , OB0_TYPE }, // 122 - { OB0::ob0_pll_func , "ob0_pll_func" , OB0_TYPE }, // 123 - { OB0::ob0_repr , "ob0_repr" , OB0_TYPE }, // 124 - { INVALID_RING , "invalid" , OB0_TYPE }, // 125 - { INVALID_RING , "invalid" , OB0_TYPE }, // 126 + { OB0::ob0_pll_bndy_bucket_1 , "ob0_pll_bndy_bucket_1" , OB0_TYPE }, // 123 + { OB0::ob0_pll_bndy_bucket_2 , "ob0_pll_bndy_bucket_2" , OB0_TYPE }, // 124 + { OB0::ob0_pll_bndy_bucket_3 , "ob0_pll_bndy_bucket_3" , OB0_TYPE }, // 125 + { OB0::ob0_repr , "ob0_repr" , OB0_TYPE }, // 126 { OB1::ob1_fure , "ob1_fure" , OB1_TYPE }, // 127 { OB1::ob1_gptr , "ob1_gptr" , OB1_TYPE }, // 128 { OB1::ob1_time , "ob1_time" , OB1_TYPE }, // 129 { OB1::ob1_pll_gptr , "ob1_pll_gptr" , OB1_TYPE }, // 130 { OB1::ob1_pll_bndy , "ob1_pll_bndy" , OB1_TYPE }, // 131 - { OB1::ob1_pll_func , "ob1_pll_func" , OB1_TYPE }, // 132 - { OB1::ob1_repr , "ob1_repr" , OB1_TYPE }, // 133 - { INVALID_RING , "invalid" , OB1_TYPE }, // 134 - { INVALID_RING , "invalid" , OB1_TYPE }, // 135 + { OB1::ob1_pll_bndy_bucket_1 , "ob1_pll_bndy_bucket_1" , OB1_TYPE }, // 132 + { OB1::ob1_pll_bndy_bucket_2 , "ob1_pll_bndy_bucket_2" , OB1_TYPE }, // 133 + { OB1::ob1_pll_bndy_bucket_3 , "ob1_pll_bndy_bucket_3" , OB1_TYPE }, // 134 + { OB1::ob1_repr , "ob1_repr" , OB1_TYPE }, // 135 { OB2::ob2_fure , "ob2_fure" , OB2_TYPE }, // 136 { OB2::ob2_gptr , "ob2_gptr" , OB2_TYPE }, // 137 { OB2::ob2_time , "ob2_time" , OB2_TYPE }, // 138 { OB2::ob2_pll_gptr , "ob2_pll_gptr" , OB2_TYPE }, // 139 { OB2::ob2_pll_bndy , "ob2_pll_bndy" , OB2_TYPE }, // 140 - { OB2::ob2_pll_func , "ob2_pll_func" , OB2_TYPE }, // 141 - { OB2::ob2_repr , "ob2_repr" , OB2_TYPE }, // 142 - { INVALID_RING , "invalid" , OB2_TYPE }, // 143 - { INVALID_RING , "invalid" , OB2_TYPE }, // 144 + { OB2::ob2_pll_bndy_bucket_1 , "ob2_pll_bndy_bucket_1" , OB2_TYPE }, // 141 + { OB2::ob2_pll_bndy_bucket_2 , "ob2_pll_bndy_bucket_2" , OB2_TYPE }, // 142 + { OB2::ob2_pll_bndy_bucket_3 , "ob2_pll_bndy_bucket_3" , OB2_TYPE }, // 143 + { OB2::ob2_repr , "ob2_repr" , OB2_TYPE }, // 144 { OB3::ob3_fure , "ob3_fure" , OB3_TYPE }, // 145 { OB3::ob3_gptr , "ob3_gptr" , OB3_TYPE }, // 146 { OB3::ob3_time , "ob3_time" , OB3_TYPE }, // 147 { OB3::ob3_pll_gptr , "ob3_pll_gptr" , OB3_TYPE }, // 148 { OB3::ob3_pll_bndy , "ob3_pll_bndy" , OB3_TYPE }, // 149 - { OB3::ob3_pll_func , "ob3_pll_func" , OB3_TYPE }, // 150 - { OB3::ob3_repr , "ob3_repr" , OB3_TYPE }, // 151 - { INVALID_RING , "invalid" , OB3_TYPE }, // 152 - { INVALID_RING , "invalid" , OB3_TYPE }, // 153 + { OB3::ob3_pll_bndy_bucket_1 , "ob3_pll_bndy_bucket_1" , OB3_TYPE }, // 150 + { OB3::ob3_pll_bndy_bucket_2 , "ob3_pll_bndy_bucket_2" , OB3_TYPE }, // 151 + { OB3::ob3_pll_bndy_bucket_3 , "ob3_pll_bndy_bucket_3" , OB3_TYPE }, // 152 + { OB3::ob3_repr , "ob3_repr" , OB3_TYPE }, // 153 { PCI0::pci0_fure , "pci0_fure" , PCI0_TYPE }, // 154 { PCI0::pci0_gptr , "pci0_gptr" , PCI0_TYPE }, // 155 { PCI0::pci0_time , "pci0_time" , PCI0_TYPE }, // 156 @@ -1257,37 +1265,37 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] = { OB0::ob0_time , OB0_TYPE }, // 120 { OB0::ob0_pll_gptr , OB0_TYPE }, // 121 { OB0::ob0_pll_bndy , OB0_TYPE }, // 122 - { OB0::ob0_pll_func , OB0_TYPE }, // 123 - { OB0::ob0_repr , OB0_TYPE }, // 124 - { INVALID_RING , OB0_TYPE }, // 125 - { INVALID_RING , OB0_TYPE }, // 126 + { OB0::ob0_pll_bndy_bucket_1 , OB0_TYPE }, // 123 + { OB0::ob0_pll_bndy_bucket_2 , OB0_TYPE }, // 124 + { OB0::ob0_pll_bndy_bucket_3 , OB0_TYPE }, // 125 + { OB0::ob0_repr , OB0_TYPE }, // 126 { OB1::ob1_fure , OB1_TYPE }, // 127 { OB1::ob1_gptr , OB1_TYPE }, // 128 { OB1::ob1_time , OB1_TYPE }, // 129 { OB1::ob1_pll_gptr , OB1_TYPE }, // 130 { OB1::ob1_pll_bndy , OB1_TYPE }, // 131 - { OB1::ob1_pll_func , OB1_TYPE }, // 132 - { OB1::ob1_repr , OB1_TYPE }, // 133 - { INVALID_RING , OB1_TYPE }, // 134 - { INVALID_RING , OB1_TYPE }, // 135 + { OB1::ob1_pll_bndy_bucket_1 , OB1_TYPE }, // 132 + { OB1::ob1_pll_bndy_bucket_2 , OB1_TYPE }, // 133 + { OB1::ob1_pll_bndy_bucket_3 , OB1_TYPE }, // 134 + { OB1::ob1_repr , OB1_TYPE }, // 135 { OB2::ob2_fure , OB2_TYPE }, // 136 { OB2::ob2_gptr , OB2_TYPE }, // 137 { OB2::ob2_time , OB2_TYPE }, // 138 { OB2::ob2_pll_gptr , OB2_TYPE }, // 139 { OB2::ob2_pll_bndy , OB2_TYPE }, // 140 - { OB2::ob2_pll_func , OB2_TYPE }, // 141 - { OB2::ob2_repr , OB2_TYPE }, // 142 - { INVALID_RING , OB2_TYPE }, // 143 - { INVALID_RING , OB2_TYPE }, // 144 + { OB2::ob2_pll_bndy_bucket_1 , OB2_TYPE }, // 141 + { OB2::ob2_pll_bndy_bucket_2 , OB2_TYPE }, // 142 + { OB2::ob2_pll_bndy_bucket_3 , OB2_TYPE }, // 143 + { OB2::ob2_repr , OB2_TYPE }, // 144 { OB3::ob3_fure , OB3_TYPE }, // 145 { OB3::ob3_gptr , OB3_TYPE }, // 146 { OB3::ob3_time , OB3_TYPE }, // 147 { OB3::ob3_pll_gptr , OB3_TYPE }, // 148 { OB3::ob3_pll_bndy , OB3_TYPE }, // 149 - { OB3::ob3_pll_func , OB3_TYPE }, // 150 - { OB3::ob3_repr , OB3_TYPE }, // 151 - { INVALID_RING , OB3_TYPE }, // 152 - { INVALID_RING , OB3_TYPE }, // 153 + { OB3::ob3_pll_bndy_bucket_1 , OB3_TYPE }, // 150 + { OB3::ob3_pll_bndy_bucket_2 , OB3_TYPE }, // 151 + { OB3::ob3_pll_bndy_bucket_3 , OB3_TYPE }, // 152 + { OB3::ob3_repr , OB3_TYPE }, // 153 { PCI0::pci0_fure , PCI0_TYPE }, // 154 { PCI0::pci0_gptr , PCI0_TYPE }, // 155 { PCI0::pci0_time , PCI0_TYPE }, // 156 diff --git a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h index 930664a4..9ba4862a 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h +++ b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h @@ -179,49 +179,53 @@ enum RingID ob0_gptr = 119, ob0_time = 120, ob0_pll_gptr = 121, - ob0_pll_bndy = 122, - ob0_pll_func = 123, + ob0_pll_bndy = 122, + ob0_pll_bndy_bucket_1 = 123, + ob0_pll_bndy_bucket_2 = 124, + ob0_pll_bndy_bucket_3 = 125, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob0_repr = 124, - // values 125-126 unused + ob0_repr = 126, ob1_fure = 127, ob1_gptr = 128, ob1_time = 129, ob1_pll_gptr = 130, ob1_pll_bndy = 131, - ob1_pll_func = 132, + ob1_pll_bndy_bucket_1 = 132, + ob1_pll_bndy_bucket_2 = 133, + ob1_pll_bndy_bucket_3 = 134, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob1_repr = 133, - // values 134-135 unused + ob1_repr = 135, ob2_fure = 136, ob2_gptr = 137, ob2_time = 138, ob2_pll_gptr = 139, ob2_pll_bndy = 140, - ob2_pll_func = 141, + ob2_pll_bndy_bucket_1 = 141, + ob2_pll_bndy_bucket_2 = 142, + ob2_pll_bndy_bucket_3 = 143, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob2_repr = 142, - // values 143-144 unused + ob2_repr = 144, ob3_fure = 145, ob3_gptr = 146, ob3_time = 147, ob3_pll_gptr = 148, ob3_pll_bndy = 149, - ob3_pll_func = 150, + ob3_pll_bndy_bucket_1 = 150, + ob3_pll_bndy_bucket_2 = 151, + ob3_pll_bndy_bucket_3 = 152, // OB Chiplet Rings // OB0, OB1, OB2 and OB3 instance specific Ring - ob3_repr = 151, - // values 152-153 unused + ob3_repr = 153, // PCI Chiplet Rings // PCI0 Common Rings |
