From ceab789089358c5bec527d11748b9e6912521a74 Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Fri, 30 Jun 2017 03:28:03 -0400 Subject: p9_sbe_chiplet_reset updates Added sim ony delay to work with NEST_PLL_BUCKET = 1 to support MV GSD2PIB Change-Id: I68b8f255c26b85e7b77fde01ac538b3208c13c49 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42641 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Soma Bhanutej Reviewed-by: Abhishek Agarwal Reviewed-by: PARVATHI RACHAKONDA Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42792 Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/import/chips/p9/procedures/hwp/perv') diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 1b3a8b2f..9e05481f 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -1422,7 +1422,9 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_obus_scan0( FAPI_DBG("Force PLL out enable for PLLs"); FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data)); +#ifdef SIM_ONLY_DELAY fapi2::delay(10000, (40 * 400)); +#endif l_data.flush<1>(); l_data.clearBit(); -- cgit v1.2.1