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| author | spashabk-in <shakeebbk@in.ibm.com> | 2016-11-21 05:24:49 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-11-22 01:34:46 -0500 |
| commit | e748d4217fe114334533945a3a1f09e2b178d253 (patch) | |
| tree | 9613a490d97e67a05b9c980f736862b9549fb5e8 /src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C | |
| parent | 1f5d8da1131120bad452841435612c19afe4dae0 (diff) | |
| download | talos-sbe-e748d4217fe114334533945a3a1f09e2b178d253.tar.gz talos-sbe-e748d4217fe114334533945a3a1f09e2b178d253.zip | |
Change auto variables to references
Change-Id: I2b9c38757f89d23c627e4a8f2cb3b072bd3bc984
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32867
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32870
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C index c1cb606c..e2dea74e 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C @@ -89,7 +89,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const uint8_t l_bypass = 0; FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ..."); - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) { FAPI_DBG("Drop PDLY bypass"); @@ -104,7 +104,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const if ( l_read_attr ) { - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) { FAPI_DBG("call clock start stop module and drop syncclk muxsel"); @@ -113,7 +113,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const if (l_bypass == 0) { - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) { @@ -121,7 +121,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt)); } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) @@ -130,14 +130,14 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt)); } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) { FAPI_DBG("Check pll lock for PCIe"); FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt)); } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) { @@ -146,7 +146,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const } } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) @@ -156,14 +156,14 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const } else { - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL)) { FAPI_DBG("Drop MCC bypass"); FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_dcc_bypass(l_chplt_trgt)); } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) { FAPI_DBG("call clock start stop module and drop syncclk_muxsel"); @@ -172,7 +172,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const if (l_bypass == 0) { - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) @@ -181,7 +181,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt)); } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) @@ -190,14 +190,14 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt)); } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL)) { FAPI_DBG("Check pll lock for pcie"); FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt)); } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) @@ -207,7 +207,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const } } - for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> + for (auto& l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV> (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL)) |
