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author | CHRISTINA L. GRAVES <clgraves@us.ibm.com> | 2016-12-01 23:01:39 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-02 21:48:16 -0500 |
commit | ec0caeeb0d414fa307fd0893c6bdb74959129eb6 (patch) | |
tree | 020d66f4995c43c9aa464541cf51fa0382f89165 /src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H | |
parent | 234c3bcaa7cb7dced78d9885be4cebc7ab6b0a3d (diff) | |
download | talos-sbe-ec0caeeb0d414fa307fd0893c6bdb74959129eb6.tar.gz talos-sbe-ec0caeeb0d414fa307fd0893c6bdb74959129eb6.zip |
p9_pba_coherent_utils -- add PIB abort error handling for Cronus platform
Change-Id: I64d748c70bbc4a4b3934b64d5d6202c83b21c2db
RTC: 167768
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33322
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33323
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H index 049d19e2..bf6ff046 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -280,6 +280,31 @@ extern "C" const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const uint64_t i_baseAddress); +///@brief does extra error handling for if we hit a problem with a read or write +///@param[in] i_target => P9 chip target +///@param[in] i_rc => The current error that we are seeing from the read/write +///@return the error that we got from the scom or a different error that points to a problem in the PBA + fapi2::ReturnCode p9_pba_coherent_error_handling(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + fapi2::ReturnCode i_rc); + +///@brief does error checking on the OCB side +///@param[in] i_target => P9 chip target +///@return FAPI_RC_SUCCESS if no errors are detected otherwise an error that contains what is in the OCB status registers + fapi2::ReturnCode p9_pba_coherent_check_ocb_status(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +///@brief does error checking on the PBA Fir +///@param[in] i_target => P9 chip target +///@return FAPI_RC_SUCCESS if no errros are detected otherwise an error that has what error is in the PBA Fir + fapi2::ReturnCode p9_pba_coherent_check_pba_fir(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +///@brief calls all of the error checking procedures (ocb_status, check_pba_fir, and status_check) +///@param[in] i_target => P9 chip target +///@return FAPI_RC_SUCCESS if no errors are detected on the PBA + fapi2::ReturnCode p9_pba_coherent_check_status_for_err_handling(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& + i_target); + + + } //extern "C" #endif //_P9_PBA_COHERENT_UTILS_H_ |