Chip address extension workaround for HW423589 (option2), part1

chip_ec_attributes.xml
nest_attributes.xml
p9_sbe_attributes.xml
  add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines
    set of chips which physically support the feature
  add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips
    which need extended address workaround for MCD issue (applied only
    to Nimbus EC 21)
  add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of
    memory groups formed.  Written by p9_mss_eff_grouping.  For
    HW423589_OPTION2, this will default to 512GB
  add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold
    extended address configuration.  Written by p9_sbe_fabricinit (SBE)
    and p9_mss_eff_grouping (HB).  For HW423589_OPTION2, this will
    default to 0b0000_111, consuming all chip ID bits for extended
    addressing.

p9_fbc_utils.C
p9_fbc_utils.H
  extend p9_fbc_utils_get_chip_base_address to support address
  extension, now outputs set of ranges in each msel based on
  ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID

  maintain original function for PPE platform which requires
  knowledge of non-aliased base addresses only, for code size

p9_mss_eff_grouping.C
p9_mss_eff_grouping_errors.xml
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform
  restrict size of groups formed for HW423589_OPTION2

p9_sbe_fabricinit.C
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform
  configure FBC/NMMU extended addressing registers

p9_setup_bars.C
p9_setup_bars_defs.H
p9_setup_bars_errors.xml
  add general purpose support for extended address mode
  for HW423589_OPTION2, configure static MCD setup

p9_hcode_image_defines.H
p9_hcode_image_build.C
  customize SGPE image with address extension configuration to apply

p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scom.initfile
p9.l3.scom.initfile
p9.ncu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_hcd_cache_scominit.C
p9_hcd_cache_scominit.c
p9_pcie_config.C
  set unit address extension configuration on supported chips

p9_rng_init_phase2.C
p9_sbe_scominit.C
p9c_set_inband_addr.C
p9_sbe_load_bootloader.C
p9_sbe_mcs_setup.C
  adapt to alterations in p9_fbc_utils_get_chip_base_address

Change-Id: I614d566c073f1169f04f647057e6e85889f1c237
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48892
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 43 insertions, 6 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
index 4b3a90a4..a160ad18 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
@@ -69,6 +69,13 @@ const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL;
 // cacheline size = 128B
 const uint64_t FABRIC_CACHELINE_SIZE = 0x80;
 
+// chip address extension mask, for HW423589_OPTION2
+// repurposes chip ID(0:2) as address bits
+const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0;
+const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7;
+
+const uint64_t MAX_INTERLEAVE_GROUP_SIZE                  = 0x40000000000ULL; // 4_TB
+const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL;  // 512_GB
 
 //------------------------------------------------------------------------------
 // Function prototypes
@@ -99,17 +106,22 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
 
 ///
-/// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip
+/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip,
+///        accounting for fixed msel assignments, but not aliasing
+///        enabled by chip address extension facility
 ///
 /// @param[in] i_target Reference to processor chip target
 /// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations
-/// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip
-/// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip
-/// @param[out] o_base_address_m Mirrored base address for this chip
-/// @param[out] o_base_address_mmio MMIO base address for this chip
+/// @param[out] o_base_address_nm0 Non-mirrored base address for
+///             this chip (covering msel=0b00)
+/// @param[out] o_base_address_nm1 Non-mirrored base address for
+///             this chip (covering msel=0b01)
+/// @param[out] o_base_address_m Mirrored base address for
+///             this chip (covering msel=0b10)
+/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11)
 /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
 ///
-fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
     const p9_fbc_utils_addr_mode_t i_addr_mode,
     uint64_t& o_base_address_nm0,
@@ -117,4 +129,29 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
     uint64_t& o_base_address_m,
     uint64_t& o_base_address_mmio);
 
+///
+/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip,
+///        accounting for fixed msel assignments as well as variable aliasing
+///        enabled by chip address extension facility
+///
+/// @param[in] i_target Reference to processor chip target
+/// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations
+/// @param[out] o_base_address_nm0 List of non-mirrored base addresses for
+///             this chip (covering msel=0b00), ordered from smallest->largest
+/// @param[out] o_base_address_nm1 List of non-mirrored base addresses for
+///             this chip (covering msel=0b01), ordered from smallest->largest
+/// @param[out] o_base_address_m List of mirrored base addresses for
+///             this chip (covering msel=0b10), ordered from
+///             smallest->largest
+/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11)
+/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9_fbc_utils_addr_mode_t i_addr_mode,
+    std::vector<uint64_t>& o_base_address_nm0,
+    std::vector<uint64_t>& o_base_address_nm1,
+    std::vector<uint64_t>& o_base_address_m,
+    uint64_t& o_base_address_mmio);
+
 #endif // _P9_FBC_UTILS_H_