Chip address extension workaround for HW423589 (option2), part1

chip_ec_attributes.xml
nest_attributes.xml
p9_sbe_attributes.xml
  add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines
    set of chips which physically support the feature
  add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips
    which need extended address workaround for MCD issue (applied only
    to Nimbus EC 21)
  add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of
    memory groups formed.  Written by p9_mss_eff_grouping.  For
    HW423589_OPTION2, this will default to 512GB
  add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold
    extended address configuration.  Written by p9_sbe_fabricinit (SBE)
    and p9_mss_eff_grouping (HB).  For HW423589_OPTION2, this will
    default to 0b0000_111, consuming all chip ID bits for extended
    addressing.

p9_fbc_utils.C
p9_fbc_utils.H
  extend p9_fbc_utils_get_chip_base_address to support address
  extension, now outputs set of ranges in each msel based on
  ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID

  maintain original function for PPE platform which requires
  knowledge of non-aliased base addresses only, for code size

p9_mss_eff_grouping.C
p9_mss_eff_grouping_errors.xml
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform
  restrict size of groups formed for HW423589_OPTION2

p9_sbe_fabricinit.C
  set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform
  configure FBC/NMMU extended addressing registers

p9_setup_bars.C
p9_setup_bars_defs.H
p9_setup_bars_errors.xml
  add general purpose support for extended address mode
  for HW423589_OPTION2, configure static MCD setup

p9_hcode_image_defines.H
p9_hcode_image_build.C
  customize SGPE image with address extension configuration to apply

p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scom.initfile
p9.l3.scom.initfile
p9.ncu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_hcd_cache_scominit.C
p9_hcd_cache_scominit.c
p9_pcie_config.C
  set unit address extension configuration on supported chips

p9_rng_init_phase2.C
p9_sbe_scominit.C
p9c_set_inband_addr.C
p9_sbe_load_bootloader.C
p9_sbe_mcs_setup.C
  adapt to alterations in p9_fbc_utils_get_chip_base_address

Change-Id: I614d566c073f1169f04f647057e6e85889f1c237
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48892
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

15 files changed, 397 insertions, 61 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C
index 2087439c..0884a953 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C
@@ -165,7 +165,7 @@ p9_hcd_cache_scominit(
         // AND we are give second configured EX to process(l_exloop==1)
         if (l_attr_sys_force_all_cores || (!l_exloop))
         {
-            FAPI_EXEC_HWP(l_rc, p9_l2_scom, *l_iter, l_sys);
+            FAPI_EXEC_HWP(l_rc, p9_l2_scom, *l_iter, l_sys, l_chip);
 
             if (l_rc)
             {
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C
index d09438bf..a7f9f751 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C
@@ -36,13 +36,21 @@ constexpr uint64_t literal_8 = 8;
 constexpr uint64_t literal_0b0000 = 0b0000;
 
 fapi2::ReturnCode p9_l2_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
-                             const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1)
+                             const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2)
 {
     {
+        fapi2::ATTR_EC_Type   l_chip_ec;
+        fapi2::ATTR_NAME_Type l_chip_id;
+        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT2, l_chip_id));
+        FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
         fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_TGT1_ATTR_SYSTEM_IPL_PHASE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, TGT1, l_TGT1_ATTR_SYSTEM_IPL_PHASE));
+        fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
+        fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
         uint64_t l_def_L2_EPS_DIVIDE = literal_1;
         fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0));
@@ -89,6 +97,13 @@ fapi2::ReturnCode p9_l2_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x1001080bull, l_scom_buffer ));
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
+            {
+                l_scom_buffer.insert<32, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID );
+                l_scom_buffer.insert<36, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
+            }
+
             l_scom_buffer.insert<4, 4, 60, uint64_t>(literal_0b0001 );
             l_scom_buffer.insert<8, 4, 60, uint64_t>(literal_0b0100 );
             FAPI_TRY(fapi2::putScom(TGT0, 0x1001080bull, l_scom_buffer));
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H
index d2035ba6..89f29c93 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -32,13 +32,13 @@
 
 
 typedef fapi2::ReturnCode (*p9_l2_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
-        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&);
+        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
 
 extern "C"
 {
 
     fapi2::ReturnCode p9_l2_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
-                                 const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1);
+                                 const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2);
 
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C
index bce432ae..c3bbe34c 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C
@@ -58,6 +58,10 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1));
         fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2));
+        fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
+        fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
         fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_TGT1_ATTR_SYSTEM_IPL_PHASE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, TGT1, l_TGT1_ATTR_SYSTEM_IPL_PHASE));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
@@ -107,6 +111,13 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
             constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_OFF = 0x0;
             l_scom_buffer.insert<22, 1, 63, uint64_t>(l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_OFF );
 
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
+            {
+                l_scom_buffer.insert<23, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID );
+                l_scom_buffer.insert<27, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
+            }
+
             if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME))
             {
                 constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_ADDR_HASH_EN_CFG_ON = 0x1;
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
index be26f3b4..b5dbc975 100644
--- a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
@@ -49,6 +49,10 @@ fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
         FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec));
         fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE;
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE));
+        fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID));
+        fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID));
         fapi2::buffer<uint64_t> l_scom_buffer;
         {
             FAPI_TRY(fapi2::getScom( TGT0, 0x1001100aull, l_scom_buffer ));
@@ -74,6 +78,13 @@ fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
             if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
                     && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
             {
+                l_scom_buffer.insert<44, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID );
+                l_scom_buffer.insert<48, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID );
+            }
+
+            if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5)
+                    && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) )
+            {
                 constexpr auto l_EXP_NC_NCMISC_NCSCOMS_TLBIE_PACING_CNT_EN_ON = 0x1;
                 l_scom_buffer.insert<10, 1, 63, uint64_t>(l_EXP_NC_NCMISC_NCSCOMS_TLBIE_PACING_CNT_EN_ON );
             }
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
index 55767769..aa69a0b8 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
@@ -145,7 +145,7 @@ fapi_try_exit:
 
 
 // NOTE: see comments above function prototype in header
-fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
     const p9_fbc_utils_addr_mode_t i_addr_mode,
     uint64_t& o_base_address_nm0,
@@ -198,7 +198,6 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
     }
 
     // else, leave chip ID=0 for the purposes of establishing drawer base address
-
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy),
              "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)");
 
@@ -245,3 +244,128 @@ fapi_try_exit:
     FAPI_DBG("End");
     return fapi2::current_err;
 }
+
+
+// NOTE: see comments above function prototype in header
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9_fbc_utils_addr_mode_t i_addr_mode,
+    std::vector<uint64_t>& o_base_address_nm0,
+    std::vector<uint64_t>& o_base_address_nm1,
+    std::vector<uint64_t>& o_base_address_m,
+    uint64_t& o_base_address_mmio)
+{
+    uint64_t l_base_address_nm0 = 0;
+    uint64_t l_base_address_nm1 = 0;
+    uint64_t l_base_address_m = 0;
+    uint8_t l_addr_extension_group_id;
+    uint8_t l_addr_extension_chip_id;
+    fapi2::buffer<uint64_t> l_addr_extension_enable = 0;
+    uint8_t l_regions_per_msel = 1;
+    std::vector<uint8_t> l_alias_bit_positions;
+    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+
+    fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode;
+    fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2_Type l_hw423589_option2;
+
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target,
+             i_addr_mode,
+             l_base_address_nm0,
+             l_base_address_nm1,
+             l_base_address_m,
+             o_base_address_mmio),
+             "Error from p9_fbc_utils_get_chip_base_address_no_aliases");
+
+    // read attributes defining address extension enable configuration
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, i_target, l_extended_addressing_mode),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, i_target, l_hw423589_option2),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)");
+
+    if (l_extended_addressing_mode)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID,
+                               FAPI_SYSTEM,
+                               l_addr_extension_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)");
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID,
+                               FAPI_SYSTEM,
+                               l_addr_extension_chip_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID");
+
+        // align to RA
+        l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_GROUP_ID_START_BIT,
+                                                FABRIC_ADDR_LS_GROUP_ID_END_BIT - FABRIC_ADDR_LS_GROUP_ID_START_BIT + 1 >
+                                                (l_addr_extension_group_id);
+        l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_CHIP_ID_START_BIT,
+                                                FABRIC_ADDR_LS_CHIP_ID_END_BIT - FABRIC_ADDR_LS_CHIP_ID_START_BIT + 1 >
+                                                (l_addr_extension_chip_id);
+    }
+
+    // walk across bits set in enable bit field, count number of bits set
+    // to determine permutations
+    FAPI_DBG("Address extension enable mask: 0x%016lX", l_addr_extension_enable());
+
+    if (l_addr_extension_enable != 0)
+    {
+        for (uint8_t ii = FABRIC_ADDR_LS_GROUP_ID_START_BIT;
+             ii <= FABRIC_ADDR_LS_CHIP_ID_END_BIT;
+             ii++)
+        {
+            if (l_addr_extension_enable.getBit(ii))
+            {
+                l_regions_per_msel *= 2;
+                l_alias_bit_positions.push_back(ii);
+            }
+        }
+    }
+
+    FAPI_DBG("Valid regions per msel: %d", l_regions_per_msel);
+
+    for (uint8_t l_region = 0;
+         l_region < l_regions_per_msel;
+         l_region++)
+    {
+        fapi2::buffer<uint64_t> l_alias_mask = 0;
+        FAPI_DBG("Generating region: %d", l_region);
+
+        if (l_region)
+        {
+            uint8_t l_value = l_region;
+
+            for (int jj = l_alias_bit_positions.size() - 1;
+                 jj >= 0;
+                 jj--)
+            {
+                l_alias_mask.writeBit(l_value & 1,
+                                      l_alias_bit_positions[jj]);
+                l_value = l_value >> 1;
+            }
+        }
+
+        FAPI_DBG("Mask: 0x%016lX", l_alias_mask());
+
+        // hide region reserved for GPU LPC
+        if (!l_hw423589_option2 || (l_region != 1))
+        {
+            o_base_address_nm0.push_back(l_base_address_nm0 |
+                                         l_alias_mask());
+            o_base_address_m.push_back(l_base_address_m |
+                                       l_alias_mask());
+        }
+
+        // second non-mirrored msel region unusable with HW423589_OPTION2
+        // (no MCD resources available to map)
+        if (!l_hw423589_option2)
+        {
+            o_base_address_nm1.push_back(l_base_address_nm1 |
+                                         l_alias_mask());
+        }
+    }
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
index 4b3a90a4..a160ad18 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
@@ -69,6 +69,13 @@ const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL;
 // cacheline size = 128B
 const uint64_t FABRIC_CACHELINE_SIZE = 0x80;
 
+// chip address extension mask, for HW423589_OPTION2
+// repurposes chip ID(0:2) as address bits
+const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0;
+const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7;
+
+const uint64_t MAX_INTERLEAVE_GROUP_SIZE                  = 0x40000000000ULL; // 4_TB
+const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL;  // 512_GB
 
 //------------------------------------------------------------------------------
 // Function prototypes
@@ -99,17 +106,22 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
 
 ///
-/// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip
+/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip,
+///        accounting for fixed msel assignments, but not aliasing
+///        enabled by chip address extension facility
 ///
 /// @param[in] i_target Reference to processor chip target
 /// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations
-/// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip
-/// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip
-/// @param[out] o_base_address_m Mirrored base address for this chip
-/// @param[out] o_base_address_mmio MMIO base address for this chip
+/// @param[out] o_base_address_nm0 Non-mirrored base address for
+///             this chip (covering msel=0b00)
+/// @param[out] o_base_address_nm1 Non-mirrored base address for
+///             this chip (covering msel=0b01)
+/// @param[out] o_base_address_m Mirrored base address for
+///             this chip (covering msel=0b10)
+/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11)
 /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
 ///
-fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases(
     const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
     const p9_fbc_utils_addr_mode_t i_addr_mode,
     uint64_t& o_base_address_nm0,
@@ -117,4 +129,29 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
     uint64_t& o_base_address_m,
     uint64_t& o_base_address_mmio);
 
+///
+/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip,
+///        accounting for fixed msel assignments as well as variable aliasing
+///        enabled by chip address extension facility
+///
+/// @param[in] i_target Reference to processor chip target
+/// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations
+/// @param[out] o_base_address_nm0 List of non-mirrored base addresses for
+///             this chip (covering msel=0b00), ordered from smallest->largest
+/// @param[out] o_base_address_nm1 List of non-mirrored base addresses for
+///             this chip (covering msel=0b01), ordered from smallest->largest
+/// @param[out] o_base_address_m List of mirrored base addresses for
+///             this chip (covering msel=0b10), ordered from
+///             smallest->largest
+/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11)
+/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9_fbc_utils_addr_mode_t i_addr_mode,
+    std::vector<uint64_t>& o_base_address_nm0,
+    std::vector<uint64_t>& o_base_address_nm1,
+    std::vector<uint64_t>& o_base_address_m,
+    uint64_t& o_base_address_mmio);
+
 #endif // _P9_FBC_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
index 3235616f..7f488ef5 100755
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
@@ -44,6 +44,8 @@
 #include <p9_fbc_utils.H>
 #include <p9_misc_scom_addresses.H>
 #include <p9_misc_scom_addresses_fld.H>
+#include <p9n2_misc_scom_addresses.H>
+#include <p9n2_misc_scom_addresses_fld.H>
 
 //------------------------------------------------------------------------------
 // Constant definitions
@@ -75,14 +77,19 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     fapi2::buffer<uint64_t> l_cmd_data;
     fapi2::buffer<uint64_t> l_status_data_act;
     fapi2::buffer<uint64_t> l_status_data_exp;
+    fapi2::buffer<uint64_t> l_mode_data;
     fapi2::buffer<uint64_t> l_hp_mode_data;
+    fapi2::buffer<uint64_t> l_nmmu_cqmode_data;
     bool l_fbc_is_initialized, l_fbc_is_running;
     fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_pump_mode;
     fapi2::ATTR_PROC_FABRIC_GROUP_ID_Type l_fbc_group_id_abs;
     fapi2::ATTR_PROC_EFF_FABRIC_GROUP_ID_Type l_fbc_group_id_eff;
     fapi2::ATTR_PROC_FABRIC_CHIP_ID_Type l_fbc_chip_id_abs;
     fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID_Type l_fbc_chip_id_eff;
+    fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode;
     uint8_t l_fbc_xlate_addr_to_id = 0;
+    uint8_t l_addr_extension_group_id = 0;
+    uint8_t l_addr_extension_chip_id = 0;
 
     // before fabric is initialized, configure resources which live in hotplug registers
     // but which themselves are not hotpluggable
@@ -96,14 +103,60 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
              "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_CHIP_ID)");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EFF_FABRIC_CHIP_ID, i_target, l_fbc_chip_id_eff),
              "Error from FAPI_ATTR_GET (ATTR_PROC_EFF_FABRIC_CHIP_ID)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, i_target, l_extended_addressing_mode),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)");
+
+    // sample center mode and hotplug mode registers
+    FAPI_TRY(fapi2::getScom(i_target, PU_PB_CENT_SM0_PB_CENT_MODE, l_mode_data),
+             "Error from getScom (PU_PB_CENT_SM0_PB_CENT_MODE)");
 
     FAPI_TRY(fapi2::getScom(i_target, PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR, l_hp_mode_data),
              "Error from getScom (PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR)");
 
+    // update mode register content
+    if (l_extended_addressing_mode)
+    {
+        fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2_Type l_hw423589_option2;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, i_target, l_hw423589_option2),
+                 "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)");
+
+        if (l_hw423589_option2)
+        {
+            l_addr_extension_group_id = CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2;
+            l_addr_extension_chip_id = CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2;
+        }
+
+        // enable extended addressing mode, seed attributes from defaults
+        // and use attribute values to configure fabric -- should allow for testing
+        // alternate configurations via Cronus with const attribute overrides
+        FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID,
+                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                               l_addr_extension_group_id),
+                 "Error from FAPI_ATTR_SET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)");
+        FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID,
+                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                               l_addr_extension_chip_id),
+                 "Error from FAPI_ATTR_SET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)");
+
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID,
+                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                               l_addr_extension_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID,
+                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                               l_addr_extension_chip_id),
+                 "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)");
+
+        l_mode_data.insertFromRight<P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK,
+                                    P9N2_PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_ADDR_EXTENSION_MASK_LEN>
+                                    ((l_addr_extension_group_id << 3) | l_addr_extension_chip_id);
+    }
+
     // determine HW XOR mask based on fabric ID attributes
     l_fbc_xlate_addr_to_id =  ((l_fbc_group_id_abs << 3) | l_fbc_chip_id_abs);
     l_fbc_xlate_addr_to_id ^= ((l_fbc_group_id_eff << 3) | l_fbc_chip_id_eff);
 
+    // update hotplug mode register content
     l_hp_mode_data.insertFromRight<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID,  // XOR mask
                                    PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN>(l_fbc_xlate_addr_to_id);
 
@@ -120,7 +173,17 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
         l_hp_mode_data.setBit<PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP>();
     }
 
-    // write back to all hotplug registers (EAST/CENTER/WEST, NEXT & CURR)
+    // write back to all mode registers (EAST/CENTER/WEST)
+    FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_MODE, l_mode_data),
+             "Error from putScom (PU_PB_CENT_SM0_PB_CENT_MODE)");
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_MODE, l_mode_data),
+             "Error from putScom (PU_PB_EAST_MODE)");
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_MODE, l_mode_data),
+             "Error from putScom (PU_PB_WEST_SM0_PB_WEST_MODE)");
+
+    // write back to all hotplug mode registers (EAST/CENTER/WEST, NEXT & CURR)
     FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR, l_hp_mode_data),
              "Error from putScom (PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR)");
     FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT, l_hp_mode_data),
@@ -136,6 +199,18 @@ p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT, l_hp_mode_data),
              "Error from putScom (PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT)");
 
+    // set NMMU extended addressing configuration prior to fabric init
+    if (l_extended_addressing_mode)
+    {
+        FAPI_TRY(fapi2::getScom(i_target, P9N2_PU_NMMU_MMCQ_PB_MODE_REG, l_nmmu_cqmode_data),
+                 "Error from getScom (P9N2_PU_NMMU_MMCQ_PB_MODE_REG)");
+        l_nmmu_cqmode_data.insertFromRight<P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK,
+                                           P9N2_PU_NMMU_MMCQ_PB_MODE_REG_ADDR_EXT_MASK_LEN>
+                                           ((l_addr_extension_group_id << 3) | l_addr_extension_chip_id);
+        FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_NMMU_MMCQ_PB_MODE_REG, l_nmmu_cqmode_data),
+                 "Error from getScom (P9N2_PU_NMMU_MMCQ_PB_MODE_REG)");
+    }
+
     // check state of fabric pervasive stop control signal
     // if set, this would prohibit all fabric commands from being broadcast
     FAPI_DBG("Checking status of FBC stop ...");
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
index 8bffe723..fed5330f 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
@@ -310,12 +310,13 @@ calc_image_footprint(
     // target base address = (drawer non-mirrored base address) +
     //                       (hostboot HRMOR offset) +
     //                       (bootloader offset)
-    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
-             ABS_FBC_GRP_ID_ONLY,
-             l_drawer_base_address_nm0,
-             l_drawer_base_address_nm1,
-             l_drawer_base_address_m,
-             l_drawer_base_address_mmio),
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(
+                 i_master_chip_target,
+                 ABS_FBC_GRP_ID_ONLY,
+                 l_drawer_base_address_nm0,
+                 l_drawer_base_address_nm1,
+                 l_drawer_base_address_m,
+                 l_drawer_base_address_mmio),
              "Error from p9_fbc_utils_get_chip_base_address (drawer)");
 
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET,
@@ -404,7 +405,7 @@ get_bootloader_config_data(
     FAPI_DBG("Start");
 
     // read platform initialized attributes to determine struct content
-    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_master_chip_target,
              EFF_FBC_GRP_CHIP_IDS,
              l_chip_base_address_nm0,
              l_chip_base_address_nm1,
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
index d65b37c3..3bd71971 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
@@ -226,7 +226,7 @@ p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
         // determine base address
         //   = (drawer non-mirrored base address) + (hostboot HRMOR offset)
         //   min MCS base size is 4GB, local HB will always be below
-        FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+        FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target,
                  ABS_FBC_GRP_ID_ONLY,
                  l_chip_base_address_nm0,
                  l_chip_base_address_nm1,
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index e8fc9904..49a12b75 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -153,12 +153,13 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     }
 
     // determine base address of chip nm/m/mmmio regions in real address space
-    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
-             EFF_FBC_GRP_CHIP_IDS,
-             l_base_addr_nm0,
-             l_base_addr_nm1,
-             l_base_addr_m,
-             l_base_addr_mmio),
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(
+                 i_target,
+                 EFF_FBC_GRP_CHIP_IDS,
+                 l_base_addr_nm0,
+                 l_base_addr_nm1,
+                 l_base_addr_m,
+                 l_base_addr_mmio),
              "Error from p9_fbc_utils_get_chip_base_address");
 
     // set XSCOM BAR
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 817347ce..6d85503e 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -5738,4 +5738,46 @@
     </chipEcFeature>
   </attribute>
   <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE</id>>
+    <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Defines chip HW support for extended addressing mode
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_CUMULUS</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW423589_OPTION2</id>>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Enable extended addressing mode to workaround MCD
+      coherency issue HW423589
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x21</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
 </attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index cce29eb4..ac99a027 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -393,6 +393,28 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
+  <id>ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Address extension enable value for RA 15:18
+  </description>
+  <valueType>uint8</valueType>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Address extension enable value for RA 19:21
+  </description>
+  <valueType>uint8</valueType>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
   <id>ATTR_PROC_FABRIC_GROUP_ID</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description>
@@ -879,6 +901,19 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
+  <id>ATTR_MAX_INTERLEAVE_GROUP_SIZE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The physical capacity of each msel region is 4_TB without extended addressing.
+    This attribute defines the maximum addressable space to be used within each msel,
+    which may be lower than the physical capacity.
+  </description>
+  <valueType>uint64</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
   <id>ATTR_MEM_MIRROR_PLACEMENT_POLICY</id>
   <targetType>TARGET_TYPE_SYSTEM</targetType>
   <description>Define placement policy/scheme for non-mirrored/mirrored memory
@@ -898,22 +933,6 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
-  <id>ATTR_PROC_MEM_BASE</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> The location where the stacking of non-mirrored memory groups
-                of the chip starts.  This address is determined in a fixed
-                manner from the chip's position in the fabric topology (i.e.
-                each chip will consume a fixed portion of the system address
-                map).
-                Set by p9_mss_eff_grouping.
-  </description>
-  <valueType>uint64</valueType>
-  <writeable/>
-  <persistRuntime/>
-  <initToZero/>
-</attribute>
-<!-- ********************************************************************** -->
-<attribute>
   <id>ATTR_PROC_MEM_BASES</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> The address where each memory group starts in the non-mirrored
@@ -946,22 +965,6 @@
 </attribute>
 <!-- ********************************************************************* -->
 <attribute>
-  <id>ATTR_PROC_MIRROR_BASE</id>
-  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-  <description> The location where the stacking of mirrored memory groups
-                of the chip starts.  This address is determined in a fixed
-                manner from the chip's position in the fabric topology (i.e.
-                each chip will consume a fixed portion of the system address
-                map).
-                Set by p9_mss_eff_grouping.
-  </description>
-  <valueType>uint64</valueType>
-  <writeable/>
-  <persistRuntime/>
-  <initToZero/>
-</attribute>
-<!-- ********************************************************************** -->
-<attribute>
   <id>ATTR_PROC_MIRROR_BASES</id>
   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
   <description> The address where each memory group starts in the mirrored
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 15de2e47..dcb1a3ca 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -510,6 +510,14 @@ attribute tank
            <virtual/>
   </entry>
   <entry>
+           <name>ATTR_CHIP_EC_FEATURE_HW423589_OPTION2</name>
+           <virtual/>
+  </entry>
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE</name>
+           <virtual/>
+  </entry>
+  <entry>
            <name>ATTR_CHIP_EC_FEATURE_HW414700</name>
            <virtual/>
   </entry>
@@ -541,4 +549,12 @@ attribute tank
            <name>ATTR_SBE_ADDR_KEY_STASH_ADDR</name>
            <value>0x0000000000000000</value>
   </entry>
+  <entry>
+           <name>ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID</name>
+           <value>0x00</value>
+  </entry>
+  <entry>
+           <name>ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID</name>
+           <value>0x00</value>
+  </entry>
 </entries>
diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C
index b49a2886..c2a417c6 100644
--- a/src/sbefw/sbecmdiplcontrol.C
+++ b/src/sbefw/sbecmdiplcontrol.C
@@ -906,7 +906,7 @@ ReturnCode istepLoadBootLoader( sbeIstepHwp_t i_hwp)
         FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET,
                       FAPI_SYSTEM,
                       l_hostboot_hrmor_offset);
-        rc = p9_fbc_utils_get_chip_base_address(
+        rc = p9_fbc_utils_get_chip_base_address_no_aliases(
                                     proc,
                                     ABS_FBC_GRP_ID_ONLY,
                                     drawer_base_address_nm0,