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| author | Joe McGill <jmcgill@us.ibm.com> | 2016-12-07 12:58:40 -0600 |
|---|---|---|
| committer | spashabk-in <shakeebbk@in.ibm.com> | 2016-12-20 05:18:51 -0600 |
| commit | 1530962a1d0646bfab325c825f1426843298f8b4 (patch) | |
| tree | fdee0db804d04b3c92b75bdbe7437fdcf2574698 /src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H | |
| parent | 2c5d1b4332ed2dd3780f38582ea28ac134a00d62 (diff) | |
| download | talos-sbe-1530962a1d0646bfab325c825f1426843298f8b4.tar.gz talos-sbe-1530962a1d0646bfab325c825f1426843298f8b4.zip | |
p9_build_smp -- enable MC fastpath
when issuing pbob.enable_all via the ADU HW state machine (ALTD_WITH_POST_INIT
in the ADU CMD register) the op is issued with a tsize field that disables
the FBC to MC fastpath
to workaround, this change will issue an additional quiesce/init sequence
after the final switch AB, with a user programmed tsize field that properly
sets the fastpath enable bit
Change-Id: If1e4b9df4526990c413d0e0a924ab2f692963113
CQ: HW397129
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33535
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33540
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H index 69b66c39..2f82269c 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H @@ -81,8 +81,9 @@ extern"C" { CACHE_INHIBIT = 0, DMA_PARTIAL = 1, - PB_OPER = 2, - PMISC_OPER = 3 + PB_DIS_OPER = 2, + PMISC_OPER = 3, + PB_INIT_OPER = 4 }; // Transaction size |
