p9_build_smp -- enable MC fastpath

  when issuing pbob.enable_all via the ADU HW state machine (ALTD_WITH_POST_INIT
  in the ADU CMD register) the op is issued with a tsize field that disables
  the FBC to MC fastpath

  to workaround, this change will issue an additional quiesce/init sequence
  after the final switch AB, with a user programmed tsize field that properly
  sets the fastpath enable bit

Change-Id: If1e4b9df4526990c413d0e0a924ab2f692963113
CQ: HW397129
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33535
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33540
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

3 files changed, 38 insertions, 16 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
index 2fe9c74b..1bec59ff 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
@@ -117,7 +117,8 @@ extern "C"
     const uint32_t ALTD_CMD_SCOPE_GROUP         = 0b00000011;
 
     // Values for PB operations
-    const uint32_t ALTD_CMD_PB_OPERATION_TSIZE  = 0b00001000;
+    const uint32_t ALTD_CMD_PB_DIS_OPERATION_TSIZE  = 0b00001000;
+    const uint32_t ALTD_CMD_PB_INIT_OPERATION_TSIZE  = 0b00001011;
     const uint32_t ALTD_CMD_SCOPE_SYSTEM        = 0b00000101;
 
     // Values for PMISC operations
@@ -316,7 +317,7 @@ extern "C"
         fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0);
         fapi2::buffer<uint64_t> altd_addr_reg_data(i_address);
         fapi2::buffer<uint64_t> altd_data_reg_data(0x0);
-        fapi2::buffer<uint64_t> altd_option_reg(0x0);
+        fapi2::buffer<uint64_t> altd_option_reg_data(0x0);
         p9_ADU_oper_flag l_myAduFlag;
         p9_ADU_oper_flag::OperationType_t l_operType;
         p9_ADU_oper_flag::Transaction_size_t l_transSize;
@@ -458,7 +459,8 @@ extern "C"
         // ---------------------------------------------
         // Setting for PB and PMISC operations
         // ---------------------------------------------
-        if ( (l_operType == p9_ADU_oper_flag::PB_OPER) ||
+        if ( (l_operType == p9_ADU_oper_flag::PB_DIS_OPER) ||
+             (l_operType == p9_ADU_oper_flag::PB_INIT_OPER) ||
              (l_operType == p9_ADU_oper_flag::PMISC_OPER) )
         {
 
@@ -485,21 +487,38 @@ extern "C"
             // Set TM_QUIESCE
             altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>();
 
-
             // ---------------------------------------------------
             // PB specific: TTYPE & TSIZE
             // ---------------------------------------------------
-            if (l_operType == p9_ADU_oper_flag::PB_OPER)
+            if ((l_operType == p9_ADU_oper_flag::PB_DIS_OPER) ||
+                (l_operType == p9_ADU_oper_flag::PB_INIT_OPER))
             {
-                FAPI_DBG("ADU operation type: PB");
+                FAPI_DBG("ADU operation type: PB OPERATION");
 
                 // Set TTYPE
                 altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT,
                                                   ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PB_OPER);
 
-                // TSIZE for PB operation is fixed value: 0b00001000
-                altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
-                                                  ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PB_OPERATION_TSIZE);
+                if (l_operType == p9_ADU_oper_flag::PB_DIS_OPER)
+                {
+                    // TSIZE for PB operation is fixed value: 0b00001000
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PB_DIS_OPERATION_TSIZE);
+                }
+                else
+                {
+                    // Set up quiesce
+                    altd_option_reg_data.setBit<FBC_ALTD_WITH_PRE_QUIESCE>();
+                    altd_option_reg_data.insertFromRight<FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT,
+                                                         FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS>
+                                                         (QUIESCE_SWITCH_WAIT_COUNT);
+                    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_OPTION_REG, altd_option_reg_data),
+                             "Error writing to ALTD_OPTION Register");
+
+                    // TSIZE for PB operation is fixed value: 0b00001011
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PB_INIT_OPERATION_TSIZE);
+                }
             }
 
             // ---------------------------------------------------
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
index 69b66c39..2f82269c 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
@@ -81,8 +81,9 @@ extern"C"
             {
                 CACHE_INHIBIT = 0,
                 DMA_PARTIAL   = 1,
-                PB_OPER       = 2,
-                PMISC_OPER    = 3
+                PB_DIS_OPER   = 2,
+                PMISC_OPER    = 3,
+                PB_INIT_OPER  = 4
             };
 
             // Transaction size
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
index aed13132..e11a3c6a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
@@ -52,8 +52,9 @@ extern "C"
         // Operation type
         // 0b000: DMA partial
         // 0b001: Cache-inhibited
-        // 0b010: PB op
+        // 0b010: PB disable op
         // 0b011: PMISC op
+        // 0b100: PB enable op
         FLAG_ADU_TTYPE = 0xE0000000ull,                        // Bits 0:2
 
         // Utilize ADU HW auto-increment function
@@ -109,10 +110,11 @@ extern "C"
     };
 
 // Operation type values
-    const uint32_t FLAG_ADU_TTYPE_DMA   = 0x00000000ull;   // DMA partial
-    const uint32_t FLAG_ADU_TTYPE_CI    = 0x20000000ull;   // Cache inhibit
-    const uint32_t FLAG_ADU_TTYPE_PB    = 0x40000000ull;   // PB operation
-    const uint32_t FLAG_ADU_TTYPE_PMISC = 0x60000000ull;   // Switch operation
+    const uint32_t FLAG_ADU_TTYPE_DMA     = 0x00000000ull;   // DMA partial
+    const uint32_t FLAG_ADU_TTYPE_CI      = 0x20000000ull;   // Cache inhibit
+    const uint32_t FLAG_ADU_TTYPE_PB_DIS  = 0x40000000ull;   // PB operation (disable)
+    const uint32_t FLAG_ADU_TTYPE_PMISC   = 0x60000000ull;   // Switch operation
+    const uint32_t FLAG_ADU_TTYPE_PB_INIT = 0x80000000ull;   // PB operation (init)
 
 // Flag size values
     const uint32_t FLAG_SIZE_TSIZE_1   = 0x00000000ull;