RTC: 126147

FIFO Reset support

Change-Id: I1654d4a5a72bebd0764c2f560030057bf984cc31
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23042
Tested-by: Jenkins Server
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>

4 files changed, 111 insertions, 0 deletions

diff --git a/sbe/test/test.xml b/sbe/test/test.xml
index 07d1f1a0..23f0d46f 100755
--- a/sbe/test/test.xml
+++ b/sbe/test/test.xml
@@ -11,6 +11,7 @@
           <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testCntlInstruction.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testRegAccess.xml</include>
+          <include>../simics/targets/p9_nimbus/sbeTest/testFifoReset.xml</include>
           <testcase>
               <simcmd>sbe-trace 0</simcmd>
           </testcase>
diff --git a/sbe/test/testFifoReset.py b/sbe/test/testFifoReset.py
new file mode 100644
index 00000000..9660df2e
--- /dev/null
+++ b/sbe/test/testFifoReset.py
@@ -0,0 +1,57 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest")
+import testUtil
+
+err = False
+
+# Test data that only contains the command header
+TESTDATA = [0, 0, 0, 3,
+            0, 0, 0xA1, 0x01]
+
+# Complete test data
+TESTDATA_FULL = [0, 0, 0, 3,
+                 0, 0, 0xA1, 0x01,
+                 0, 0x02, 0x00, 0x01]
+
+# Get capabilities command. This will ensure the DS FIFO gets full
+TESTDATA_2 = [0, 0, 0, 2,
+              0, 0, 0xA8, 0x02]
+
+def main():
+    try:
+        testUtil.runCycles(10000000)
+        # Send a partial chip-op
+        testUtil.writeUsFifo(TESTDATA)
+        testUtil.resetFifo()
+        # Make sure both the upstream and downstrem FIFOs are clear after the reset
+        testUtil.waitTillUsFifoEmpty()
+        testUtil.waitTillDsFifoEmpty()
+        # Now send a complete chip-op on the upstream FIFO
+        testUtil.writeUsFifo(TESTDATA_FULL)
+        testUtil.writeEot()
+        testUtil.resetFifo()
+        # Make sure both the upstream and downstrem FIFOs are clear after the reset
+        testUtil.waitTillUsFifoEmpty()
+        testUtil.waitTillDsFifoEmpty()
+        # Now send a get capabilities chip-op, so that in response, the DS FIFO
+        # gets full before we do a reset
+        testUtil.writeUsFifo(TESTDATA_2)
+        testUtil.writeEot()
+        testUtil.resetFifo()
+        # Make sure both the upstream and downstrem FIFOs are clear after the reset
+        testUtil.waitTillUsFifoEmpty()
+        testUtil.waitTillDsFifoEmpty()
+    except:
+        print("\nTest completed with error(s), Raise error")
+        raise
+    print("\nTest completed with no errors")
+
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testFifoReset.xml b/sbe/test/testFifoReset.xml
new file mode 100644
index 00000000..42c125d9
--- /dev/null
+++ b/sbe/test/testFifoReset.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <!-- SBE FIFO reset Test case -->
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testFifoReset.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+      <!-- An istep chip-op should succeed post the FIFO reset  -->
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testIstepInvalid.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
diff --git a/sbe/test/testUtil.py b/sbe/test/testUtil.py
index 3af06ffc..55802c0c 100644
--- a/sbe/test/testUtil.py
+++ b/sbe/test/testUtil.py
@@ -32,6 +32,47 @@ def readEot():
     checkEqual( (status[3] & 0x80), 0x80 );
     read(lbus, 0x2440, 4)
 
+def resetFifo():
+    write(lbus, 0x240C, (0, 0, 0, 1))
+    return
+
+def readUsFifoStatus():
+    status = read(lbus, 0x2404, 4)
+    return status
+
+def readDsFifoStatus():
+    status = read(lbus, 0x2444, 4)
+    return status
+
+def waitTillFifoEmpty(func):
+    count = 0
+    loop = True
+    while(loop is True):
+        status = func()
+        if(status[1] == 0x10):
+            loop = False
+            break
+        else:
+            count = count + 1
+            runCycles(200000)
+            if(count > 10):
+                raise Exception('Timed out waiting for FIFO to get flushed')
+
+
+def waitTillUsFifoEmpty():
+    try:
+        waitTillFifoEmpty(readUsFifoStatus)
+    except:
+        raise Exception('US FIFO did not get empty')
+
+
+def waitTillDsFifoEmpty():
+    try:
+        waitTillFifoEmpty(readDsFifoStatus)
+    except:
+        raise Exception('DS FIFO did not get empty')
+
+
 # This function will only read the entry but will not compare it
 # with anything. This can be used to flush out enteries.
 def readDsEntry(entryCount):