Get/Put Occ Sram Support

Change-Id: I8f4669bfbca3d58d8f55d5d115d370bfa99ae49d
RTC:128980
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20658
Tested-by: Jenkins Server
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>

4 files changed, 116 insertions, 1 deletions

diff --git a/sbe/test/test.xml b/sbe/test/test.xml
index d8ad0a2c..ce3ee1e1 100755
--- a/sbe/test/test.xml
+++ b/sbe/test/test.xml
@@ -32,6 +32,7 @@
           <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testGeneric.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testPutGetMem.xml</include>
+          <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include>
           <testcase>
               <simcmd>sbe-trace</simcmd>
           </testcase>
diff --git a/sbe/test/testGetCapabilities.py b/sbe/test/testGetCapabilities.py
index 8fa9d241..d7616eb7 100755
--- a/sbe/test/testGetCapabilities.py
+++ b/sbe/test/testGetCapabilities.py
@@ -15,7 +15,7 @@ EXPDATA1 = [0x0,0x0,0x0,0x0,
            0x0,0x0,0x0,0x0,
            0x00,0x0,0x0,0x0];
 
-EXPDATA2 = [0xa4,0x0,0x0,0x03,
+EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc
            0x0,0x0,0x0,0x0,
            0x0,0x0,0x0,0x0,
            0x0,0x0,0x0,0x0,
diff --git a/sbe/test/testSram.py b/sbe/test/testSram.py
new file mode 100644
index 00000000..2ffa35ee
--- /dev/null
+++ b/sbe/test/testSram.py
@@ -0,0 +1,106 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+LOOP_COUNT = 1
+
+PUTSRAM_OCC_CNTLDATA =  [0,0,0,0x20,
+                         0,0,0xa4,0x04, #magic
+                         0,0,0,0x01,
+                         0xe7,0xf0,0x00,0x00, #addr
+                         0,0,0x01,0x00]  # length
+
+PUTSRAM_OCC_TESTDATA =  [0xab,0xcd,0xef,0x12,
+                         0xba,0xdc,0xfe,0x21,
+                         0x34,0x56,0x78,0x9a,
+                         0x43,0x65,0x87,0xa9,
+                         0xab,0xcd,0xef,0x12,
+                         0xba,0xdc,0xfe,0x21,
+                         0x34,0x56,0x78,0x9a,
+                         0x43,0x65,0x87,0xa9]
+
+PUTSRAM_OCC_EXP_CNTLDATA  =  [0,0,0x01,0x00,
+                              0xc0,0xde,0xa4,0x04,
+                              0x0,0x0,0x0,0x0,
+                              0x00,0x0,0x0,0x03]
+
+GETSRAM_OCC_CNTLDATA =  [0,0,0,0x5,
+                         0,0,0xa4,0x03,
+                         0,0,0,0x01,
+                         0xe7,0xf0,0x00,0x00,  #address
+                         0x00,0x00,0x01,0x00]  # length of data
+
+GETSRAM_OCC_EXP_TESTDATA =  [0xab,0xcd,0xef,0x12,  #data
+                             0xba,0xdc,0xfe,0x21,
+                             0x34,0x56,0x78,0x9a,
+                             0x43,0x65,0x87,0xa9,
+                             0xab,0xcd,0xef,0x12,
+                             0xba,0xdc,0xfe,0x21,
+                             0x34,0x56,0x78,0x9a,
+                             0x43,0x65,0x87,0xa9]
+
+GETSRAM_OCC_EXP_CNTLDATA =   [0x00,0x00,0x01,0x00,  # length
+                              0xc0,0xde,0xa4,0x03,
+                              0x0,0x0,0x0,0x0,
+                              0x00,0x0,0x0,0x03];
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+
+    # Put Occ Sram test - Linear - Can be tested over Normal
+    # Debug mode
+    testUtil.writeUsFifo( PUTSRAM_OCC_CNTLDATA )
+    # Write 32 bytes of data 8 times => 32*8 = 256 = 0x100
+    i_cnt = 0
+    while i_cnt < 8:
+        testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA )
+        i_cnt = i_cnt+1
+
+    testUtil.writeEot( )
+
+    # Read the expected data for put sram
+    testUtil.readDsFifo( PUTSRAM_OCC_EXP_CNTLDATA )
+    testUtil.readEot( )
+
+    # Get Sram Linear
+    testUtil.writeUsFifo( GETSRAM_OCC_CNTLDATA )
+    testUtil.writeEot( )
+
+    # Read the Expected Data for get Sram
+    i_cnt = 0
+    while i_cnt < 8:
+        testUtil.readDsFifo( GETSRAM_OCC_EXP_TESTDATA )
+        i_cnt = i_cnt+1
+
+    testUtil.readDsFifo( GETSRAM_OCC_EXP_CNTLDATA )
+    testUtil.readEot( )
+
+    # Put Occ Sram test - Circular - Can be enabled once we get
+    # valid address range to read the circular data
+    #testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA_1 )
+    #testUtil.writeEot( )
+    #testUtil.readDsFifo( PUTSRAM_OCC_EXPDATA_1 )
+    #testUtil.readEot( )
+    #testUtil.writeUsFifo( GETSRAM_OCC_TESTDATA_1 )
+    #testUtil.writeEot( )
+    #testUtil.readDsFifo( GETSRAM_OCC_EXPDATA_1 )
+    #testUtil.readEot( )
+
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/sbe/test/testSram.xml b/sbe/test/testSram.xml
new file mode 100755
index 00000000..b44ddb6d
--- /dev/null
+++ b/sbe/test/testSram.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <testcase>
+          <!-- TODO RTC - 150091 - Add the Occ sram test case -->
+          <!--<simcmd>run-python-file targets/p9_nimbus/sbeTest/testSram.py</simcmd>-->
+          <!--<exitonerror>yes</exitonerror>-->
+      </testcase>
+