diff options
author | Raja Das <rajadas2@in.ibm.com> | 2016-02-09 03:10:11 -0600 |
---|---|---|
committer | AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> | 2016-03-24 00:57:24 -0400 |
commit | 9b222a06e7013429df09bf7ebbbaead076ad5acc (patch) | |
tree | 61ba8d1d4c772ffcc0c0752616db44469afd6a69 /sbe | |
parent | 19139d2eb05f1211bd21e5ee3689ae9a215cf0fc (diff) | |
download | talos-sbe-9b222a06e7013429df09bf7ebbbaead076ad5acc.tar.gz talos-sbe-9b222a06e7013429df09bf7ebbbaead076ad5acc.zip |
Get/Put Occ Sram Support
Change-Id: I8f4669bfbca3d58d8f55d5d115d370bfa99ae49d
RTC:128980
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/20658
Tested-by: Jenkins Server
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Diffstat (limited to 'sbe')
-rw-r--r-- | sbe/image/Makefile | 15 | ||||
-rw-r--r-- | sbe/image/img_defs.mk | 6 | ||||
-rw-r--r-- | sbe/sbefw/sbeSpMsg.H | 51 | ||||
-rw-r--r-- | sbe/sbefw/sbe_sp_intf.H | 19 | ||||
-rw-r--r-- | sbe/sbefw/sbecmdgeneric.C | 6 | ||||
-rw-r--r-- | sbe/sbefw/sbecmdiplcontrol.C | 2 | ||||
-rw-r--r-- | sbe/sbefw/sbecmdmemaccess.C | 24 | ||||
-rw-r--r-- | sbe/sbefw/sbecmdmemaccess.H | 18 | ||||
-rw-r--r-- | sbe/sbefw/sbecmdparser.C | 13 | ||||
-rw-r--r-- | sbe/sbefw/sbecmdsram.C | 333 | ||||
-rw-r--r-- | sbe/sbefw/sbecmdsram.H | 41 | ||||
-rw-r--r-- | sbe/sbefw/sbefwfiles.mk | 2 | ||||
-rwxr-xr-x | sbe/test/test.xml | 1 | ||||
-rwxr-xr-x | sbe/test/testGetCapabilities.py | 2 | ||||
-rw-r--r-- | sbe/test/testSram.py | 106 | ||||
-rwxr-xr-x | sbe/test/testSram.xml | 8 |
16 files changed, 592 insertions, 55 deletions
diff --git a/sbe/image/Makefile b/sbe/image/Makefile index da00f581..f42f82ed 100644 --- a/sbe/image/Makefile +++ b/sbe/image/Makefile @@ -110,11 +110,17 @@ SIMICS_PPE_TAR_FILES += $(OBJDIR)/../../tools/ppetracepp/ppe2fsp SIMICS_PPE_TAR_FILES += $(OBJDIR)/trexStringFile SIMICS_BB_TAR_FILES += $(OBJDIR)/../build/simics/* +# Common Pm libraries +PM_MAKE_DIR := $(PM_SRCDIR) +LIB_DIRS += -L$(OBJDIR)/pm +PMLIB := $(OBJDIR)/pm/libpm.a +LLIBS += -lpm + SBE_TOOLS := $(TOOLS_IMAGE_DIR)/sbe_default_tool P9_XIP_TOOL := $(P9_XIP_BINDIR)/p9_xip_tool -LINK_OBJS = $(OBJS) $(SBEFWLIB) $(PKLIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(HWPLIB) $(P2PLIB) $(PERVLIB) $(NESTLIB) +LINK_OBJS = $(OBJS) $(SBEFWLIB) $(PKLIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(HWPLIB) $(P2PLIB) $(PERVLIB) $(NESTLIB) $(PMLIB) # Define the objects OBJS := $(addprefix $(OBJDIR)/, $(TOP_OBJECTS)) @@ -256,7 +262,7 @@ $(OBJDIR): $(TOOLS_ATTR_DIR)/ppeCreateIfAttrService.pl $(PPE_FAPI2_DIR)/include $(IMPORT_XML_DIR)/attribute_info/p9_sbe_attributes.xml $(ATTRFILES) mkdir -p $(OBJDIR) -.PHONY: clean topfixedheaders $(PKLIB) $(P2PLIB) $(PPELIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(PERVLIB) $(NESTLIB) $(HWPLIB) buildInfo pibMemAttrSet +.PHONY: clean topfixedheaders $(PKLIB) $(P2PLIB) $(PPELIB) $(FAPI2LIB) $(CACHELIB) $(CORELIB) $(PERVLIB) $(NESTLIB) $(PMLIB) $(HWPLIB) buildInfo pibMemAttrSet #errxml: topfixedheaders attrids platattr attrserv @@ -306,6 +312,11 @@ $(NESTLIB): @echo "Processing nest makefile" $(MAKE) -I $(IMAGE_SRCDIR) -C $(NEST_MAKE_DIR) -f Makefile +#Build the pm code +$(PMLIB): + @echo "Processing pm makefile" + $(MAKE) -I $(IMAGE_SRCDIR) -C $(PM_MAKE_DIR) -f Makefile + #Build the HWP lib procedures $(HWPLIB): @echo "Processing HWP lib makefile" diff --git a/sbe/image/img_defs.mk b/sbe/image/img_defs.mk index ba883473..a9669af8 100644 --- a/sbe/image/img_defs.mk +++ b/sbe/image/img_defs.mk @@ -66,6 +66,10 @@ ifndef NEST_SRCDIR export NEST_SRCDIR = $(abspath ../../import/chips/p9/procedures/hwp/nest) endif +ifndef PM_SRCDIR +export PM_SRCDIR = $(abspath ../../import/chips/p9/procedures/hwp/pm) +endif + ifndef HWPLIB_SRCDIR export HWPLIB_SRCDIR = $(abspath ../../import/chips/p9/procedures/hwp/lib) endif @@ -79,7 +83,7 @@ export P9_XIP_BINDIR = $(P9_XIP_SRCDIR)/bin endif ifndef IMG_INCLUDES -export IMG_INCLUDES = -I$(P9_XIP_SRCDIR) -I$(IMAGE_SRCDIR) -I$(CACHE_SRCDIR) -I$(CORE_SRCDIR) -I$(PERV_SRCDIR) -I$(NEST_SRCDIR) +export IMG_INCLUDES = -I$(P9_XIP_SRCDIR) -I$(IMAGE_SRCDIR) -I$(CACHE_SRCDIR) -I$(CORE_SRCDIR) -I$(PERV_SRCDIR) -I$(NEST_SRCDIR) -I$(PM_SRCDIR) endif ifndef BASE_OBJDIR diff --git a/sbe/sbefw/sbeSpMsg.H b/sbe/sbefw/sbeSpMsg.H index a60ae274..ff49e2f2 100644 --- a/sbe/sbefw/sbeSpMsg.H +++ b/sbe/sbefw/sbeSpMsg.H @@ -78,7 +78,43 @@ typedef struct secondaryStatus = SBE_SEC_OPERATION_SUCCESSFUL; } -}sbeResponseGenericHeader_t; +}sbeRespGenHdr_t; + +/** + * @brief structure for generic Resp header with Len for fifo response. + * + */ +typedef struct +{ + uint32_t respLen; + sbeRespGenHdr_t respHdr; + + /** + * @brief set response length + * + * @param[in] i_len Length + * + * @return + */ + void setLength( const uint32_t i_len ) + { + respLen = i_len; + } + + /** + * @brief set initial values for response header + * + * @note We did not set this in constructor as based on use case + * it is possible that g_sbeCmdHdr does not have proper + * values at time of object creation. + * + */ + void init() + { + respHdr.init(); + } +}sbeRespGenHdrWithLen_t; + /** * @brief structure for ffdc header for fifo response. @@ -327,6 +363,17 @@ typedef struct }sbeMemAccessReqMsgHdr_t; +/** + * @brief Structure for SBE OCC Get/Put Sram Access ChipOps (0xA403/A404) + */ +typedef struct +{ + uint32_t reserved:24; // Not used + sbeSramAccessMode mode:8; // Channel select 0-3 + uint32_t addr; // 32-Bit Memory Address + uint32_t len; // Length of Data in Bytes +}sbeOccSramAccessReqMsgHdr_t; + // Maximum number of capabilities static const uint32_t SBE_MAX_CAPABILITIES = 18; @@ -345,7 +392,7 @@ typedef struct sbeCapabilityRespMsg }sbeCapabilityRespMsg_t; // TODO via RTC 128658 -// We may be able to replace this structure by sbeResponseGenericHeader_t +// We may be able to replace this structure by sbeRespGenHdr_t /** * @brief Command response structure to hold the primary and secondary diff --git a/sbe/sbefw/sbe_sp_intf.H b/sbe/sbefw/sbe_sp_intf.H index b536bd9f..c2f5b546 100644 --- a/sbe/sbefw/sbe_sp_intf.H +++ b/sbe/sbefw/sbe_sp_intf.H @@ -91,8 +91,8 @@ enum sbeMemoryAccesCommands { SBE_CMD_GETMEM = 0x01, /* Get Memory (Proc/PBA) */ SBE_CMD_PUTMEM = 0x02, /* Put Memory (Proc/PBA) */ - SBE_CMD_GETSRAM = 0x03, /* Get Memory (SRAM) */ - SBE_CMD_PUTSRAM = 0x04, /* Put Memory (SRAM) */ + SBE_CMD_GETSRAM_OCC = 0x03, /* Get Memory (OCC SRAM) */ + SBE_CMD_PUTSRAM_OCC = 0x04, /* Put Memory (OCC SRAM) */ }; /** @@ -247,8 +247,10 @@ enum PUT_RING_SUPPPORTED = 0xA3000002, GET_MEMORY_SUPPPORTED = 0xA4000001, PUT_MEMORY_SUPPPORTED = 0xA4000002, - GET_SRAM_SUPPPORTED = 0xA4000004, - PUT_SRAM_SUPPPORTED = 0xA4000008, + GET_SRAM_OCC_SUPPPORTED = 0xA4000004, + PUT_SRAM_OCC_SUPPPORTED = 0xA4000008, + GET_SRAM_CME_SUPPPORTED = 0xA4000010, + PUT_SRAM_CME_SUPPPORTED = 0xA4000011, GET_REGISTER_SUPPPORTED = 0xA5000001, PUT_REGISTER_SUPPPORTED = 0xA5000002, READ_FAST_ARRAY_SUPPPORTED = 0xA6000001, @@ -275,6 +277,15 @@ enum sbeMemoryAccessFlags SBE_MEM_ACCESS_FLAGS_FAST_MODE_ON = 0x00000020, }; +/** + * @brief enum for various modes for Sram Access + */ +enum sbeSramAccessMode +{ + NORMAL_MODE = 0x1, + DEBUG_MODE = 0x2, + CIRCULAR_MODE = 0x3, +}; #ifdef __cplusplus diff --git a/sbe/sbefw/sbecmdgeneric.C b/sbe/sbefw/sbecmdgeneric.C index 7ad0016b..eda09d88 100644 --- a/sbe/sbefw/sbecmdgeneric.C +++ b/sbe/sbefw/sbecmdgeneric.C @@ -38,7 +38,9 @@ sbeCapabilityRespMsg::sbeCapabilityRespMsg() capability[MEMORY_CAPABILITY_START_IDX] = GET_MEMORY_SUPPPORTED | - PUT_MEMORY_SUPPPORTED ; + PUT_MEMORY_SUPPPORTED | + GET_SRAM_OCC_SUPPPORTED | + PUT_SRAM_OCC_SUPPPORTED; } // Functions //---------------------------------------------------------------------------- @@ -48,7 +50,7 @@ uint32_t sbeGetCapabilities (uint8_t *i_pArg) SBE_DEBUG(SBE_FUNC); uint32_t rc = SBE_SEC_OPERATION_SUCCESSFUL; uint32_t len = 0; - sbeResponseGenericHeader_t respHdr; + sbeRespGenHdr_t respHdr; respHdr.init(); sbeCapabilityRespMsg_t capMsg; diff --git a/sbe/sbefw/sbecmdiplcontrol.C b/sbe/sbefw/sbecmdiplcontrol.C index ee212cf4..72d86215 100644 --- a/sbe/sbefw/sbecmdiplcontrol.C +++ b/sbe/sbefw/sbecmdiplcontrol.C @@ -217,7 +217,7 @@ uint32_t sbeHandleIstep (uint8_t *i_pArg) ReturnCode fapiRc = FAPI2_RC_SUCCESS; uint32_t len = 0; sbeIstepReqMsg_t req; - sbeResponseGenericHeader_t respHdr; + sbeRespGenHdr_t respHdr; respHdr.init(); sbeResponseFfdc_t ffdc; diff --git a/sbe/sbefw/sbecmdmemaccess.C b/sbe/sbefw/sbecmdmemaccess.C index b47e00e9..6a55e66c 100644 --- a/sbe/sbefw/sbecmdmemaccess.C +++ b/sbe/sbefw/sbecmdmemaccess.C @@ -35,7 +35,7 @@ uint32_t sbeMemAccess_Wrap(const bool i_flagGetOrPut) uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; ReturnCode l_fapiRc = FAPI2_RC_SUCCESS; - sbeResponseGenericHeader_t l_respHdr; + sbeRespGenHdr_t l_respHdr; l_respHdr.init(); sbeResponseFfdc_t l_ffdc; @@ -353,26 +353,4 @@ uint32_t sbeGetMem (uint8_t *i_pArg) #undef SBE_FUNC } -///////////////////////////////////////////////////// -////////////////////////////////////////////////////// -uint32_t sbeGetSram (uint8_t *i_pArg) -{ - #define SBE_FUNC " sbeGetSram " - uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; - - - return l_rc; - #undef SBE_FUNC -} -///////////////////////////////////////////////////// -////////////////////////////////////////////////////// -uint32_t sbePutSram (uint8_t *i_pArg) -{ - #define SBE_FUNC " sbePutSram " - uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; - - - return l_rc; - #undef SBE_FUNC -} diff --git a/sbe/sbefw/sbecmdmemaccess.H b/sbe/sbefw/sbecmdmemaccess.H index b8c01922..9fcaf5f0 100644 --- a/sbe/sbefw/sbecmdmemaccess.H +++ b/sbe/sbefw/sbecmdmemaccess.H @@ -28,23 +28,5 @@ uint32_t sbeGetMem (uint8_t *i_pArg); */ uint32_t sbePutMem (uint8_t *i_pArg); -/** - * @brief sbeGetSram : Implements SBE Get SRAM ChipOp - * - * @param[in] i_pArg Buffer to be passed to the function (not used as of now) - * - * @return Rc from the FIFO access utility - */ -uint32_t sbeGetSram (uint8_t *i_pArg); - -/** - * @brief sbePutSram : Implements SBE Put SRAM ChipOp - * - * @param[in] i_pArg Buffer to be passed to the function (not used as of now) - * - * @return Rc from the FIFO access utility - */ -uint32_t sbePutSram (uint8_t *i_pArg); - #endif /* __SBEFW_SBECMDMEMACCESS_H */ diff --git a/sbe/sbefw/sbecmdparser.C b/sbe/sbefw/sbecmdparser.C index 6adbb1ca..f71e5a96 100644 --- a/sbe/sbefw/sbecmdparser.C +++ b/sbe/sbefw/sbecmdparser.C @@ -11,6 +11,7 @@ #include "sbecmdgeneric.H" #include "sbecmdmemaccess.H" #include "sbecmdcntrldmt.H" +#include "sbecmdsram.H" #include "sbetrace.H" #include "sbe_sp_intf.H" #include "sbeHostMsg.H" @@ -90,6 +91,15 @@ static sbeCmdStruct_t g_sbeMemoryAccessCmdArray [] = SBE_FENCE_AT_CONTINUOUS_IPL, }, + {sbeGetOccSram, + SBE_CMD_GETSRAM_OCC, + SBE_FENCE_AT_CONTINUOUS_IPL, + }, + + {sbePutOccSram, + SBE_CMD_PUTSRAM_OCC, + SBE_FENCE_AT_CONTINUOUS_IPL, + }, }; ////////////////////////////////////////////////////////////// @@ -176,6 +186,9 @@ uint8_t sbeValidateCmdClass (const uint8_t i_cmdClass, l_numCmds = sbeGetCmdStructAttr (i_cmdClass, &l_pCmd); if (!l_numCmds) { + SBE_ERROR(SBE_FUNC"SBE_SEC_COMMAND_CLASS_NOT_SUPPORTED " + "i_cmdClass[0x%02X], i_cmdOpcode[0x%02X]", + i_cmdClass, i_cmdOpcode); // Command class not supported l_rc = SBE_SEC_COMMAND_CLASS_NOT_SUPPORTED; break; diff --git a/sbe/sbefw/sbecmdsram.C b/sbe/sbefw/sbecmdsram.C new file mode 100644 index 00000000..8a3065a1 --- /dev/null +++ b/sbe/sbefw/sbecmdsram.C @@ -0,0 +1,333 @@ +/* + * @file: ppe/sbe/sbefw/sbecmdsram.C + * + * @brief This file contains the SBE Sram Access chipOps + * + */ + +#include "sbecmdsram.H" +#include "sbefifo.H" +#include "sbe_sp_intf.H" +#include "sbetrace.H" +#include "sbeFifoMsgUtils.H" + +#include "fapi2.H" +#include "p9_pm_ocb_init.H" +#include "p9_pm_ocb_indir_setup_linear.H" +#include "p9_pm_ocb_indir_access.H" +#include "p9_perv_scom_addresses.H" + +using namespace fapi2; + + +/////////////////////////////////////////////////////////////////////// +// @brief sbeOccSramAccess_Wrap Occ Sran Access Wrapper function +// +// @param [in] i_isGetFlag Flag to indicate the sram Access Type +// true : GetOccSram ChipOp +// false : PutOccSram ChipOp +// +// @return RC from the underlying FIFO utility +/////////////////////////////////////////////////////////////////////// +uint32_t sbeOccSramAccess_Wrap(const bool i_isGetFlag) +{ + #define SBE_FUNC " sbeOccSramAccess_Wrap " + SBE_ENTER(SBE_FUNC); + + uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; + + ReturnCode l_fapiRc = FAPI2_RC_SUCCESS; + + sbeRespGenHdrWithLen_t l_respHdr; + l_respHdr.init(); + sbeResponseFfdc_t l_ffdc; + + // Total Returned length from the procedure + uint32_t l_totalReturnLen = 0; + + // Create the req struct for the OCC Sram Chip-op + sbeOccSramAccessReqMsgHdr_t l_req = {0}; + + // Check if True - Get / False - Put + p9ocb::PM_OCB_ACCESS_OP l_ocb_access = + (i_isGetFlag)? p9ocb::OCB_GET : p9ocb::OCB_PUT; + + do + { + // Do a SCOM on Register PERV_SCRATCH_REGISTER_3_SCOM for Bit3 + // to know if Fsp is attached + // This can be a attribute read or to refer a global value. + // TODO - RTC:120752 + uint64_t l_scratchReg3data = 0; + bool l_isFspAttached = false; + l_rc = getscom_abs(PERV_SCRATCH_REGISTER_3_SCOM, &l_scratchReg3data); + if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc) + { + SBE_ERROR(SBE_FUNC "getscom_abs failed for " + "PERV_SCRATCH_REGISTER_3_SCOM l_rc [0x%08X]", l_rc); + break; + } + + // Fetch the Bit3 + if(l_scratchReg3data & SBE_FWCTRLFLG3_FSP_ATTACHED) + { + l_isFspAttached = true; + } + + // Get the Req Struct Size Data from upstream Fifo + uint32_t l_len2dequeue = sizeof(l_req) / sizeof(uint32_t); + l_rc = sbeUpFifoDeq_mult (l_len2dequeue, + (uint32_t *)&l_req, + i_isGetFlag); + + // If FIFO failure + if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc) + { + // Let command processor routine to handle the RC. + break; + } + + SBE_DEBUG("mode [0x%08X] addr[0x%08X] len[0x%08X]", + l_req.mode, l_req.addr, l_req.len); + + // Get the Proc Chip Target to be passed in to the procedure call + Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc = plat_getChipTarget(); + + // Do linear setup for indirect access HWP for Chan0, Chan2 and Chan3 + // For Circular Mode, Chan1 is assumed to be setup by default + // Linear mode is setup with Linear streaming mode only + + // Sram Access condition to pass valid address during the first access + bool l_validAddrForFirstAccess = true; + + // Channel Selection based on Mode as well as Fsp attchament + p9ocb::PM_OCB_CHAN_NUM l_chan = p9ocb::OCB_CHAN0; + switch(l_req.mode) + { + case NORMAL_MODE: + if(!l_isFspAttached) + { + l_chan = p9ocb::OCB_CHAN2; + } + break; + + case DEBUG_MODE: + l_chan = p9ocb::OCB_CHAN3; + break; + + case CIRCULAR_MODE: + l_chan = p9ocb::OCB_CHAN1; + l_validAddrForFirstAccess = false; + break; + + default: + SBE_ERROR(SBE_FUNC "Invalid Mode Passed by User"); + l_rc = SBE_SEC_GENERIC_FAILURE_IN_EXECUTION; + l_respHdr.respHdr.setStatus( SBE_PRI_INVALID_DATA, l_rc); + break; + } + if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc) + { + break; + } + + // Setup Needs to be called in Normal and Debug Mode only + if( (l_req.mode == NORMAL_MODE) || (l_req.mode == DEBUG_MODE) ) + { + l_fapiRc = p9_pm_ocb_indir_setup_linear(l_proc, l_chan, + p9ocb::OCB_TYPE_LINSTR, + l_req.addr); + if(l_fapiRc != FAPI2_RC_SUCCESS) + { + SBE_ERROR(SBE_FUNC "p9_pm_ocb_indir_setup_linear failed, " + "Channel[0x%02X] Addr[0x%08X]", + l_chan, l_req.addr); + + // Respond with HWP FFDC + l_respHdr.respHdr.setStatus(SBE_PRI_GENERIC_EXECUTION_FAILURE, + SBE_SEC_GENERIC_FAILURE_IN_EXECUTION); + l_ffdc.setRc(l_fapiRc); + break; + } + } + + //Create a 128 Byte Buffer - 16 64-Bit buffer + // This is our Granule size as well for this HWP + uint32_t l_getBuf[SBE_OCC_SRAM_GRANULE/SBE_32BIT_ALIGN_FACTOR] = {}; + uint32_t l_remainingLen = l_req.len; // Initialize with Total Len + uint32_t l_lenPassedToHwp = 0; + uint32_t l_actLen = 0; // Return Len from Hwp not used + + while(l_remainingLen) + { + if(l_remainingLen <= SBE_OCC_SRAM_GRANULE) + { + l_lenPassedToHwp = l_remainingLen; + } + else + { + l_lenPassedToHwp = SBE_OCC_SRAM_GRANULE; + } + l_remainingLen = l_remainingLen - l_lenPassedToHwp; + + // Fetch buffer from Upstream Fifo for the HWP if it is PutOCC Sram + if(!i_isGetFlag) + { + l_len2dequeue = (l_lenPassedToHwp/SBE_32BIT_ALIGN_FACTOR); + l_rc = sbeUpFifoDeq_mult ( l_len2dequeue, + l_getBuf, + false); + // If there was an underlying FIFO operation failure + if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc) + { + // Let command processor routine to handle the RC. + break; + } + } + + // Don't need to put any check for Linear/Circular - It's the same + // API for access, For circular valid address flag is false, Hwp + // doesn't need the address field from us. + l_fapiRc = p9_pm_ocb_indir_access( + l_proc, + l_chan, + l_ocb_access, // Get/Put + (l_lenPassedToHwp/SBE_64BIT_ALIGN_FACTOR), // 64-bit aligned + l_validAddrForFirstAccess, // If requested addr is valid + l_req.addr, // Requested Addr being passed + l_actLen, // O/p from hwp not used + (uint64_t *)l_getBuf); // O/p buffer + if(l_fapiRc != FAPI2_RC_SUCCESS) + { + SBE_ERROR(SBE_FUNC "p9_pm_ocb_indir_access failed, " + "Channel[0x%02X] Addr[0x%08X] 64Bit Aligned Len[0x%08X]", + l_chan, l_req.addr, (l_lenPassedToHwp/SBE_64BIT_ALIGN_FACTOR)); + + // Respond with HWP FFDC + l_respHdr.respHdr.setStatus(SBE_PRI_GENERIC_EXECUTION_FAILURE, + SBE_SEC_GENERIC_FAILURE_IN_EXECUTION); + l_ffdc.setRc(l_fapiRc); + break; + } + + l_totalReturnLen = l_totalReturnLen + l_lenPassedToHwp; + // Change this to false, so that Indirect Access Hwp doesn't + // reset the Address to starting point. + l_validAddrForFirstAccess = false; + + if(i_isGetFlag) // Get Occ Sram + { + l_len2dequeue = (l_lenPassedToHwp/SBE_32BIT_ALIGN_FACTOR); + // Push this into the downstream FIFO + l_rc = sbeDownFifoEnq_mult (l_len2dequeue, l_getBuf); + + // If FIFO failure + if (SBE_SEC_OPERATION_SUCCESSFUL != l_rc) + { + // Let command processor routine to handle the RC. + break; + } + } + } // End of while Put/Get from Hwp + + // If there was a FIFO error, will skip sending the response, + // instead give the control back to the command processor thread + if ( SBE_SEC_OPERATION_SUCCESSFUL != l_rc ) + { + break; + } + + do + { + l_len2dequeue = 0; + if (!i_isGetFlag) + { + // If there was a HWP failure for put sram occ request, + // need to Flush out upstream FIFO, until EOT arrives + if ( l_fapiRc != FAPI2_RC_SUCCESS ) + { + l_rc = sbeUpFifoDeq_mult(l_len2dequeue, NULL, + true, true); + if ( SBE_SEC_OPERATION_SUCCESSFUL != l_rc ) + { + break; + } + } + // For other success paths, just attempt to offload + // the next entry, which is supposed to be the EOT entry + else + { + l_rc = sbeUpFifoDeq_mult(l_len2dequeue, NULL, true); + if ( SBE_SEC_OPERATION_SUCCESSFUL != l_rc ) + { + break; + } + } + } + + // Distance to Header is minus the length field in the response + // buffer. So when we do sizeof(l_respHdr) It will add an extra byte + // for the length. So it compensates for the length, if we start the + // distance from hdr as zero. + uint32_t l_dist2Hdr = 0; + + // Now enqueue the minimum response header + // first enqueue the length of data actually written + l_respHdr.setLength(l_totalReturnLen); + uint32_t l_len = sizeof(l_respHdr) / sizeof(uint32_t); + l_rc = sbeDownFifoEnq_mult(l_len, (uint32_t *)(&l_respHdr)); + + if ( SBE_SEC_OPERATION_SUCCESSFUL != l_rc ) + { + break; + } + + l_dist2Hdr += l_len; + + // Enqueue FFDC data if there is one + if( l_ffdc.getRc() ) + { + l_len = sizeof(l_ffdc) / sizeof(uint32_t); + l_rc = sbeDownFifoEnq_mult (l_len, (uint32_t *)(&l_ffdc)); + if ( SBE_SEC_OPERATION_SUCCESSFUL != l_rc ) + { + break; + } + + l_dist2Hdr += l_len; + } + + l_len = sizeof(l_dist2Hdr) / sizeof(uint32_t); + l_rc = sbeDownFifoEnq_mult ( l_len, &l_dist2Hdr); + + if ( SBE_SEC_OPERATION_SUCCESSFUL != l_rc ) + { + break; + } + }while(0); + }while(0); + + SBE_EXIT(SBE_FUNC); + return l_rc; + #undef SBE_FUNC +} + + +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +uint32_t sbePutOccSram (uint8_t *i_pArg) +{ + #define SBE_FUNC " sbePutOccSram " + return sbeOccSramAccess_Wrap (false); + #undef SBE_FUNC +} + +///////////////////////////////////////////////////// +////////////////////////////////////////////////////// +uint32_t sbeGetOccSram (uint8_t *i_pArg) +{ + #define SBE_FUNC " sbeGetOccSram " + return sbeOccSramAccess_Wrap (true); + #undef SBE_FUNC +} + diff --git a/sbe/sbefw/sbecmdsram.H b/sbe/sbefw/sbecmdsram.H new file mode 100644 index 00000000..1dbc87e1 --- /dev/null +++ b/sbe/sbefw/sbecmdsram.H @@ -0,0 +1,41 @@ +/* + * @file: ppe/sbe/sbefw/sbecmdsram.H + * + * @brief This file contains the Interfaces for the Sram Access chip-ops + * + */ + +#ifndef __SBEFW_SBECMDSRAM_H +#define __SBEFW_SBECMDSRAM_H + +#include <stdint.h> + +static const uint8_t SBE_32BIT_ALIGN_FACTOR = 4; +static const uint8_t SBE_64BIT_ALIGN_FACTOR = 8; + +static const uint64_t SBE_FWCTRLFLG3_FSP_ATTACHED = 0X1000000000000000; + +/* + * @brief Granule size in Bytes for 'Get from Hwp'/'Put to Hwp' + */ +static const uint32_t SBE_OCC_SRAM_GRANULE = 128; + +/** + * @brief sbeGetOccSram : Implements SBE Get Occ Sram ChipOp + * + * @param[in] i_pArg Buffer to be passed to the function (not used as of now) + * + * @return Rc from the FIFO access utility + */ +uint32_t sbeGetOccSram (uint8_t *i_pArg); + +/** + * @brief sbePutOccSram : Implements SBE Put Occ Sram ChipOp + * + * @param[in] i_pArg Buffer to be passed to the function (not used as of now) + * + * @return Rc from the FIFO access utility + */ +uint32_t sbePutOccSram (uint8_t *i_pArg); + +#endif /* __SBEFW_SBECMDSRAM_H */ diff --git a/sbe/sbefw/sbefwfiles.mk b/sbe/sbefw/sbefwfiles.mk index b537dff4..00b79328 100644 --- a/sbe/sbefw/sbefwfiles.mk +++ b/sbe/sbefw/sbefwfiles.mk @@ -12,7 +12,7 @@ SBEFW-CPP-SOURCES += attr.C SBEFW-CPP-SOURCES += sbecmdmemaccess.C SBEFW-CPP-SOURCES += sbeHostUtils.C SBEFW-CPP-SOURCES += sbecmdcntrldmt.C - +SBEFW-CPP-SOURCES += sbecmdsram.C SBEFW-C-SOURCES = SBEFW-S-SOURCES = diff --git a/sbe/test/test.xml b/sbe/test/test.xml index d8ad0a2c..ce3ee1e1 100755 --- a/sbe/test/test.xml +++ b/sbe/test/test.xml @@ -32,6 +32,7 @@ <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include> <include>../simics/targets/p9_nimbus/sbeTest/testGeneric.xml</include> <include>../simics/targets/p9_nimbus/sbeTest/testPutGetMem.xml</include> + <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include> <testcase> <simcmd>sbe-trace</simcmd> </testcase> diff --git a/sbe/test/testGetCapabilities.py b/sbe/test/testGetCapabilities.py index 8fa9d241..d7616eb7 100755 --- a/sbe/test/testGetCapabilities.py +++ b/sbe/test/testGetCapabilities.py @@ -15,7 +15,7 @@ EXPDATA1 = [0x0,0x0,0x0,0x0, 0x0,0x0,0x0,0x0, 0x00,0x0,0x0,0x0]; -EXPDATA2 = [0xa4,0x0,0x0,0x03, +EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc 0x0,0x0,0x0,0x0, 0x0,0x0,0x0,0x0, 0x0,0x0,0x0,0x0, diff --git a/sbe/test/testSram.py b/sbe/test/testSram.py new file mode 100644 index 00000000..2ffa35ee --- /dev/null +++ b/sbe/test/testSram.py @@ -0,0 +1,106 @@ +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +LOOP_COUNT = 1 + +PUTSRAM_OCC_CNTLDATA = [0,0,0,0x20, + 0,0,0xa4,0x04, #magic + 0,0,0,0x01, + 0xe7,0xf0,0x00,0x00, #addr + 0,0,0x01,0x00] # length + +PUTSRAM_OCC_TESTDATA = [0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9, + 0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9] + +PUTSRAM_OCC_EXP_CNTLDATA = [0,0,0x01,0x00, + 0xc0,0xde,0xa4,0x04, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03] + +GETSRAM_OCC_CNTLDATA = [0,0,0,0x5, + 0,0,0xa4,0x03, + 0,0,0,0x01, + 0xe7,0xf0,0x00,0x00, #address + 0x00,0x00,0x01,0x00] # length of data + +GETSRAM_OCC_EXP_TESTDATA = [0xab,0xcd,0xef,0x12, #data + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9, + 0xab,0xcd,0xef,0x12, + 0xba,0xdc,0xfe,0x21, + 0x34,0x56,0x78,0x9a, + 0x43,0x65,0x87,0xa9] + +GETSRAM_OCC_EXP_CNTLDATA = [0x00,0x00,0x01,0x00, # length + 0xc0,0xde,0xa4,0x03, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + # Put Occ Sram test - Linear - Can be tested over Normal + # Debug mode + testUtil.writeUsFifo( PUTSRAM_OCC_CNTLDATA ) + # Write 32 bytes of data 8 times => 32*8 = 256 = 0x100 + i_cnt = 0 + while i_cnt < 8: + testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA ) + i_cnt = i_cnt+1 + + testUtil.writeEot( ) + + # Read the expected data for put sram + testUtil.readDsFifo( PUTSRAM_OCC_EXP_CNTLDATA ) + testUtil.readEot( ) + + # Get Sram Linear + testUtil.writeUsFifo( GETSRAM_OCC_CNTLDATA ) + testUtil.writeEot( ) + + # Read the Expected Data for get Sram + i_cnt = 0 + while i_cnt < 8: + testUtil.readDsFifo( GETSRAM_OCC_EXP_TESTDATA ) + i_cnt = i_cnt+1 + + testUtil.readDsFifo( GETSRAM_OCC_EXP_CNTLDATA ) + testUtil.readEot( ) + + # Put Occ Sram test - Circular - Can be enabled once we get + # valid address range to read the circular data + #testUtil.writeUsFifo( PUTSRAM_OCC_TESTDATA_1 ) + #testUtil.writeEot( ) + #testUtil.readDsFifo( PUTSRAM_OCC_EXPDATA_1 ) + #testUtil.readEot( ) + #testUtil.writeUsFifo( GETSRAM_OCC_TESTDATA_1 ) + #testUtil.writeEot( ) + #testUtil.readDsFifo( GETSRAM_OCC_EXPDATA_1 ) + #testUtil.readEot( ) + + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/sbe/test/testSram.xml b/sbe/test/testSram.xml new file mode 100755 index 00000000..b44ddb6d --- /dev/null +++ b/sbe/test/testSram.xml @@ -0,0 +1,8 @@ +<?xml version="1.0" encoding="UTF-8"?> + + <testcase> + <!-- TODO RTC - 150091 - Add the Occ sram test case --> + <!--<simcmd>run-python-file targets/p9_nimbus/sbeTest/testSram.py</simcmd>--> + <!--<exitonerror>yes</exitonerror>--> + </testcase> + |