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author | Doug Gilbert <dgilbert@us.ibm.com> | 2015-08-27 12:38:58 -0500 |
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committer | Gregory S. Still <stillgs@us.ibm.com> | 2015-09-09 16:44:50 -0500 |
commit | 725a94495556190df093c41182fcccf0fe03e313 (patch) | |
tree | f420a47056d46fe96365d94212f6420272ed1506 /pk/ppe42/ppe42_exceptions.S | |
parent | 5006e40fa94b9cc33e8b03a11de5accee9773193 (diff) | |
download | talos-sbe-725a94495556190df093c41182fcccf0fe03e313.tar.gz talos-sbe-725a94495556190df093c41182fcccf0fe03e313.zip |
Remove unsupported sc instruction in PPE-Kernel
Change-Id: Icc11444905cd1333701980b49980139f96656bd7
CQ: HW326920
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20173
Tested-by: Jenkins Server
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Claus Michael Olsen <cmolsen@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'pk/ppe42/ppe42_exceptions.S')
-rw-r--r-- | pk/ppe42/ppe42_exceptions.S | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/pk/ppe42/ppe42_exceptions.S b/pk/ppe42/ppe42_exceptions.S index 272c0e41..f8f68d99 100644 --- a/pk/ppe42/ppe42_exceptions.S +++ b/pk/ppe42/ppe42_exceptions.S @@ -201,21 +201,8 @@ dec_handler: b check_for_ext_interrupt program_exception_handler: - ## first check if exception was caused by an illegal 'sc' instruction - mfspr %r3, SPRN_EDR - _liw %r4, PPE42_SC_INST - cmpwbeq %r3, %r4, __sc_helper _pk_panic PPE42_ILLEGAL_INSTRUCTION - ## Saved SRR0 is currently pointing to the 'sc' instruction. We need to advance it - ## to the next instruction so that we don't end up in an endless loop (something - ## that the ppc sc instruction does automatically). -__sc_helper: - mfsrr0 %r4 - _lwzsd %r3, __pk_saved_sp - addi %r4, %r4, 4 - stw %r4, PK_CTX_SRR0(%r3) - .global __pk_next_thread_resume __pk_next_thread_resume: @@ -305,6 +292,23 @@ ctx_discard: ## (r3, r4, lr, and cr have already been saved for us) and ## r3 contains the interrupted kernel context + .global __ctx_switch +__ctx_switch: + stwu %r1, -PK_CTX_SIZE(%r1) + stvd %d3, PK_CTX_GPR3(%r1) + mfcr %r3 + mflr %r4 + stvd %d3, PK_CTX_CR(%r1) + _liw %r3 __pk_next_thread_resume + mtlr %r3 + ## emulate what interrupt would do + mtsrr0 %r4 + mfmsr %r3 + mtsrr1 %r3 + + ## ctx_continue_push expects r3 to be value of sprg0 + mfsprg0 %r3 + ctx_continue_push: stvd %d5, PK_CTX_GPR5(%r1) @@ -488,7 +492,7 @@ ctx_pop: lvd %d5, PK_CTX_GPR5(%r1) lvd %d3, PK_CTX_CR(%r1) mtlr %r4 - mtcr %r3 + mtcr0 %r3 lvd %d3, PK_CTX_GPR3(%r1) addi %r1, %r1, PK_CTX_SIZE |