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authorDoug Gilbert <dgilbert@us.ibm.com>2015-08-27 12:38:58 -0500
committerGregory S. Still <stillgs@us.ibm.com>2015-09-09 16:44:50 -0500
commit725a94495556190df093c41182fcccf0fe03e313 (patch)
treef420a47056d46fe96365d94212f6420272ed1506 /pk
parent5006e40fa94b9cc33e8b03a11de5accee9773193 (diff)
downloadtalos-sbe-725a94495556190df093c41182fcccf0fe03e313.tar.gz
talos-sbe-725a94495556190df093c41182fcccf0fe03e313.zip
Remove unsupported sc instruction in PPE-Kernel
Change-Id: Icc11444905cd1333701980b49980139f96656bd7 CQ: HW326920 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20173 Tested-by: Jenkins Server Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Claus Michael Olsen <cmolsen@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Diffstat (limited to 'pk')
-rw-r--r--pk/ppe42/ppe42.h12
-rw-r--r--pk/ppe42/ppe42_exceptions.S32
2 files changed, 22 insertions, 22 deletions
diff --git a/pk/ppe42/ppe42.h b/pk/ppe42/ppe42.h
index ecc990e3..35d57bad 100644
--- a/pk/ppe42/ppe42.h
+++ b/pk/ppe42/ppe42.h
@@ -464,11 +464,6 @@ do {*(volatile uint32_t *)(addr) = (data);} while(0)
#define PPE42_RESET_TRAP 0
#endif
-// PPE42 doesn't support the system call instruction so we use this illegal
-// instruction to force a program exception which then emulates the system call
-// instruction.
-#define PPE42_SC_INST 0x44000002
-
#ifndef __ASSEMBLER__
/// The PPE42 PK machine context is simply the MSR, a 32-bit integer.
@@ -547,9 +542,10 @@ pk_machine_context_get(PkMachineContext *context)
return PK_OK;
}
-/// The PK kernel thread context switch - PPE42 uses the 'sc' illegal instruction
-/// to force a program exception to occur.
-#define __pk_switch() asm volatile (".long 0x44000002")
+extern void __ctx_switch();
+/// The PK context switch for the PPE kernel
+// There is no protected mode in PPE42 so just call kernel code
+#define __pk_switch() __ctx_switch()
/// In the PowerPC EABI all initial stack frames require 8 bytes - the 4 bytes
diff --git a/pk/ppe42/ppe42_exceptions.S b/pk/ppe42/ppe42_exceptions.S
index 272c0e41..f8f68d99 100644
--- a/pk/ppe42/ppe42_exceptions.S
+++ b/pk/ppe42/ppe42_exceptions.S
@@ -201,21 +201,8 @@ dec_handler:
b check_for_ext_interrupt
program_exception_handler:
- ## first check if exception was caused by an illegal 'sc' instruction
- mfspr %r3, SPRN_EDR
- _liw %r4, PPE42_SC_INST
- cmpwbeq %r3, %r4, __sc_helper
_pk_panic PPE42_ILLEGAL_INSTRUCTION
- ## Saved SRR0 is currently pointing to the 'sc' instruction. We need to advance it
- ## to the next instruction so that we don't end up in an endless loop (something
- ## that the ppc sc instruction does automatically).
-__sc_helper:
- mfsrr0 %r4
- _lwzsd %r3, __pk_saved_sp
- addi %r4, %r4, 4
- stw %r4, PK_CTX_SRR0(%r3)
-
.global __pk_next_thread_resume
__pk_next_thread_resume:
@@ -305,6 +292,23 @@ ctx_discard:
## (r3, r4, lr, and cr have already been saved for us) and
## r3 contains the interrupted kernel context
+ .global __ctx_switch
+__ctx_switch:
+ stwu %r1, -PK_CTX_SIZE(%r1)
+ stvd %d3, PK_CTX_GPR3(%r1)
+ mfcr %r3
+ mflr %r4
+ stvd %d3, PK_CTX_CR(%r1)
+ _liw %r3 __pk_next_thread_resume
+ mtlr %r3
+ ## emulate what interrupt would do
+ mtsrr0 %r4
+ mfmsr %r3
+ mtsrr1 %r3
+
+ ## ctx_continue_push expects r3 to be value of sprg0
+ mfsprg0 %r3
+
ctx_continue_push:
stvd %d5, PK_CTX_GPR5(%r1)
@@ -488,7 +492,7 @@ ctx_pop:
lvd %d5, PK_CTX_GPR5(%r1)
lvd %d3, PK_CTX_CR(%r1)
mtlr %r4
- mtcr %r3
+ mtcr0 %r3
lvd %d3, PK_CTX_GPR3(%r1)
addi %r1, %r1, PK_CTX_SIZE
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