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author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-05-04 12:28:25 +0200 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-05-05 01:18:54 -0400 |
commit | c90202f245da58039853e8193d028fe9eb483f9f (patch) | |
tree | ce44d9381355deadad2bc53c8f6a7dad9776912d /import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | |
parent | ccade972b384204fd6f0be112d2715ecd2cd5be8 (diff) | |
download | talos-sbe-c90202f245da58039853e8193d028fe9eb483f9f.tar.gz talos-sbe-c90202f245da58039853e8193d028fe9eb483f9f.zip |
IPL optimized codes
Change-Id: I60bd09be22ae75561667253204ffd33c6fdeb58d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24060
Tested-by: Jenkins Server
Tested-by: PPE CI
Tested-by: Hostboot CI
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24061
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/perv/p9_sbe_common.C')
-rw-r--r-- | import/chips/p9/procedures/hwp/perv/p9_sbe_common.C | 212 |
1 files changed, 97 insertions, 115 deletions
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index dbdb7dc6..5952d1ee 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,10 +32,12 @@ //## auto_generated #include "p9_sbe_common.H" +//## auto_generated #include "p9_const_common.H" -#include "p9_misc_scom_addresses_fld.H" -#include "p9_perv_scom_addresses.H" +#include <p9_perv_scom_addresses.H> +#include <p9_perv_scom_addresses_fld.H> +#include <p9_const_common.H> enum P9_SBE_COMMON_Private_Constants @@ -58,39 +60,39 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const { fapi2::buffer<uint64_t> l_data64; int l_timeout = 0; - FAPI_DBG("Entering ..."); + FAPI_INF("Entering ..."); - FAPI_INF("For all chiplets: exit flush"); + FAPI_DBG("For all chiplets: exit flush"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 - l_data64.setBit<PEC_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); - FAPI_INF("For all chiplets: enable alignement"); + FAPI_DBG("For all chiplets: enable alignement"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 1 - l_data64.setBit<PEC_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64)); - FAPI_INF("Clear chiplet is aligned"); + FAPI_DBG("Clear chiplet is aligned"); //Setting SYNC_CONFIG register value FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b1 - l_data64.setBit<PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); + l_data64.setBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); - FAPI_INF("unset clear chiplet is aligned" ); + FAPI_DBG("Unset Clear chiplet is aligned"); //Setting SYNC_CONFIG register value FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b0 - l_data64.clearBit<PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); + l_data64.clearBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64)); fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY); - FAPI_INF("Poll OPCG done bit to check for run-N completeness"); + FAPI_DBG("Poll OPCG done bit to check for run-N completeness"); l_timeout = CPLT_ALIGN_CHECK_POLL_COUNT; //UNTIL CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC == 1 @@ -99,7 +101,7 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const //Getting CPLT_STAT0 register value FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64)); bool l_poll_data = - l_data64.getBit<PEC_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC + l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC>(); //bool l_poll_data = CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC if (l_poll_data == 1) { @@ -110,26 +112,65 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const --l_timeout; } - FAPI_INF("Loop Count :%d", l_timeout); + FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, fapi2::CPLT_NOT_ALIGNED_ERR(), "ERROR:CHIPLET NOT ALIGNED"); - FAPI_INF("For all chiplets: disable alignement"); + FAPI_DBG("For all chiplets: disable alignement"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 0 - l_data64.setBit<PEC_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>(); FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64)); - FAPI_DBG("Exiting ..."); + FAPI_INF("Exiting ..."); fapi_try_exit: return fapi2::current_err; } +/// @brief check clocks status +/// +/// @param[in] i_regions regions from upper level input +/// @param[in] i_clock_status clock status +/// @param[in] i_reg bit status +/// @param[in] i_clock_cmd clock command +/// @param[out] o_exp_clock_status expected clock status +/// @return FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer<uint64_t> + i_regions, + const fapi2::buffer<uint64_t> i_clock_status, + const bool i_reg, + const fapi2::buffer<uint8_t> i_clock_cmd, + fapi2::buffer<uint64_t>& o_exp_clock_status) +{ + FAPI_INF("Entering ..."); + + if ( (i_reg) && (i_clock_cmd == 0b01) ) + { + o_exp_clock_status = i_clock_status & (~(i_regions << 49)); + } + else + { + if ( (i_reg) && (i_clock_cmd == 0b10) ) + { + o_exp_clock_status = i_clock_status | (i_regions << 49); + } + else + { + o_exp_clock_status = i_clock_status; + } + } + + FAPI_INF("Exiting ..."); + + return fapi2::FAPI2_RC_SUCCESS; + +} + /// @brief --Setting Clock Region Register /// --Reading Clock status /// @@ -141,14 +182,14 @@ fapi2::ReturnCode p9_sbe_common_clock_start_allRegions(const fapi2::buffer<uint64_t> l_sl_clock_status; fapi2::buffer<uint64_t> l_nsl_clock_status; fapi2::buffer<uint64_t> l_ary_clock_status; - FAPI_DBG("Entering ..."); + FAPI_INF("Entering ..."); - FAPI_INF("Start remaining pervasive clocks (beyond PIB & NET)"); + FAPI_DBG("Start remaining pervasive clocks (beyond PIB & NET)"); //Setting CLK_REGION register value //CLK_REGION = CLK_REGION_VALUE FAPI_TRY(fapi2::putScom(i_anychiplet, PERV_CLK_REGION, CLK_REGION_VALUE)); - FAPI_INF("Check for clocks running (SL , NSL , ARY)"); + FAPI_DBG("Check for clocks running (SL , NSL , ARY)"); //Getting CLOCK_STAT_SL register value FAPI_TRY(fapi2::getScom(i_anychiplet, PERV_CLOCK_STAT_SL, l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL @@ -174,7 +215,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_allRegions(const .set_READ_CLK_ARY(l_ary_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); - FAPI_DBG("Exiting ..."); + FAPI_INF("Exiting ..."); fapi_try_exit: return fapi2::current_err; @@ -207,29 +248,33 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const fapi2::buffer<uint64_t> l_exp_nsl_clock_status; fapi2::buffer<uint64_t> l_exp_ary_clock_status; fapi2::buffer<uint8_t> l_clk_cmd; + fapi2::buffer<uint16_t> l_regions; + fapi2::buffer<uint8_t> l_reg_all; bool l_reg_sl = false; bool l_reg_nsl = false; bool l_reg_ary = false; fapi2::buffer<uint64_t> l_data64; - FAPI_DBG("Entering ..."); + FAPI_INF("Entering ..."); + i_regions.extractToRight<53, 11>(l_regions); + i_clock_types.extractToRight<5, 3>(l_reg_all); l_reg_sl = i_clock_types.getBit<5>(); l_reg_nsl = i_clock_types.getBit<6>(); l_reg_ary = i_clock_types.getBit<7>(); - FAPI_INF("Chiplet exit flush"); + FAPI_DBG("Chiplet exit flush"); //Setting CPLT_CTRL0 register value l_data64.flush<0>(); //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1 - l_data64.setBit<PEC_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); + l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>(); FAPI_TRY(fapi2::putScom(i_target, PERV_CPLT_CTRL0_OR, l_data64)); - FAPI_INF("Clear Scan region type register"); + FAPI_DBG("Clear Scan region type register"); //Setting SCAN_REGION_TYPE register value //SCAN_REGION_TYPE = 0 FAPI_TRY(fapi2::putScom(i_target, PERV_SCAN_REGION_TYPE, 0)); - FAPI_INF("Reading the initial status of clock controller"); + FAPI_DBG("Reading the initial status of clock controller"); //Getting CLOCK_STAT_SL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL @@ -239,48 +284,24 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const //Getting CLOCK_STAT_ARY register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY - FAPI_INF("Clock status of SL_Register:%#018lX NSL_Register:%#018lX ARY_Register:%#018lX", + FAPI_DBG("Clock status of SL_Register:%#018lX NSL_Register:%#018lX ARY_Register:%#018lX", l_sl_clock_status, l_nsl_clock_status, l_ary_clock_status); i_clock_cmd.extractToRight<6, 2>(l_clk_cmd); - FAPI_INF("Setup all Clock Domains and Clock Types"); + FAPI_DBG("Setup all Clock Domains and Clock Types"); //Setting CLK_REGION register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLK_REGION, l_data64)); - l_data64.insertFromRight<PEC_CLK_REGION_CLOCK_CMD, PEC_CLK_REGION_CLOCK_CMD_LEN> + l_data64.insertFromRight<PERV_1_CLK_REGION_CLOCK_CMD, PERV_1_CLK_REGION_CLOCK_CMD_LEN> (l_clk_cmd); //CLK_REGION.CLOCK_CMD = l_clk_cmd //CLK_REGION.SLAVE_MODE = i_startslave - l_data64.writeBit<PEC_CLK_REGION_SLAVE_MODE>(i_startslave); + l_data64.writeBit<PERV_1_CLK_REGION_SLAVE_MODE>(i_startslave); //CLK_REGION.MASTER_MODE = i_startmaster - l_data64.writeBit<PEC_CLK_REGION_MASTER_MODE>(i_startmaster); - //CLK_REGION.CLOCK_REGION_PERV = i_regions.getBit<53>() - l_data64.writeBit<4>(i_regions.getBit<53>()); - //CLK_REGION.CLOCK_REGION_UNIT1 = i_regions.getBit<54>() - l_data64.writeBit<5>(i_regions.getBit<54>()); - //CLK_REGION.CLOCK_REGION_UNIT2 = i_regions.getBit<55>() - l_data64.writeBit<6>(i_regions.getBit<55>()); - //CLK_REGION.CLOCK_REGION_UNIT3 = i_regions.getBit<56>() - l_data64.writeBit<7>(i_regions.getBit<56>()); - //CLK_REGION.CLOCK_REGION_UNIT4 = i_regions.getBit<57>() - l_data64.writeBit<8>(i_regions.getBit<57>()); - //CLK_REGION.CLOCK_REGION_UNIT5 = i_regions.getBit<58>() - l_data64.writeBit<9>(i_regions.getBit<58>()); - //CLK_REGION.CLOCK_REGION_UNIT6 = i_regions.getBit<59>() - l_data64.writeBit<10>(i_regions.getBit<59>()); - //CLK_REGION.CLOCK_REGION_UNIT7 = i_regions.getBit<60>() - l_data64.writeBit<11>(i_regions.getBit<60>()); - //CLK_REGION.CLOCK_REGION_UNIT8 = i_regions.getBit<61>() - l_data64.writeBit<12>(i_regions.getBit<61>()); - //CLK_REGION.CLOCK_REGION_UNIT9 = i_regions.getBit<62>() - l_data64.writeBit<13>(i_regions.getBit<62>()); - //CLK_REGION.CLOCK_REGION_UNIT10 = i_regions.getBit<63>() - l_data64.writeBit<14>(i_regions.getBit<63>()); - //CLK_REGION.SEL_THOLD_SL = l_reg_sl - l_data64.writeBit<PEC_CLK_REGION_SEL_THOLD_SL>(l_reg_sl); - //CLK_REGION.SEL_THOLD_NSL = l_reg_nsl - l_data64.writeBit<PEC_CLK_REGION_SEL_THOLD_NSL>(l_reg_nsl); - //CLK_REGION.SEL_THOLD_ARY = l_reg_ary - l_data64.writeBit<PEC_CLK_REGION_SEL_THOLD_ARY>(l_reg_ary); + l_data64.writeBit<PERV_1_CLK_REGION_MASTER_MODE>(i_startmaster); + //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions + l_data64.insertFromRight<4, 11>(l_regions); + //CLK_REGION.SEL_THOLD_ALL = l_reg_all + l_data64.insertFromRight<48, 3>(l_reg_all); FAPI_TRY(fapi2::putScom(i_target, PERV_CLK_REGION, l_data64)); //To do do checking only for chiplets that dont have Master-slave mode enabled @@ -289,59 +310,20 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const { // Calculating the Expected clock status - if ( (l_reg_sl) && (i_clock_cmd == 0b01) ) - { - l_exp_sl_clock_status = l_sl_clock_status & (~(i_regions << 49)); - } - else - { - if ( (l_reg_sl) && (i_clock_cmd == 0b10) ) - { - l_exp_sl_clock_status = l_sl_clock_status | (i_regions << 49); - } - else - { - l_exp_sl_clock_status = l_sl_clock_status; - } - } + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_sl_clock_status, l_reg_sl, + i_clock_cmd, l_exp_sl_clock_status)); - if ( (l_reg_nsl) && (i_clock_cmd == 0b01) ) - { - l_exp_nsl_clock_status = l_nsl_clock_status & (~(i_regions << 49)); - } - else - { - if ( (l_reg_nsl) && (i_clock_cmd == 0b10) ) - { - l_exp_nsl_clock_status = l_nsl_clock_status | (i_regions << 49); - } - else - { - l_exp_nsl_clock_status = l_nsl_clock_status; - } - } + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_nsl_clock_status, l_reg_nsl, + i_clock_cmd, l_exp_nsl_clock_status)); - if ( (l_reg_ary) && (i_clock_cmd == 0b01) ) - { - l_exp_ary_clock_status = l_ary_clock_status & (~(i_regions << 49)); - } - else - { - if ( (l_reg_ary) && (i_clock_cmd == 0b10) ) - { - l_exp_ary_clock_status = l_ary_clock_status | (i_regions << 49); - } - else - { - l_exp_ary_clock_status = l_ary_clock_status; - } - } + FAPI_TRY(p9_sbe_common_check_status(i_regions, l_ary_clock_status, l_reg_ary, + i_clock_cmd, l_exp_ary_clock_status)); - FAPI_INF("Check for clocks running SL"); + FAPI_DBG("Check for clocks running SL"); //Getting CLOCK_STAT_SL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL, l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL - FAPI_INF("Expected value is %#018lX, Actaul value is %#018lX", + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", l_exp_sl_clock_status, l_sl_clock_status); FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, @@ -349,11 +331,11 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const .set_READ_CLK_SL(l_sl_clock_status), "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); - FAPI_INF("Check for clocks running NSL"); + FAPI_DBG("Check for clocks running NSL"); //Getting CLOCK_STAT_NSL register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL, l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL - FAPI_INF("Expected value is %#018lX, Actaul value is %#018lX", + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", l_exp_nsl_clock_status, l_nsl_clock_status); FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, @@ -361,11 +343,11 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const .set_READ_CLK_NSL(l_nsl_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); - FAPI_INF("Check for clocks running ARY"); + FAPI_DBG("Check for clocks running ARY"); //Getting CLOCK_STAT_ARY register value FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY, l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY - FAPI_INF("Expected value is %#018lX, Actaul value is %#018lX", + FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX", l_exp_ary_clock_status, l_ary_clock_status); FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, @@ -374,7 +356,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); } - FAPI_DBG("Exiting ..."); + FAPI_INF("Exiting ..."); fapi_try_exit: return fapi2::current_err; @@ -389,15 +371,15 @@ fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets) { fapi2::buffer<uint64_t> l_data64; - FAPI_DBG("Entering ..."); + FAPI_INF("Entering ..."); //Setting OPCG_ALIGN register value FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64)); - l_data64.insertFromRight<PEC_OPCG_ALIGN_SCAN_RATIO, PEC_OPCG_ALIGN_SCAN_RATIO_LEN> + l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN> (0xE0); //OPCG_ALIGN.SCAN_RATIO = 0xE0 FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64)); - FAPI_DBG("Exiting ..."); + FAPI_INF("Exiting ..."); fapi_try_exit: return fapi2::current_err; |