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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2016-05-04 12:28:25 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-05-05 01:18:54 -0400 |
| commit | c90202f245da58039853e8193d028fe9eb483f9f (patch) | |
| tree | ce44d9381355deadad2bc53c8f6a7dad9776912d /import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | |
| parent | ccade972b384204fd6f0be112d2715ecd2cd5be8 (diff) | |
| download | talos-sbe-c90202f245da58039853e8193d028fe9eb483f9f.tar.gz talos-sbe-c90202f245da58039853e8193d028fe9eb483f9f.zip | |
IPL optimized codes
Change-Id: I60bd09be22ae75561667253204ffd33c6fdeb58d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24060
Tested-by: Jenkins Server
Tested-by: PPE CI
Tested-by: Hostboot CI
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24061
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H')
| -rw-r--r-- | import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index 441d1319..7867d6cf 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -26,6 +26,7 @@ /// 4) Similar way, Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode /// /// Done +/// //------------------------------------------------------------------------------ // *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> // *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com> @@ -55,7 +56,7 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants HANG_PULSE_0X10 = 0x10, HANG_PULSE_0X0F = 0x0F, HANG_PULSE_0X06 = 0x06, - HANG_PULSE_0X17 = 0x18, + HANG_PULSE_0X17 = 0x17, HANG_PULSE_0X18 = 0x18, HANG_PULSE_0X22 = 0x22, HANG_PULSE_0X13 = 0x13, @@ -80,7 +81,9 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants SCAN_RATIO_0X0 = 0x0, SYNC_CONFIG_4TO1 = 0X0800000000000000, HW_NS_DELAY = 200000, // unit is nano seconds - SIM_CYCLE_DELAY = 10000 // unit is cycles + SIM_CYCLE_DELAY = 10000, // unit is cycles + HANG_PULSE_0X12 = 0x12, + HANG_PULSE_0X1C = 0x1C }; } @@ -111,7 +114,4 @@ extern "C" fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip); } -fapi2::ReturnCode p9_sbe_chiplet_reset_pcie_iop_logic_setup( - const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip); - #endif |
