Adding in the exception vector

Change-Id: I48193600b25fa62f60b61a6a269ccbedbd96f12d
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23386
Tested-by: Jenkins Server
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24142
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

6 files changed, 223 insertions, 23 deletions

diff --git a/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
index 6ecd526b..ac1106d7 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
+++ b/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
@@ -109,13 +109,16 @@ extern "C"
     const uint32_t PBA_BAR_SCOPE_END_BIT = 2;
     const uint32_t PBA_BAR_BASE_ADDRESS_START_BIT = 8;
     const uint32_t PBA_BAR_BASE_ADDRESS_END_BIT = 43;
-    const uint32_t PBA_BAR_BASE_ADDRESS_SHIFT = 21;
+    const uint32_t PBA_BAR_BASE_ADDRESS_SHIFT = 20;
     const uint64_t PBA_BAR_BASE_ADDRESS_MASK = 0xFFFFFFFFFull;
 
 //PBA BAR Mask register field/bit definitions
     const uint32_t PBA_BAR_MASK_START_BIT = 23;
     const uint32_t PBA_BAR_MASK_END_BIT = 43;
 
+//OCB3_ADDRESS field/bit definitions
+    const uint32_t OCB3_ADDRESS_REG_ADDR_SHIFT = 32;
+
     //---------------------------------------------------------------------------------
     // Function definitions
     //---------------------------------------------------------------------------------
@@ -231,7 +234,7 @@ extern "C"
                  "Error writing to the OCB3 Status Control Register with or mask");
 
         //Write the address to OCB3_ADDRESS Register
-        ocb3_addr_data = 0xB000000000000000 | (i_address & 0x7FFFFFFull);
+        ocb3_addr_data = 0xB000000000000000 | ((i_address & 0x7FFFFFFull) << OCB3_ADDRESS_REG_ADDR_SHIFT);
         ocb3_addr.insertFromRight<0, 64>(ocb3_addr_data);
 
         FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBAR3, ocb3_addr),
@@ -454,7 +457,7 @@ extern "C"
                  "Error reading from the PBA Slave Reset Register");
 
         //If there are any errors in the Status registers that we got above, collect all of the data and send an error
-        /*FAPI_ASSERT((((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
+        FAPI_ASSERT((((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
                      && ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
                      && ((wr_buf0_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
                      && ((wr_buf1_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
@@ -463,7 +466,7 @@ extern "C"
                         rd_buf2_valid).set_RDBUF3(rd_buf3_valid).set_WRBUF0(
                         wr_buf0_valid).set_WRBUF1(wr_buf1_valid).set_SLVRSTDATA(reset_buf),
                     "Error in checking the PBA Reset, PBA Read Buffer, or PBA Write Buffer Registers");
-        */
+
     fapi_try_exit:
         FAPI_DBG("End");
         return fapi2::current_err;
diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
new file mode 100644
index 00000000..59c4a2bd
--- /dev/null
+++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H $         */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* EKB Project                                                            */
+/*                                                                        */
+/* COPYRIGHT 2016                                                         */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------------
+//
+/// @file p9_sbe_hb_structures.H
+/// @brief Structures that the SBE and HB will both use
+//
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE, HB
+//-----------------------------------------------------------------------------------
+
+#ifndef _SBE_HB_STRUCTURES_H_
+#define _SBE_HB_STRUCTURES_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+// Structure starts at the bootloader zero address
+struct BootloaderConfigData_t
+{
+    uint32_t version;  // Some kind of version field so we know if there is new data being added
+    uint8_t sbeBootSide;  // 0=SBE side 0, 1=SBE side 1   [ATTR_????]
+    uint8_t pnorBootSide;  // 0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
+    uint16_t pnorSizeMB;  // Size of PNOR in MB  [ATTR_PNOR_SIZE]
+};
+
+#endif
diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
index 4085f4e6..f794987a 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
+++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
@@ -46,7 +46,8 @@
 const bool PBA_HWP_WRITE_OP = false;
 const uint32_t PBA_HWP_FLAGS = FLAG_FASTMODE | // fastmode
                                ((p9_pba_write_ttype::LCO << FLAG_TTYPE_SHIFT) & p9_pba_flags::FLAG_TTYPE);   // LCO_M
-
+const int EXCEPTION_VECTOR_NUM_CACHELINES = 96;
+const uint32_t SBE_BOOTLOADER_VERSION = 0x901;
 //-----------------------------------------------------------------------------------
 // Function definitions
 //-----------------------------------------------------------------------------------
@@ -58,13 +59,22 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
     uint8_t* i_payload_data)
 {
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    //the branching instruction for 12KB past where it currently is (1024 * 12 = 12288 = 0x3000)
+    //The branch instruction is 0100 10_address to branch to_ 0  0
+    //                      0      6                   29 30 31
+    //bit 30 is for absolute address (since it is not set this is relative)
+    const uint32_t l_branch_to_12 = 0x4800C000ull;
     uint64_t l_bootloader_offset;
     uint64_t l_hostboot_hrmor_offset;
     uint64_t l_chip_base_address_nm;
     uint64_t l_chip_base_address_m;
     uint64_t l_target_address;
-    uint64_t l_payload_data_offset;
-    bool firstAccess = true;
+    uint32_t l_exception_instruction;
+    bool l_firstAccess = true;
+    uint32_t l_num_cachelines_to_roll;
+    uint8_t l_data_to_pass_to_pba_array[FABRIC_CACHELINE_SIZE];
+    uint32_t l_exception_vector_size = 0;
+    int l_cacheline_num = 0;
 
     FAPI_DBG("Start");
 
@@ -78,7 +88,6 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
     // target base address = (chip non-mirrored base address) +
     //                       (hostboot HRMOR offset) +
     //                       (bootloader offset)
-
     FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
              l_chip_base_address_nm,
              l_chip_base_address_m),
@@ -97,6 +106,30 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
                 set_HRMOR_OFFSET(l_hostboot_hrmor_offset).
                 set_BOOTLOADER_OFFSET(l_bootloader_offset),
                 "Target base address is not cacheline aligned!");
+
+    //Check to see if we need to populate the exception vectors
+    //Check the SBE_HBBL_EXCEPTION_INSTRUCT attribute
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT, FAPI_SYSTEM, l_exception_instruction),
+             "fapiGetAttribute of ATTR_SBE_HBBL_EXCEPTION_INSTRUCT failed!");
+
+    l_target_address = l_chip_base_address_nm;
+
+    BootloaderConfigData_t l_bootloader_config_data;
+
+    l_bootloader_config_data.version = SBE_BOOTLOADER_VERSION;
+
+    //At address X + 0x8 put whatever is in ATTR_SBE_BOOT_SIDE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.sbeBootSide),
+             "fapiGetAttribute of ATTR_SBE_BOOT_SIDE failed!");
+
+    //At address X + 0x9 put whatever is in ATTR_PNOR_BOOT_SIDE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.pnorBootSide),
+             "fapiGetAttribute of ATTR_PNOR_BOOT_SIDE failed!");
+
+    //At address X + 0xA put whatever is in ATTR_PNOR_SIZE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_SIZE, FAPI_SYSTEM, l_bootloader_config_data.pnorSizeMB),
+             "fapiGetAttribute of ATTR_PNOR_SIZE failed!");
+
     // check that the payload size is non-zero and evenly divisible into cachelines
     FAPI_ASSERT(i_payload_size && !(i_payload_size % FABRIC_CACHELINE_SIZE),
                 fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_PAYLOAD_SIZE().
@@ -106,13 +139,15 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
                 "Payload size is invalid!");
 
     // move data using PBA setup/access HWPs
-    l_target_address = l_chip_base_address_nm;
-    l_payload_data_offset = 0;
 
-    while (l_target_address < (l_chip_base_address_nm + i_payload_size))
+    if (l_exception_instruction != 0x0)
+    {
+        l_exception_vector_size = EXCEPTION_VECTOR_NUM_CACHELINES * FABRIC_CACHELINE_SIZE;
+    }
+
+    while (l_target_address < (l_chip_base_address_nm + i_payload_size + l_exception_vector_size))
     {
         // invoke PBA setup HWP to prep stream
-        uint32_t l_num_cachelines_to_roll;
         FAPI_TRY(p9_pba_setup( i_master_chip_target,
                                i_master_ex_target,
                                l_target_address,
@@ -120,31 +155,90 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
                                PBA_HWP_FLAGS,
                                l_num_cachelines_to_roll), "Error from p9_pba_setup");
 
-        firstAccess = true;
+        l_firstAccess = true;
 
         // call PBA access HWP per cacheline to move payload data
         while (l_num_cachelines_to_roll &&
-               (l_target_address < (l_chip_base_address_nm + i_payload_size)))
+               (l_target_address < (l_chip_base_address_nm + i_payload_size + l_exception_vector_size)))
         {
+            if ((l_cacheline_num == 0) && (l_exception_instruction != 0))
+            {
+                //This is for the first cacheline of data that has the branch, pnor_size, and pnor_boot_side in it
+                //The rest of the exception vector is what was in SBE_HBBL_EXCEPTION_INSTRUCT replicated multiple times (until the end of 12KB of exception vector data)
+                for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+                {
+                    //At address X put whatever is in l_branch_to_12
+                    if (i < 4)
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_branch_to_12 >> (24 - 8 * i )) & 0xFF;
+                    }
+                    //At address X + 0x4 put the HBBL_STRUCT_VERSION
+                    else if (i < 8)
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.version >> (24 - 8 * ((i - 4) % 4))) & 0xFF;
+                    }
+                    //At address X + 0x8 put the SBE_BOOT_SIDE
+                    else if (i == 8)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.sbeBootSide;
+                    }
+                    //At address X + 0x9 put the PNOR_BOOT_SIDE
+                    else if (i  == 9)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorBootSide;
+                    }
+                    //At address X + 0xA pu the PNOR_SIZE
+                    else if (i == 10)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB >> 8 & 0xFF;
+                    }
+                    else if (i == 11)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB & 0xFF;
+                    }
+                    //Fill the rest with the exception vector instruction
+                    else
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF;
+                    }
+                }
+            }
+            else if ((l_cacheline_num  == 1) && (l_exception_instruction != 0))
+            {
+                //This is for the other 95 cachelines that we are sending
+                for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+                {
+                    l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF;
+                }
+            }
+            else if ((l_cacheline_num >= EXCEPTION_VECTOR_NUM_CACHELINES) || (l_exception_instruction == 0))
+            {
+                //This is for the data after the exception vector
+                for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+                {
+                    l_data_to_pass_to_pba_array[i] = i_payload_data[((l_cacheline_num - (l_exception_vector_size / FABRIC_CACHELINE_SIZE)) *
+                                                     FABRIC_CACHELINE_SIZE)
+                                                     + i];
+                }
+            }
 
             FAPI_TRY(p9_pba_access(i_master_chip_target,
                                    l_target_address,
                                    PBA_HWP_WRITE_OP,
                                    PBA_HWP_FLAGS,
-                                   firstAccess,
+                                   l_firstAccess,
                                    (l_num_cachelines_to_roll == 1) ||
                                    ((l_target_address + FABRIC_CACHELINE_SIZE) >
-                                    (l_chip_base_address_nm + i_payload_size)),
-                                   i_payload_data + l_payload_data_offset), "Error from p9_pba_access");
-            firstAccess = false;
+                                    (l_chip_base_address_nm + i_payload_size + l_exception_vector_size)),
+                                   l_data_to_pass_to_pba_array), "Error from p9_pba_access");
+            l_firstAccess = false;
             // decrement count of cachelines remaining in current stream
             l_num_cachelines_to_roll--;
 
             // stride address/payload data pointer offset to next cacheline
             l_target_address += FABRIC_CACHELINE_SIZE;
-            l_payload_data_offset += (FABRIC_CACHELINE_SIZE / sizeof(uint8_t));
+            l_cacheline_num++;
         }
-
     }
 
 fapi_try_exit:
diff --git a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
index 6f0b5282..e4450c1e 100644
--- a/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
+++ b/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
@@ -48,7 +48,7 @@
 //-----------------------------------------------------------------------------------
 
 #include <fapi2.H>
-
+#include <p9_sbe_hb_structures.H>
 //-----------------------------------------------------------------------------------
 // Structure definitions
 //-----------------------------------------------------------------------------------
diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 9f81b576..e71d01e8 100644
--- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -528,5 +528,21 @@
   <entry>
            <name>ATTR_MASTER_EX</name>
   </entry>
-
+  <entry> 
+           <name>ATTR_PNOR_SIZE</name>
+           <value>0x00</value>
+  </entry>
+  <entry>
+           <name>ATTR_PNOR_BOOT_SIDE</name>
+           <value>0x00</value>
+  </entry>
+  <entry>
+           <name>ATTR_SBE_BOOT_SIDE</name>
+           <value>0x00</value>
+  </entry>
+  <!-- TODO we need to change this once the absolute address is known -->
+  <entry>
+           <name>ATTR_SBE_HBBL_EXCEPTION_INSTRUCT</name>
+           <value>0x48000000</value>
+  </entry>
 </entries>
diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml
index 1288bcca..84a5f8b4 100644
--- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml
+++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml
@@ -7,7 +7,7 @@
 <!--                                                                        -->
 <!-- EKB Project                                                            -->
 <!--                                                                        -->
-<!-- COPYRIGHT 2015                                                         -->
+<!-- COPYRIGHT 2015,2016                                                    -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -44,4 +44,36 @@
   <persistRuntime/>
   <platInit/>
 </attribute>
+<attribute>
+  <id>ATTR_PNOR_SIZE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines size of PNOR that will be put into the exception vector if written</description>
+  <valueType>uint16</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+<attribute>
+  <id>ATTR_SBE_BOOT_SIDE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines sbe boot side that will be put into the exception vector if written</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+<attribute>
+  <id>ATTR_PNOR_BOOT_SIDE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines boot side of PNOR that will be put into the exception vector if written</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+<attribute>
+  <id>ATTR_SBE_HBBL_EXCEPTION_INSTRUCT</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Instruction for exception vector that will be put into the exception vector if not 0</description>
+  <valueType>uint32</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
 </attributes>